Once Around the Pins

40

VCC
30 pF 19
12 MHz

XTL1 XTL2

18 30 pF

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

32 33 34 35 36 37 38 39 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

29 30 31 9

PSEN ALE EA RST

8051

17 16 15 14 13 12 11 10

P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0

VSS
20

A15 A14 A13 A12 A11 A10 A9 A8

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FIGURE 2-2 8051 pinouts

8051 Pin Functions

Port 0 Dual purpose port: 1) General purpose I/O port 2) Multiplexed address and data bus, when using external memory Port 1

Dedicated port: 1) Each pin is available for interfacing to external devices

Port 2 Dual purpose port: 1) General purpose I/O port 2) High-byte of the address bus with external code memory or external data memory greater than 256 bytes

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8051 Pin Functions con't

Port 3
Dual purpose port: 1) General purpose I/O port 2) Various functions assigned to each pin as follows:
BIT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 NAME RXD TXD INT0 INT1 T0 T1 WR RD BIT ADDRESS B0H B1H B2H B3H B4H B5H B6H B7H ALTERNATE FUNCTION Receive data for serial port Transmit data for serial port External interrupt 0 External interrupt 1 Timer/counter 0 external input Timer/counter 1 external input External data memory write strobe External data memory read strobe

PSEN (Program Store Enable) Control signal used in the fetching of an instruction When low, it enables external code memory When high, the program instructions are fetched from internal ROM 24

8051 Pin Functions con't

ALE (Address Latch Enable) Used for multiplexing the low-byte address bus and the data bus on Port 0 ALE signal latches the address into an external register during the first half of the memory cycle. This frees up the Port 0 lines in the second half of the memory cycle to be used for data input or output Since the ALE pulses regularly at 1/6th the on-chip frequency, it can be used as a general purpose clock EA (External Access) If high, 8051 executes code from internal ROM If low, code executes from external memory only (and PSEN pulses low accordingly) 25

8051 Pin Functions con't

RST (Reset) Master reset for the 8051 occurs when this signal is brought high for at least 2 machine cycles 8051 internal registers are set to default values In normal operation, RST is low On-Chip Oscillator Inputs Typically driven by a crystal using stabilizing capacitors Crystal frequency is usually 12 Mhz Can also be driven by a TTL clock source
TTL Oscillator 8051 XTAL1

XTAL2

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I/O Port Structure

8051 internal bus VCC Read latch Internal pull-up

Read pin Port pin

D Port latch Write to latch

* Open drain output for

Port 0 when operating as an I/O pin (ie. No pull-up resistor)

Write to a port pin loads data into a port latch that drives a transistor connected to the port pin Read-modify-write operations (CPL P1.5) read the latch to avoid misinterpreting the voltage level in the event the pin is heavily loaded Read operations (MOV C, P1.5) read the pin; port latch must have previously been set to a 1 otherwise the FET is ON and pulls the output low. If a port latch is cleared or a system reset occurs then it cannot function as an input unless the latch is set first (eg. SETB P1.5)

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Memory Organization
Notable features: Registers and I/O ports are memory mapped (accessible like any other memory location) Stack resides within internal RAM Internal memory is divided between: Register banks (00H-1FH) Bit-addressable RAM (20H-2FH) General-purpose RAM (30H-7FH) Special function registers (80H-FFH) 28

Byte address 7F

Bit address

Byte address FF F0 7F E0 E7 7E E6 7D E5 D5 B5 A5

Bit address 7C E4 D4 BC B4 AC A4 7B E3 D3 BB B3 7A E2 D2 BA B2 79 E1 B9 B1 78 E0 B ACC

General purpose RAM

D0 D7 D6 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 18 17 10 0F 08 07 00 B8 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 7C 75 74 6D 6C 65 64 5D 5C 55 54 4D 4C 45 44 3D 3C 35 34 2D 2C 25 24 1D 1C 15 14 0D 0C 05 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 -

D0 PSW B8 IP

B0 B7 B6 A8 AF -

B0 P3 A8 IE

AB AA A9 A5 A5 A5

Bit addressable locations

A0 A7 A6 99 98 90 8D 8C 8B 8A 89 88 87 83 82 81 80

A5 P2 SBUF SCON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0

9F 97

9E 96

Not bit addressable 9D 9C 9B 9A 95 94 93 92

99 91

98 90

Bank 3 Bank 2 Bank 1 Default register bank for R0-R7

8F

8E

Not bit addressable Not bit addressable Not bit addressable Not bit addressable Not bit addressable 8D 8C 8B 8A Not bit addressable Not bit addressable Not bit addressable Not bit addressable 85 84 83 82

89

88

87

86

81

80

RAM

SPECIAL FUNCTION REGISTERS

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FIGURE 2-6 Summary of the 8051 on-chip memory

General-Purpose RAM

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Bit-Addressable RAM
210 bit-addressable locations 128 bytes are located from 20H to 2FH Rest are in special function registers Bits can be set, cleared, ANDed, Ored, etc,... Most microprocessors require a read-modify-write sequence to achieve the same effect. I/O ports are also bit-addressable 128 general-purpose bit-addressable locations from 20H to 2FH which can be accessed as bytes or bits For example, to set bit 67H: SETB 67H 31

Register Banks
Contained in the bottom 32 locations of internal memory 8051 instruction set supports 8 registers, R0-R7, and by default are located at 00H-07H ex. to read the contents of 05H into the accumulator:
MOV A,R5 ;ONE BYTE INSTRUCTION, REG ADDRESSING

Same operation using a 2-byte instruction and direct addressing:

MOV A,05H

Instructions using registers R0 to R7 (ie. Register addressing) are shorter than the same instructions using direct addressing Frequently used data values should use registers. Active register bank may be changed by changing the appropriate bits in the program status word (PSW)

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Special Function Registers

...are internal registers that are accessed implicitly by the instruction set. Each register (except for the PC and IR) has its own address In addition to R0-R7, the 8051 has 21 SFRs at the top of internal RAM, from addresses 80H to FFH (note that most of the 128 addresses in this range are not defined) SFRs are both bit-addressable and byte-addressable: SETB 0E0H ;SETS BIT 0 IN ACCUMULATOR

E0H is both the byte address of the entire ACC and the bit address of the least significant bit in the ACC ex. Port 1 is at byte address 90H or 10010000B. The bits within Port 1 have addresses 90H to 97H, or 10010xxxB 33

Program Status Word (PSW)

BIT PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 SYMBOL CY AC F0 RS1 RS0 ADDRESS D7H D6H D5H D4H D3H BIT DESCRIPTION Carry flag Auxiliary carry flag Flag 0 Register bank select 1 Register bank select 2 00 = bank 0; addresses 00H-07H 01 = bank 1; addresses 08H-0FH 10 = bank 2; addresses 10H-17H 11 = bank 3; addresses 18H-1FH Overflow flag Reserved Even parity flag

PSW.2 PSW.1 PSW.0

OV P

D2H D1H D0H

Carry Flag (C or CY) Dual purpose 1. Arithmetic operations set if there is a carry out of bit 7 during an add, or set if there is a borrow into bit 7 during a subtract eg. If the ACC contains FFH, then the instruction ADD A,#1 leaves the ACC equal to 00H and sets the carry flag in the PSW 2. Boolean accumulator 1-bit register for Boolean instructions operating on bits. eg. The following instruction ANDs bit 25H with the carry flag and places the result back in the carry flag

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Program Status Word (con't)

Auxiliary Carry Flag (AC) When adding binary-coded-decimal (BCD) values, the AC is set if a carry was generated out of bit 3 into bit 4 or if the result in the lower nibble is in the range 0AH-0FH If the values added are BCD, then the add instruction must be followed by DA A (decimal adjust accumulator) to bring the results greater than 9 back into range Flag 0 General-purpose flag bit available for user applications

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Program Status Word (con't)

Register Bank Select Bits (RS0 and RS1) Determine the active register bank Cleared after a system reset and are changed as needed by software The following code enables register bank 3 and then moves the contents of R7 (byte address 1FH) to the ACC: SETB SETB MOV RS1 RS0 A,R7

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Program Status Word (con't)

Overflow Flag Set after an arithmetic overflow occurred during an addition or subtraction operation This bit can be examined when signed numbers are added or subtracted to determine if the result is in the proper range. Can be ignored if using unsigned numbers Results greater than +127 or less than -128 will set this bit The following addition example causes an overflow and sets the OV bit: Hex: 0F +7F Decimal: 15 +127

8E 142 As a signed number, 8EH represents -116, which is not the correct result of 142, therefore, the OV bit is set.

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Program Status Word (con't)

Parity Bit Is set or cleared automatically each machine cycle to establish parity with the accumulator The number of 1-bits in the accumulator plus the P bit is always even. Most commonly used with the serial port routines to include a parity bit before transmission or to check for parity after reception. Example: What is the state of the P bit after the following instruction is executed? MOV A,#55H

Solution: P=0, since 55H = 01010101B

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B Register
B Register (or accumulator B) Used along with the accumulator for multiply and divide operations. MUL AB instruction multiplies the 8-bit unsigned values in A and B and leaves the 16-bit result in A (low-byte) and B (high-byte) Similarly, DIV AB divides A by B, leaving the integer result in A and the remainder in B B register can also be used as a general-purpose scratch-pad register It is bit addressable through bit addresses F0H to F7H

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Stack Pointer
8-bit register that contains the address of the data item currently on the top of the stack. Pushing data on the stack increments the SP before writing the data. Popping from the stack reads data and then decrements the SP Stack is kept in internal RAM and is limited to addresses accessible by indirect addressing. (first 128 bytes of on-chip RAM) To reinitialize the SP with the stack beginning at 60H: MOV SP,#5FH

This would limit the stack to 32 bytes, since the uppermost address of onchip RAM is 7FH. The value 5FH is used, since the SP increments to 60H before the first push operation Default (or reset value) is 07H, thereby storing the first data value in 08H. If SP is not reinitialized, the register bank 1 (maybe 2 and 3) is not available, since this area of internal RAM is the stack

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Data Pointer
16-bit register at addresses 82H (DPL, low-byte) and 83H (DPH, high byte) used to access external code or data memory The following code writes 55H into external RAM location 1000H: MOV MOV MOVX A,#55H DPTR,#1000H @DPTR, A ; X denotes external memory

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Port Registers
4 I/O ports: P0, P1, P2, P3 All ports are bit addressable Each bit can be specified using the dot operator (ie. P1.7) P0, P2, P3 may not be available for I/O if external memory is used or if some other special features are used (interrupts, serial port, etc.) P1 is always available for I/O Example: consider the interface to a device with a status bit called BUSY, which is set when the device is busy and clear when it is ready. If BUSY connects to Port 1 bit 5, the following loop could be used to wait for the device to become ready: WAIT: JB P1.5,WAIT

This instruction means If bit P1.5 is set, jump to the lable WAIT. Ie. Jump back and check it again.

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Remaining Registers
Timer Registers 2 16-bit timers are at TL0, TH0, TL1, TH1 Controlled by using TMOD and TCON Serial Port Registers SBUF: buffer for serial port SCON: control register for serial port Interrupt Registers IE: interrupt enable IP: interrupt priority

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External Memory
Memory cycle A0-A15 24 lines D0-D7 a) Nonmultiplexed (24 lines) Memory cycle A8-A15 16 lines AD0-AD7 b) Multiplexed (16 lines) FIGURE 2-7 Multiplexing the address bus (low-byte) and data bus Data Address

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Accessing External Code Memory

Port 0 8051 EA 74HC373 D ALE G Q A0-A7 D0-D7 EPROM

Port 2 PSEN

A8-A15 OE

FIGURE 2-8 Accessing external code memory

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Accessing External Code Memory

One machine cycle S1 P1 Osc. ALE P2 P1 S2 P2 P1 S3 P2 P1 S4 P2 P1 S5 P2 P1 S6 P2 P1 S1 P2

PSEN

Port 2

PCH

PCH

Port 0

PCL

Opcode

PCL

Byte 2

FIGURE 2-9 Read timing for external code memory (opcode fetch)

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Accessing External Data Memory

One machine cycle S1 Osc. ALE PSEN RD Port 2 PCH DPH (data pointer high byte) S2 S3 S4 S5 S6 S1 S2 One machine cycle S3 S4 S5 S6

Port 0

PCL

Opcode

DPL

Data in

FIGURE 2-10 Read timing for external data memory (ie. MOVX A,@DPTR instruction)

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Accessing External Data Memory

Port 0 8051 EA +5V 74HC373 D ALE P2.0 P2.1 RD WR PSEN G A8 A9 OE W CS Q D0-D7 RAM (1K bytes) A0-A7

NC (no connection)

FIGURE 2-11 Interface to 1K RAM

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Address Decoding
Address bus Data bus

D0-D7 D0-D7 PSEN OE EPROM 8K bytes A0-A12 CS CS CS A15 C A14 B A13 A +5V
74HC138 0 1 2 3 4 5 6 7

RD WR

OE W RAM 8K bytes A0-A12 CS CS CS

E1 E2 E3

Select other EPROMS/RAMS

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