AKCE/PM/C-V/PRN/7.5.

1/23/F-05

ARULMIGU KALASALINGAM COLLEGE OF ENGINEERING ANAND NAGAR, KRISHNANKOIL - 626 190. DEPARTMENT OF INSTRUMENTATION AND CONTROL ENGINEERING COURSE PLAN SUBJECT NAME STAFF NAME III Year / VIII SEM 1. Pre-requisite: a. Fundamentals of microprocessor and DSP processors. 2. Objectives : This course is designed with two complementary goals: 1. To understand the scientific principles and concepts behind embedded systems, and 2. To obtain hands-on experience in programming embedded systems. . 3. Learning outcome and end use: Understand, and be able to discuss and communicate intelligently about a. Embedded processor architecture and programming b. I/O and device driver interfaces to embedded processors with networks, multimedia cards and disk drives c. OS primitives for concurrency, timeouts, scheduling, communication and synchronization 4. REFERENCE BOOK : 1. Rajkamal, Embedded System Architecture, Programming, Design, Tata McGraw Hill, 2003. 2. Daniel W. Lewis Fundamentals of Embedded Software, Prentice Hall of India, 2004. 3. David E. Simon, An Embedded Software Primer, Pearson Education, 2004. 4. Frank Vahid, Embedded System Design A Unified hardware & Software Introduction, John Wiley, 2002. 5. Sriram V. Iyer, Pankaj Gupte, Embedded Real Time Systems Programming, Tata McGraw Hill, 2004. : EMBEDDED SYSTEM DESIGN / EC 1032 : M.P.Rajasekaran

5. Web resources : www.DSPguide.com- 24 units covering the syllabus. www.artist- embedded.org/docs/Events/2003/ICD/Education/Moon%20Kim.pdf csis.bits-pilani.ac.in/faculty/tsbs/Main/Courses/Hsc_08/handouts/eeeg626_08.pdf www.science-engineering.net/embedded-systems.htm Topics Book Periods Cumulative Hours 3 5 7 10

6. Lesson Plan Sl.No

1. 2. 3. 4.

UNIT -I INTRODUCTION TO EMBEDDED SYSTEM Introduction to functional building blocks of 3

embedded systems

6. 7. 8. 9. 10.

Register, memory devices 2 R1 Ports, timer 2 Interrupt controllers using circuit block 3 diagram representation for each category. UNIT - II PROCESSOR AND MEMORY ORGANIZATION Structural units in a processor; 1 Selection of processor & memory devices; 2 shared memory; DMA 1 R1 Interfacing processor, memory and I/O 2 units; Memory management Cache mapping 4 techniques, dynamic allocation Fragmentation. UNIT- III DEVICES & BUSES FOR DEVICES NETWORK I/O devices; timer & counting devices; 3 serial communication using I2C, CAN, USB buses; Parallel communication using ISA, PCI, 3 R1 PCI/X buses, arm bus; Interfacing with devices/ports, device 4 drivers in a system Serial port & parallel port. UNITY - IV I/O PROGRAMMING SCHEDULE MECHANISM Intel I/O instruction Transfer rate, R1 4 latency; interrupt driven I/O -

11 13 14 16 20

14. 15. 16.

23 26 30

17.

34

18.

19. 20.

Non-maskable interrupts; software interrupts, writing interrupt service routine in C & assembly languages; preventing interrupt overrun; disability interrupts. Multi threaded programming Context switching, premature & non-premature multitasking, semaphores Scheduling Thread states, pending threads, context switching, round robin scheduling, priority based scheduling, assigning priorities, deadlock, watch dog timers.

38

2 4

40 44

21.

UNIT - V REAL TIME OPERATING SYSTEM (RTOS) Introduction to basic concepts of RTOS, 4 Basics of real time & embedded system operating systems RTOS Interrupt handling, task scheduling; embedded system design issues in system development process Action plan, use of target system, emulator, use of software tools. R1 3 3 1

48

22. 23. 24.

51 54 55

STAFF INCHARGE

HOD/ICE