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Intel 80286 to Pentium Processor Architecture


Prof. Dr. Shaiq A. Haq

Chairman CSE Department

University of Engineering & Technology, Lahore

Scheme of Presentation
Architecture of; 80286 Processor 80386 Processor 80486 Processor Intel Pentium Processor

80286 Features
Introduced in Feb. 1982 Originally 6.0MHz, went up to 20 MHz MIPS = 0.90 No. of Transistors = 134,000 Design Resolution (Pixel Size) = 1.5 micron Address Bus = 24 bit (16 MB) Data Bus = 16 bit Register Size = 16 bit No. of Registers = 14 No. of Instructions in Instruction Set = 225 +

80286 Features (cont.)

Two modes of operation;
Real Mode Protected Mode

Introduced Memory Management Unit to support multi tasking at the processor level. Little-Endian Architecture

80286 Processor

Flag Registers
The 8086 has 9 flags, the 80286 has 11 flags, and the 80386 has 13 flags. All of these flag registers include 6 flags related to data conditions (sign, zero, carry, auxiliary carry, overflow, and parity) and three flags related to machine operations (Interrupt, Single-step and Strings). The 80286 has two additional flags: I/O Privilege and Nested Task. The I/O Privilege uses two bits in protected mode to determine which I/O instructions can be used, and the nested task is used to show a link between two tasks. The processor also includes control registers and system address registers, debug and test registers for system and debugging operations.

80386 Features
Introduced in Oct. 1985 Originally 16MHz, went up to 33 MHz MIPS = 5.0 No. of Transistors = 275,000 Design Resolution (Pixel Size) = 1.5 micron Address Bus = 32 bit (4 GB RAM) Data Bus = 32 bit Register Size = 32 bit No. of Registers = 14 No. of Instructions in Instruction Set = eq. 80286+

80386 Features (cont.)

Paging Unit and Segmentation Unit to support Virtual Memory at the processor level. Three Modes;
Real Mode Protected Mode Virtual Mode

Pipelined architecture. The 80386 was the first processor in the Intel family to include parallel stages in its execution cycle.

80386 Features (cont.)

The six stages and the parts of the 386 processor that carry them out: Bus Interface Unit (BIU): accesses memory and I/O. Code Prefetch Unit: receives machine instructions from the BIU and inserts them into the instruction prefetch queue. Instruction Decode Unit: decodes machine instructions from the prefetch queue and translates them into microcode. Execution Unit: executes the microcode instructions produced by the instruction decode unit. Segment Unit: translates logical addresses to linear addresses and performs protection checks. Paging Unit: translates linear addresses into physical addresses, performs page protection checks, and keeps a list of recently accessed pages.

80386 Processor

80386 Execution Sequence

Coprocessor CISC Processor Register Register Register Register ALU

Prefetch Queue

Decoding Unit

Bus Interface

Microcode ROM

Microcode Queue Execution Unit

Control Unit

In a microprogrammed CISC the processor fetches the instructions via the bus interface into a prefetch queue, which transfers them to a decoding unit. The decoding unit breaks the machine instruction into many elementary micro-instructions and apples them to a microcode queue. The micro-instructions are transferred from the microcode queue to the control and execution unit which drives the ALU and the registers

80486 Features
Introduced in Apr. 1989 Originally 25MHz, went up to 33 MHz MIPS = 20.0 No. of Transistors = 1.2 million Design Resolution (Pixel Size) = 1.0 micron Address Bus = 32 bit Data Bus = 32 bit Register Size = 32 bit No. of Registers = 14 No. of Instructions in Instruction Set = i386 + i387

80486 Features (cont.)

Longer Pre-Fetch Queue, 32 instead of 16 bytes Some concepts of RISC architecture were introduced for the first time. Pipelined Architecture. Decoding and execution of up to 5 instructions could be done in parallel. This allowed many instructions to be implemented in only one clock cycle. first Intel processor to integrate the floating-point unit directly into the CPU chip. Has 8K high-speed level-1 cache memory that holds copies of instructions and data that have been most recently accessed.

80486 Simple Block Diagram

Cache (8K bytes) Bus Interface
Segmentation Unit

A31-A0 D31-D0 Control and Status Signals

Paging Unit

Register and ALU

Prefetcher (32-byte queue)

Decoding Unit

Control Unit

Floating Point Unit

i486 CPU

80486 Processor

80486 Pipeline
Instruction Fetch (memory access Write-back
Write result into eax

Cycle n

ADD eax, mem32

Cycle n+1

Decode ADD, fetch mem32

Cycle n+2

Decode ADD (continued)

Cycle n+3

Add eax and mem32

Cycle n+4


Decode 1

Decode 2

Intel Pentium Features

Introduced in Mar. 1993 Originally 66MHz, up to 220 MHz (Pentium Pro) MIPS = 66 No. of Transistors = 3.1 million Design Resolution (Pixel Size) = 0.8 micron Address Bus = 32 bit Data Bus = 64 bit Register Size = 32 bit No. of Registers = 16 + a set of control/test registers No. of Instructions in Instruction Set = eq. 80486+

Intel Pentium Features (cont.)

Gave about 90% improvement over 486. Superscalar design with two instruction pipelines. Dual integer pipelines (the U-pipeline for IA-32 and the V-pipeline for simple instructions). Short command execution, through many hardwired instructions Under best case conditions the Pentium can complete two instructions in every clock Two separate 8K internal caches for instruction and data (the 486 had only a single cache). The pipelined floating-point unit in Pentium performs faster operations than i486.

Intel Pentium Features (cont.)

Branch Prediction using the Branch Target Buffer (BTB). Branch prediction logic allows the Pentium to analyze instructions that are about to be executed. When the instructions contain a conditional branch (in a loop or IF statement, for example), the CPU predicts where the branch is likely to go and loads the instructions at the target address. Even-parity checking is implemented for the data bus and the internal RAM arrays (caches and TLBs). System Management Mode (SMM)

Pentium Registers(1)
Instruction Pointer 31 EIP 16 15 IP 0 EFLAG EFLAG Register 16 15 31 FLAG E0

General-Purpose Registers 16 15 31 EAX EBX ECX EDX ESI EDI EBP ESP AH BH CH DH



Segment Registers 15 0

Pentium Registers(2)
15 TR LDTR TSS Selector LDTSS Selector IDTR GDTR 0 31 0 19 TSS Base Address LDT Base Address IDT Base Address GDT Base Address TSS Limit LDT Limit IDT Limit GDT Limit 0

Control Registers 31 CR4 CR3 CR2 CR1 CR0 16 15 0 DR7 DR6 DR5 DR4 DR3 DR2 16 15 0 DR1 DR0 TR7 TR6

Debug Registers 31 16 15 0

Test Registers 31 TR12

Pentium Block Diagram

64-bit Data bus 32-bit Address bus Pentium

Bus Interface


Data Cache 8 Kbytes

Code Cache 8 Kbytes



Prefetch Buffer Instruction Decode Microcode ROM

Control Unit

v pipeline

u pipeline

Floating Point Pipeline


Intel Pentium

Demand-Paged Virtual Memory

Demand-Paged Virtual Memory Uses a combination of main memory (semiconductor memory, RAM) and system hard-disk to make it appear to applications as if the computer has access to a much larger main memory Allows swapping of pages in and out of memory