IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO.

10, OCTOBER 2001

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Pseudo C-2C Ladder-Based Data Converter Technique

Lin Cong
AbstractA C-2C ladder-based DAC architecture is potentially very attractive because of its small area, high speed and low power consumption. However, the parasitic capacitances on the interconnecting nodes of a C-2C ladder significantly deteriorate the linearity of the DAC and restrict its application. In this paper, a pseudo C-2C ladder structure is proposed. It maintains the advantages of conventional C-2C ladders and effectively compensates for the parasitic effects by adjusting the capacitor ratio in a C-2 C ladder. As a result, high linearity may be achieved in standard CMOS technologies. The technique is illustrated with the design of a 12-bit CMOS DAC. Index TermsAnalog-to-digital converters (ADC), CMOS data converters, differential nonlinearity (DNL), digital-to-analog converters (DAC), integral nonlinearity (INL), pseudo C-2C ladder.

I. INTRODUCTION Capacitor arrays are widely used for DAC and Successive Approximation ADC designs [1][3]. The use of a binary-weighted capacitor (BWC) array was first reported in 1975 [4]. Since the total capacitance value of BWC arrays rise exponentially with the resolution in number of bits, the accuracy of BWC DACs is limited to 8 to 10 bit due to the large capacitor ratios and the small area to perimeter ratio of the unit capacitor in the BWC arrays. To overcome these difficulties, a two-stage weighted capacitor (TWC) array was proposed in [5], where the capacitor array consists of two BWC arrays connected with a coupling capacitor. The obvious extension of a TWC array is a complete ladder, as shown in Fig. 1(a), in which two is the largest ratio between capacitors [6], hence good capacitor matching may be achieved. Since the total capacitance value of a ladder increases linearly with the resolution in number of bits, ladder is dramatically smaller than a BWC the area of a ladder-based DACs have array. For a given resolution, inherently higher speed than those based on BWC arrays and ladders. TWC arrays because of smaller RC effects in However, parasitic capacitances on the interconnecting nodes ladders, as shown in Fig. 1(b), severely impede their of linearity. Several attempts have been made to minimize these undesirable parasitic effects, but a satisfactory solution to this problem has never been realized. One published approach takes advantage of a three-layer unit capacitor to implement 8-bit and ladder-based D/A converters [7]. However, this 13-bit method is very complicated and even though the process variManuscript received January 24, 2001; revised October 12, 2001. This paper was recommended by Associate Editor G. Cauwenberghs. The author is with the Department of Electrical Engineering, Columbia University, New York, NY 10027 USA. Publisher Item Identifier S 1057-7130(01)11039-6.

ation is ignored, the parasitic capacitance effect still cannot be sufficiently canceled. ladder structure In this paper, a variation on the pseudo - ladderis proposed. It maintains the advantages ladders such as small capacitor ratios, of conventional high conversion rate and low power consumption, and effectively compensates for parasitic effects on the interconnecting nodes by accounting for them in the design. Furthermore, this structure accommodates a wide variety of standard unit capacitors compatible with standard CMOS technologies. To demonstrate this technique, a 12-bit DAC was designed to achieve high linearity, fast settling time with relatively small area and low power. ladder-based DAC model is established in A pseudo Section II. The implementation of a 12-bit DAC based on the technique and simulation results are presented in Section III. Conclusions are drawn in Section IV. II. PSEUDO C-2C LADDER-BASED DAC The parasitic capacitance distribution in a typical ladder is shown in Fig. 1(b), where represents the bottomplate and top-plate parasitic capacitances of the interconnecting capacitors ( ) as well as the top-plate parasitic capacitance of the branch capacitor ( ). In the following we assume that the top-plate parasitic capacitances are negligible compared with the bottom-plate parasitic capacitances, and can be ignored. This assumption is valid, for instance, in a single-poly five-metal CMOS process where metal3 and metal5 are used as the bottom plates, and metal4 as the top plate (which is called a sandwich capacitor), shielded from beneath by the bottom plate. The significant parasitic effects present at the ladder deteriorate the interconnecting nodes of the desired voltage division and result in poor linearity. To solve this problem, a pseudo - ladder model, as shown in Fig. 1(c), is proposed. The basic idea is to replace the ladder with a ladder, and adjust the capacitor ratio in the ladder so that the parasitic effects are balanced out and precise voltage divisions are achieved. Direct application of the Thevenin Theorem translates the pseudo ladder with parasitics in Fig. 1(c) into the equivalent in the ladder structure of Fig. 1(d). Each branch capacitor equivalent ladder combines the corresponding branch capacin the ladder with the parasitic capacitance itance feeding in the same node 2 (1)

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 10, OCTOBER 2001

(a)

(b)

(c)

(d)

Fig. 1. (a) Ideal C-2C ladder. (b) C-2C ladder with parasitic effects. (c) Pseudo C-2C ladder. (d) Thevenin equivalent of pseudo C-2C ladder.

where is the ratio of bottom-plate parasitic to topbottom inter-plate capacitance. Therefore, the choice (2) , yielding an equivalent ladder where renders all capacitances are uniformly scaled by the factor . Since the voltage division is determined by the capacitor ratios, the charge injected to the output common node is independent of , and identical to that of the ideal - ladder shown in Fig. 1(a). Notice that the branch capacitors driven by the reference voltage in in Fig. 1(d), so the reference Fig. 1(c) are other than voltage in the pseudo ladder is scaled by . ladder model can sufficiently balThe above pseudo ance out the parasitic effects when the process parameter is precisely know in advance. In practice, process variations cause uncertainty in which degrades linearity. The effect of process variations on linearity is illustrated with a practical design in the next section. III. DESIGN EXAMPLE AND SIMULATION RESULTS As an example, a 12-bit DAC was designed employing the pseudo - ladder. To reduce gain error and achieve good linearity, the 12-bit DAC, shown in Fig. 2, is segmented with the 6 MSBs steering a thermometer-code capacitor array (TCC) and the 6 LSBs steering a 6-stage pseudo - ladder. According to the derivation in Section II, the dummy capacitor and the capacitors in the lateral branch of the pseudo - ladder are scaled by the factor , where is decided by (2) with equal to its . nominal value The linearity of the DAC is mainly affected by two factors: the run-to-run variation of and the random mismatch between the capacitors.

Fig. 2.

12-bit pseudo C-2C ladder-based DAC.

Fig. 3 shows the INL and DNL of the DAC when varies from 0.14 to 0.18. As expected, when is close to the nominal value (0.16) assumed for the choice of , the nonlinearity of the DAC is rather small. When deviates from its nominal value, the nonlinearity increases almost linearly. The simulation results show that when changes by 4% from its nominal value, the INL and DNL of the DAC are below 0.5 LSB. If changes 12.5%, the nonlinearity of the DAC increases to 1.5 LSB. The worst-case INL and DNL is observed at the segmented point between the TCC array and the pseudo - ladder. This is because the variations of not only change the ratios between the branch and the interconnecting capacitors of the pseudo ladder but also change the weight of the ladder in the overall segmented structure. An easy way to compensate for the variation and keep the balance between the LSB ladder and the MSB array is to correspondingly adjust the reference voltage of the pseudo - ladder shown in Fig. 2. As discussed when . in Section II, Fig. 3 shows that a 4% tuning adjustment of Vtune reduces the nonlinearity of the DAC to almost a factor one half. As a result, the INL of the DAC is maintained below 0.5 LSB and

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Fig. 5.

DAC mid-point and full-scale transitions.

IV. CONCLUSION A new charge redistribution data conversion technique ladderis proposed in this paper. The ladder pseudo coefficients are determined by the relative bottom-plate parasitic capacitance. This technique maintains the advantages of ladders such as small area, high speed and conventional low power dissipation, while effectively compensating for the parasitic capacitance effect existing in the conventional ladder, thus dramatically improving the accuracy of the DAC. Simulation results show that DACs using this technique have the potential to achieve 12-bit accuracy and 1 ns settling time. ladder-based DACs is An obvious application of pseudo high-resolution successive approximation ADCs [7]. REFERENCES
[1] G. Ahn, H. Choi, S. Lim, S. Lee, and C. Lee, A 12-b, 10-MHz, 250-mW CMOS A/D convert, IEEE Journal Of Solid-State Circuits, vol. 31, pp. 20302035, December 1996. [2] B. Song, S. Lee, and M. F. Tompsett, A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter, IEEE Journal Of Solid-State Circuits, vol. 25, pp. 13281338, December 1990. [3] G. Nicollini, S. Pernici, P. Confalonieri, C. Crippa, A. Nagari, S. Mariani, A. Calloni, M. Moioli, and C. Dallavalle, A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones, IEEE Journal of Solid-State Circuits, vol. 33, pp. 11581167, August 1998. [4] J. L. McCreary and P. R. Gray, All-MOS charge redistribution analog-to-digital conversion techniquesPart 1, IEEE Journal of Solid-State Circuits, vol. SC-10, pp. 371379, December 1975. [5] Y. S. Yee, L. M. Terman, and L. G. Heller, A two-stage weighted capacitor network for D/AA/D conversion, IEEE Journal of Solid-State Circuits, vol. SC-14, pp. 778781, August 1979. [6] J. L. McCreary, Matching properties, and voltage and temperature dependence of MOS capacitors, IEEE Journal of Solid-State Circuits, vol. SC-16, pp. 608616, December 1981. [7] S. P. Singh, A. Prabhakar, and A. B. Bhattcharyya, C-2C ladder-based D/A converters for PCM codecs, IEEE Journal of Solid-State Circuits, vol. SC-22, pp. 11971200, December 1987. [8] S. Lee and B. Song, Digital-domain calibration of multistep analog-todigital converters, IEEE J. Solid-State Circuits, vol. 27, pp. 16791688, Dec. 1992. [9] J. M. Ingino and B. A. Wooley, A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter, IEEE J. Solid-State Circuits, vol. 33, pp. 19201931, Dec. 1998. [10] L. Cong and W. C. Black, A new charge redistribution D/A and A/D converter techniquePseudo C-2C Ladder, in IEEE Midwest Symp. Circuits Syst.: Lensing, Aug. 2000. [11] M. J. McNutt, S. LeMarquis, and J. L. Dunkley, Systematic capacitance matching errors and corrective layout procedures, IEEE J. Solid-State Circuits, vol. 29, pp. 611616, May 1994. [12] J. Shyu, G. C. Temes, and K. Yao, Random errors in MOS capacitors, IEEE J. Solid-State Circuits, vol. SC-17, pp. 10701076, Dec. 1982.

Fig. 3. Integral and differential DAC nonlinearity versus

= Cp=C.

Fig. 4. Yield at 0.5 LSB linearity level as a function of mismatch variability  .

the DNL is less than 0.75 LSB for a variation as large as 12.5%. For larger variations, 23 bit calibration may be applied to compensate for the residual errors [8][10]. The value, or the area of unit capacitor is determined to overcome the random mismatch between the capacitors (denoted as ) [11], [12]. Monte-Carlo simulation in Fig. 4 shows that to achieve 12-bit accuracy and guarantee over 99% yield, less than 0.1% matching is required for the unit capacitors. The corresponding capacitor value is large enough to overcome the KT/C noise. Similar matching is required to the conventional caDACs need pacitor array DACs. However, since pseudo only a small number of unit capacitors, it is more cost-effective, consumes less power, and offers a faster conversion rate owing to shorter RC delays. The mid-point and full-scale transitions of the DAC designed with TSMC 0.25 m process are shown in Fig. 5. The accuracy of the settled values on the output common node are within 0.5 LSB at the major transitions (between 1 000 000 000 000 and 011 111 111 111). The settling time of the full-scale transition of the DAC simulated by Hspice is less than 1 ns.

Lin Cong photograph and biography not available at the time of publication.