12.

Serial-Parallel Multiplier

Figure 12.1 shows the RTL diagram of a serial-parallel multiplier. One of the input vectors (a) is applied serially to the circuit (one bit at a time, starting from the LSB), while the other (b) is applied in parallel (all bits simultaneously). Say that a has M bits, while b has N. Then, after all M bits of a have been presented to the system, a string of M 0s must follow, in order to complete the (M N)-bit output product. As can be seen in gure 12.1, the system is pipelined, and is constructed using AND gates, full-adder units, plus registers (ip-ops). Each unit of the pipeline (except the leftmost one) requires one adder and two registers, plus an AND gate to compute one of the inputs. Thus for an M N multiplier, O(N) of such units are required. The solution presented below is of structural type (only COMPONENTS were used). Notice that there is more than one level of instantiation (the unit called pipe instantiates other components, while in the nal code, pipe is instantiated as well (besides other components). The design of each component is shown below, along with the PACKAGE containing all COMPONENT declarations, followed by the project proper (main code). Simulation results were also included.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 ------ and_2.vhd (component): --------LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------ENTITY and_2 IS PORT ( a, b: IN STD_LOGIC; y: OUT STD_LOGIC); END and_2; --------------------------------------ARCHITECTURE and_2 OF and_2 IS BEGIN y <= a AND b; END and_2; ---------------------------------------

b(3) a

b(2)

b(1)

b(0)

a(0) a(1) a(2) a(3)

+
D

+
D

+
D

prod

Figure 12.1 Serial-parallel multiplier.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5

------ reg.vhd (component): ----------LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------ENTITY reg IS PORT ( d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END reg; --------------------------------------ARCHITECTURE reg OF reg IS BEGIN PROCESS (clk, rst) BEGIN IF (rst='1') THEN q<='0'; ELSIF (clk'EVENT AND clk='1') THEN q<=d; END IF; END PROCESS; END reg; -------------------------------------------- fau.vhd (component): ----------LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------ENTITY fau IS

6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8

PORT ( a, b, cin: IN STD_LOGIC; s, cout: OUT STD_LOGIC); END fau; --------------------------------------ARCHITECTURE fau OF fau IS BEGIN s <= a XOR b XOR cin; cout <= (a AND b) OR (a AND cin) OR (b AND cin); END fau; -------------------------------------------- pipe.vhd (component): ---------LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.my_components.all; --------------------------------------ENTITY pipe IS PORT ( a, b, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END pipe; --------------------------------------ARCHITECTURE structural OF pipe IS SIGNAL s, cin, cout: STD_LOGIC; BEGIN U1: COMPONENT fau PORT MAP (a, b, cin, s, cout); U2: COMPONENT reg PORT MAP (cout, clk, rst, cin); U3: COMPONENT reg PORT MAP (s, clk, rst, q); END structural; ------------------------------------------- my_components.vhd (package):----LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------PACKAGE my_components IS -------------------------COMPONENT and_2 IS PORT (a, b: IN STD_LOGIC; y: OUT STD_LOGIC);

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

END COMPONENT; -------------------------COMPONENT fau IS PORT (a, b, cin: IN STD_LOGIC; s, cout: OUT STD_LOGIC); END COMPONENT; -------------------------COMPONENT reg IS PORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT; -------------------------COMPONENT pipe IS PORT (a, b, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT; -------------------------END my_components; ------------------------------------------- multiplier.vhd (project): ------LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.my_components.all; --------------------------------------ENTITY multiplier IS PORT ( a, clk, rst: IN STD_LOGIC; b: IN STD_LOGIC_VECTOR (3 DOWNTO 0); prod: OUT STD_LOGIC); END multiplier; --------------------------------------ARCHITECTURE structural OF multiplier IS SIGNAL and_out, reg_out: STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN U1: COMPONENT and_2 PORT MAP (a, b(3), and_out(3)); U2: COMPONENT and_2 PORT MAP (a, b(2), and_out(2)); U3: COMPONENT and_2 PORT MAP (a, b(1), and_out(1)); U4: COMPONENT and_2 PORT MAP (a, b(0), and_out(0)); U5: COMPONENT reg PORT MAP (and_out(3), clk, rst, reg_out(3));

Figure 12.2 Simulation results of serial-parallel multiplier.

21 U6: COMPONENT pipe PORT MAP (and_out(2), reg_out(3), 22 clk, rst, reg_out(2)); 23 U7: COMPONENT pipe PORT MAP (and_out(1), reg_out(2), 24 clk, rst, reg_out(1)); 25 U8: COMPONENT pipe PORT MAP (and_out(0), reg_out(1), 26 clk, rst, reg_out(0)); 27 prod <= reg_out(0); 28 END structural; 29 ---------------------------------------

Simulation results are shown in gure 12.2. a 1100 (decimal 12) was applied to the serial input. Notice that this input must start with the LSB (a(0) 0), which appears in the time slot 100 ns200 ns, while the MSB (a(3) 1) is situated in 400 ns500 ns. Recall that four zeros must then follow. On the other hand, at the parallel input, b 1101 (decimal 13) was applied. The expected result, prod 10011100 (decimal 156), can be observed in the lower plot. Recall that the rst bit out is the LSB; that is, prod(0) 0, which appears in the time slot immediately after the rst rising edge of clock; (that is, 150 ns250 ns), while the last bit (MSB) of prod is situated in 850 ns950 ns.