EE 447 VLSI Design

Lecture 5: Wires

Outline
Introduction
Wire Resistance Wire Capacitance

Wire RC Delay
Crosstalk Wire Engineering

Repeaters

6: Wires EE 447VLSI Design

Introduction
Chips are mostly made of wires called interconnect

In stick diagram, wires set size Transistors are little things under the wires Many layers of wires Wires are as important as transistors Speed Power Noise Alternating layers run orthogonally

6: Wires EE 447VLSI Design

Wire Geometry
Pitch = w + s Aspect ratio: AR = t/w

Old processes had AR << 1 Modern processes have AR 2 Pack in many skinny wires

t h

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Layer Stack
AMI 0.6 mm process has 3 metal layers Modern processes use 6-10+ metal layers Example:
Layer T (nm) W (nm) S (nm) AR

Intel 180 nm process M1: thin, narrow (< 3l) High density cells M2-M4: thicker For longer wires M5-M6: thickest For VDD, GND, clk

1720 1000

860

860

2.0

1600 1000

800

800

2.0

4 3 2 1

1080 700 700 700 700 700 480 800

540 320 320 250

540 320 320 250

2.0 2.2 2.2 1.9 Substrate

6: Wires EE 447VLSI Design

Wire Resistance
r = resistivity (W*m)

6: Wires EE 447VLSI Design

Wire Resistance
r = resistivity (W*m)

r l

t w

6: Wires EE 447VLSI Design

Wire Resistance
r = resistivity (W*m)

l R R t w w
R = sheet resistance (W/)
w w

r l

is a dimensionless unit(!) Count number of squares R = R * (# of squares)

l t 1 Rectangular Block R = R (L/W) W

l w

t 4 Rectangular Blocks R = R (2L/2W) W = R (L/W) W

6: Wires EE 447VLSI Design

Choice of Metals
Until 180 nm generation, most wires were aluminum Modern processes often use copper

Cu atoms diffuse into silicon and damage FETs Must be surrounded by a diffusion barrier
Metal Bulk resistivity (mW*cm)

Silver (Ag) Copper (Cu)

1.6 1.7

Gold (Au)
Aluminum (Al) Tungsten (W) Molybdenum (Mo)

2.2
2.8 5.3 5.3
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Sheet Resistance
Typical sheet resistances in 180 nm process
Layer Diffusion (silicided) Diffusion (no silicide) Sheet Resistance (W/) 3-10 50-200

Polysilicon (silicided)
Polysilicon (no silicide) Metal1 Metal2

3-10
50-400 0.08 0.05

Metal3
Metal4 Metal5 Metal6

0.05
0.03 0.02 0.02
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Contacts Resistance
Contacts and vias also have 2-20 W
Use many contacts for lower R

Many small contacts for current crowding around periphery

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Wire Capacitance
Wire has capacitance per unit length

To neighbors To layers above and below Ctotal = Ctop + Cbot + 2Cadj

s w layer n+1 h2 t h1 Cbot Cadj layer n-1 Ctop layer n

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Capacitance Trends
Parallel plate equation: C = eA/d

Wires are not parallel plates, but obey trends Increasing area (W, t) increases capacitance Increasing distance (s, h) decreases capacitance Dielectric constant e = ke0 e0 = 8.85 x 10-14 F/cm k = 3.9 for SiO2 Processes are starting to use low-k dielectrics k 3 (or less) as dielectrics use air pockets

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M2 Capacitance Data
Typical wires have ~ 0.2 fF/mm

Compare to 2 fF/mm for gate capacitance

400 350 300

M1, M3 planes
s = 320 s = 480 s = 640

250

Ctotal (aF/mm)

200

s= Isolated

150

s = 320 s = 480 s = 640

50

0 0 500 1000 1500 2000

w (nm)

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100

s=

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Diffusion & Polysilicon

Diffusion capacitance is very high (about 2

fF/mm)

Comparable to gate capacitance Diffusion also has high resistance Avoid using diffusion runners for wires!

Polysilicon has lower C but high R

Use for transistor gates Occasionally for very short wires between gates
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Lumped Element Models

Wires are a distributed system

Approximate with lumped element models

N segments R C R C L-model R/N C/N R C/2 C/2 R/N C/N R/N C/N R/2 R/2 C T-model R/N C/N

p-model

3-segment p-model is accurate to 3% in simulation L-model needs 100 segments for same accuracy! Use single segment p-model for Elmore delay
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Example
Metal2 wire in 180 nm process

5 mm long 0.32 mm wide R = Cpermicron =

Construct a 3-segment p-model

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Example
Metal2 wire in 180 nm process

5 mm long 0.32 mm wide R = 0.05 W/ Cpermicron = 0.2 fF/mm

260 W 167 fF 167 fF
6: Wires EE 447VLSI Design

Construct a 3-segment p-model

=> R = 781 W => C = 1 pF

260 W 167 fF 167 fF
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260 W 167 fF 167 fF

Wire RC Delay
Estimate the delay of a 10x inverter driving a

2x inverter at the end of the 5mm wire from the previous example.

R = 2.5 kW*mm for gates Unit inverter: 0.36 mm nMOS, 0.72 mm pMOS

tpd

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Wire RC Delay
Estimate the delay of a 10x inverter driving a

2x inverter at the end of the 5mm wire from the previous example.

R = 2.5 kW*mm for gates Unit inverter: 0.36 mm nMOS, 0.72 mm pMOS
781 W 690 W Driver 500 fF 500 fF Wire 4 fF Load

tpd

= 1.1 ns

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Crosstalk
A capacitor does not like to change its voltage

instantaneously. A wire has high capacitance to its neighbor.

When the neighbor switches from 1-> 0 or 0>1, the wire tends to switch too. Called capacitive coupling or crosstalk.
Noise on nonswitching wires Increased delay on switching wires
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Crosstalk effects

Crosstalk Delay
Assume layers above and below on average are quiet

Second terminal of capacitor can be ignored Model as Cgnd = Ctop + Cbot Effective Cadj depends on behavior of neighbors Miller effect A B

Cgnd Cadj Cgnd

DV

Ceff(A)

MCF

Constant
Switching with A Switching opposite A
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Crosstalk Delay
Assume layers above and below on average are quiet

Second terminal of capacitor can be ignored Model as Cgnd = Ctop + Cbot Effective Cadj depends on behavior of neighbors A B Miller effect C

Cgnd
adj

Cgnd

DV

Ceff(A)

MCF

Constant
Switching with A Switching opposite A

VDD
0 2VDD

Cgnd + Cadj
Cgnd Cgnd + 2 Cadj

1
0 2
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6: Wires EE 447VLSI Design

Crosstalk Noise
Crosstalk causes noise on nonswitching wires If victim is floating:

model as capacitive voltage divider

DVvictim

Cadj Cgnd v Cadj

Aggressor

DVaggressor

DVaggressor Victim

Cadj Cgnd-v DVvictim

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Driven Victims
Usually victim is driven by a gate that fights noise

Noise depends on relative resistances Victim driver is in linear region, agg. in saturation If sizes are same, Raggressor = 2-4 x Rvictim

DVvictim

1 DVaggressor Cgnd v Cadj 1 k

Cadj

Raggressor DVaggressor Rvictim Cgnd-v Cgnd-a

Aggressor Cadj Victim DVvictim

aggressor Raggressor Cgnd a Cadj k victim Rvictim Cgnd v Cadj

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Coupling Waveforms
Simulated coupling for Cadj = Cvictim
1.8

Aggressor

1.5

1.2

0.9

Victim (undriven): 50%

0.6

Victim (half size driver): 16% Victim (equal size driver): 8%

0.3

Victim (double size driver): 4%

0 0 200 400 600 800 1000 1200 1400 1800 2000

t(ps)

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Noise Implications
So what if we have noise?
If the noise is less than the noise margin, nothing

happens Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes But glitches cause extra delay Also cause extra power from false transitions Dynamic logic never recovers from glitches Memories and other sensitive circuits also can produce the wrong answer
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Wire Engineering
Goal: achieve delay, area, power goals with

acceptable noise Degrees of freedom:

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Wire Engineering
Goal: achieve delay, area, power goals with

acceptable noise Degrees of freedom:

Coupling:2Cadj / (2C adj+Cgnd)

Width Spacing
Delay (ns):RC/2

2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 500 1000 Pitch (nm) 1500 2000

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 500 1000 Pitch (nm) 1500 2000 WireSpacing (nm) 320 480 640

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Wire Engineering
Goal: achieve delay, area, power goals with

acceptable noise Degrees of freedom:

Coupling:2Cadj / (2C adj+Cgnd)

Delay (ns):RC/2

Width Spacing Layer

2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 500 1000 Pitch (nm) 1500 2000

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 500 1000 Pitch (nm) 1500 2000 WireSpacing (nm) 320 480 640

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Wire Engineering
Goal: achieve delay, area, power goals with

acceptable noise Degrees of freedom:

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 500 1000 Pitch (nm) 1500 2000

Coupling:2Cadj / (2C adj+Cgnd)

Width Spacing Layer Shielding

2.0 1.8

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 500 1000 Pitch (nm) 1500 2000 WireSpacing (nm) 320 480 640

Delay (ns):RC/2

vdd a0

a1 gnd a2

a3 vdd

vdd a0 gnd a1 vdd a2 gnd

a0

b0

a1

b1

a2

b2

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Repeaters
R and C are proportional to l
RC delay is proportional to l2

Unacceptably great for long wires

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Repeaters
R and C are proportional to l
RC delay is proportional to l2

Unacceptably great for long wires Break long wires into N shorter segments Drive each one with an inverter or buffer

Wire Length: l Driver Receiver

N Segments Segment l/N Driver l/N Repeater Repeater Repeater l/N Receiver
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6: Wires EE 447VLSI Design

Repeater Design
How many repeaters should we use?
How large should each one be? Equivalent Circuit

Wire length l/N Wire Capaitance Cw*l/N, Resistance Rw*l/N Inverter width W (nMOS = W, pMOS = 2W) Gate Capacitance C*W, Resistance R/W

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Repeater Design
How many repeaters should we use?
How large should each one be? Equivalent Circuit

Wire length l Wire Capacitance Cw*l, Resistance Rw*l Inverter width W (nMOS = W, pMOS = 2W) Gate Capacitance C*W, Resistance R/W

RwlN R/W Cwl/2N Cwl/2N

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C'W
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Repeater Results
Write equation for Elmore Delay

Differentiate with respect to W and N Set equal to 0, solve

l N
t pd l
W

2 RC RwCw

2 2
RCw RwC

RC RwCw

~60-80 ps/mm

in 180 nm process

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