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3, MARCH 2012


An Ultra-Wideband 80 GHz FMCW Radar System Using a SiGe Bipolar Transceiver Chip Stabilized by a Fractional-N PLL Synthesizer
Nils Pohl, Member, IEEE, Timo Jaeschke, Student Member, IEEE, and Klaus Aunger, Member, IEEE
AbstractA radar system with an ultra-wide FMCW ramp bandwidth of 25.6 GHz ( 32%) around a center frequency of 80 GHz is presented. The system is based on a monostatic fully integrated SiGe transceiver chip, which is stabilized using conventional fractional-N PLL chips at a reference frequency of 100 MHz. The achieved in-loop phase noise is 88 dBc/Hz (10 kHz offset frequency) for the center frequency and below 80 dBc/Hz in the wide frequency band of 25.6 GHz for all offset frequencies 1 kHz. The ultra-wide PLL-stabilization was achieved using a reverse frequency position mixer in the PLL (offset-PLL) resulting in a compensation of the variation of the oscillators tuning sensitivity with the variation of the -divider in the PLL. The output power of the transceiver chip, as well as of the mm-wave module (containing a waveguide transition), is sufciently at versus the output frequency (variation 3 dB). In radar measurements using the full bandwidth an ultra-high spatial resolution of 7.12 mm was achieved. The standard deviation between repeated measurements of the same target is 0.36 m. Index TermsFMCW, fractional-N synthesizer, millimeter wave, radar system, SiGe bipolar ICs, ultra-wideband.

With these high frequencies around 80 GHz, good antenna focusing can be achieved with compact measurement systems, e.g. for automotive, industrial, or commercial applications. This paper aims at substantial improvements of the resolution and accuracy of radar systems fabricated in mass market technologies to open up new applications and markets. Although a higher azimuthal resolution can be obtained by increasing the carrier frequency, the antenna size, using an array or using SAR techniques, the spatial resolution is directly limited by the bandwidth of the transmitted radar signal: (1) where is the speed of light. The resolution is dened by the theoretical minimum distance for separating two adjacent targets of the same amplitude, corresponding to the 6-dB width of the time signal.1 For example, for the bandwidth GHz of automotive long range radar systems (LRR), this leads to a resolution of 15 cm, and for short range radars (SRR) with GHz, an even higher resolution of cm can be achieved (cp. [16]). It has to be mentioned that for a robust separation of real targets with different amplitudes (e.g. target of different size close to each other), much larger distances of the adjacent targets than are necessary. Additionally, the resolution is further degraded by using window functions (other than a rect/si-pulse) in the radar signal processing, which are typically necessary to be able to detect far targets with substantially smaller amplitudes. The accuracy and reproducibility of radar measurements with single targets is typically several decades better than the achieved resolution. Most of the recently published radar systems with frequencies around 80 GHz are for the automotive frequency band (e.g. [5], [9], [12][14]), and thus have a limited bandwidth of up to 4 GHz. In [4] an experimental radar system, based on waveguide components, with 8 GHz bandwidth and a resolution of 18 mm is described, whereas in [10] the record bandwidth of 10 GHz is presented. In this paper an even higher bandwidth of 20 GHz is achieved. II. SYSTEM CONCEPT The block diagram of the proposed radar system is shown in Fig. 1. The high frequency part is fully integrated in a low1For this theoretical resolution limit a rectangular-pulse in the time domain is assumed, which results in a si-pulse in the frequency domain, whereas an FMCW radar system is hard limited in the frequency domain (rectangular window) resulting in a si-pulse in the time domain. If the 6-dB width in the must be multiplied by 1.205 for an FMCW system time domain is used, (cp. [15]).


OR MANY applications, radar is a cheap and accurate measurement technique. Especially the measurement of distances up to a few 100 m can be performed with a moderate transmit power, which can be generated with integrated circuits. The continuous improvement of silicon technologies enables the integration of various radar components as well as complete transceivers even at mm-waves around 80 GHz. Several mm-wave radar systems consisting of (multiple) chips in III-V compound semiconductors were published (e.g. [1][4]) and demonstrated the suitability for several applications. Recently, the rst transceiver chips fully integrated in silicon technologies were demonstrated (e.g. [5][9]), and even fully integrated radar systems in silicon were shown (see [10][14]).

Manuscript received July 04, 2011; revised November 30, 2011; accepted December 01, 2011. Date of publication January 26, 2012; date of current version March 02, 2012. Parts of this work have been supported by the Ministry of Economic Affairs and Energy of the State of North Rhine-Westphalia (Grant 315-43-02/2-005-WFBO-009) and the German Federal Ministry of Education and Research within the project RoCC (FKZ 13N9822). N. Pohl and T. Jaeschke are with Ruhr-Universitt Bochum, D-44780 Bochum, Germany (e-mail: K. Aunger is with Inneon Technologies AG, D-85579 Neubiberg, Germany. Color versions of one or more of the gures in this paper are available online at Digital Object Identier 10.1109/TMTT.2011.2180398

0018-9480/$31.00 2012 IEEE



Fig. 1. Block diagram of the radar system under investigation: The 80 GHz VCO is stabilized by a fractional-N offset-PLL (PLL1). The frequency of the local oscillator for the offset generation is above the divided 80 GHz VCO (reverse frequency position) and is stabilized by a second PLL (PLL2). Differential signal paths are marked with double lines.

power SiGe monolithic microwave integrated circuit (MMIC). It is mounted in a mm-wave substrate and wire-bonded for connecting the antenna and the additional PLL board. The ultrawideband 80 GHz oscillator is the main signal source of this radar system and is discussed in Section II-A. Adapted to its nonlinear and wide tuning characteristic, a special PLL concept for stabilization and FMCW ramp generation in the complete tuning range of the oscillator is used. It consists of two PLLs and a reverse frequency position downconversion mixer at 24 GHz, which is discussed in Section II-C. The ultra-wideband radar transmit signal around 80 GHz is then fed to the integrated receiver mixer and to the chip output via on-chip Wilkinson dividers. The transceiver chip is presented in Section III. Due to the monostatic conguration, only one mm-wave output using short bond wires and an on-chip matching network has to be realized. The differential output is then combined to a single-ended signal with a rat-race coupler on the mm-wave substrate. Finally a microstrip to waveguide transition (integrated in the mm-wave substrate) is used as a wideband interface to the antenna. The implementation of the radar system is presented in Section IV and its measurement results in Section V. The transceiver chip was fabricated in Inneons production technology B7HF200 [17]. At optimum current density, the transistor cutoff frequencies are GHz and GHz. Additionally, this technology offers a varactor diode ( , ) with a special hyperabrupt pn-junction, which is mandatory for an ultra-wideband oscillator with the used PLL concept.2 For a robust operation and reduced parasitic coupling effects, all circuits and interfaces are realized fully differential (cp. [18]). A. 80 GHz Oscillator The 80 GHz VCO used is based on [19] and the schematic is given in Fig. 2. It consists of a differential topology based on a well known concept for mm-wave oscillators [20], [21]. For an ultra-wideband tuning range, two varactor pairs are used at
2As discussed in Section II-C, the non-linear tuning characteristic of a pn-varactor can be excellently compensated using this PLL concept, which would not work with a MOS varactor due to its non-monotonic tuning sensitivity (non). monotonic

Fig. 2. Schematic of the 80 GHz VCO. All high frequency lines are imple) with inductive mented using on-chip transmission lines (microstrip, behavior.

the base and emitters nodes of the main transistors , respectively. Both varactor pairs are simultaneously driven by a single tuning voltage, which simplies the PLL. The phase noise requirements determine the used tail current of mA. The integrated mixer (see Section III) allows for moderate requirements with respect to the output power of the VCO, so a simple cascode stage is used for the output buffer. In contrast to [19], here no additional bias current (cp. in [19]) is necessary for linearization of the cascode stage, resulting in a total power consumption of 165 mW from a 5 V supply voltage (reduced by 31%), at a sufciently high output power ( 6 dBm, see Fig. 9 in Section IV) for driving the integrated receive mixer. The oscillator achieves an ultra-wideband measured tuning range (Fig. 3) of GHz at room temperature and GHz even at an ambient temperature of 90 C. This record tuning range is even slightly increased (by 2 GHz) compared to [19]. The smooth nonlinear shape of the tuning characteristic is well-suited for the used PLL loop gain linearization technique presented in Section II-C.



The variation of a fractional-N frequency divider with a constant reference frequency is commonly used for FMCW ramp generation with high linearity and low phase noise (e.g. [23], [24]). In this concept, a clean XCO can be used directly as the reference frequency.5 Furthermore, with an adequate loop lter, all additional fractional noise can be ltered. C. PLL Concept for Loop Gain Linearization For the choice of parameters of the PLL loop lter, the loop gain of the complete PLL is an important factor. However, the tuning sensitivity of the VCO as well as the -divider values depend on the current frequency of the FMCW-ramp. Both inuence the loop gain: (3) It is worthwhile to mention that despite the ultra-wide tuning range, the oscillator has a nearly constant performance over the full tuning range. The measured phase noise is as low as 97 dBc/Hz (at 1 MHz offset frequency) at the center frequency of 80 GHz and below 90 dBc/Hz in the full tuning range (cp. Fig. 11 in [19], nearly unchanged in this paper). The differential output power (Fig. 9) is 7 dBm at center frequency and decays only by 1 dB towards the band edges. This constant performance predestines this oscillator for ultra-wideband radar systems with record resolution. B. PLL Design Aspects Generally the overall division factor in the feedback path of a PLL increases the input referred noise oor of the phase-frequency detector (PFD) by a factor of to the in-loop phase noise of the stabilized VCO, therefore the use of a small division factor is an important design goal. For stabilization of mm-wave frequencies, the use of an auxiliary oscillator and a mixer in the PLL (offset-PLL) is therefore a well-known technique. Here, a second PLL-stabilized VCO3 at 24 GHz is used for mixing down the VCO signal after passing a divide-byfour prescaler, which reduces the overall division factor in the main PLL (PLL1 in Fig. 1) considerably.4 With this concept the overall phase noise is typically limited by the second PLL, but as this PLL is working in xed-frequency mode, it is possible to use a high reference frequency for good phase noise. Furthermore, in a fractional-N PLL a low constant prescaler in the loop is necessary, because it multiplies the variation of the -Divider and thus the pseudo-random fractional noise at the VCO. The output frequency of the 80 GHz VCO is given by (cp. Fig. 2) (2)
3In contrast to other concepts (e.g. [22]), where the local oscillator is based on

Fig. 3. Measured tuning characteristic of the 80 GHz VCO at various am. The results were obtained from a chip mounted in bient temperatures the mm-wave substrate.

In the presented offset-PLL concept with reverse frequency position mixing, both dependencies compensate each other (Fig. 4). The tuning characteristic of the 80 GHz VCO under investigation (Fig. 3) has a variation of the tuning sensitivity [see Fig. 4(a)] between 9 GHz/V at the lower end and 1 GHz/V at the upper end. After the 4-prescaler and mixing in reverse frequency position (with 24 GHz), the highest tuning sensitivity appears for the upper end of the frequency range and vice versa [see Fig. 4(b)]. But as the -divider is the highest for high frequencies, in the resulting PLL loop gain (which is proportional to the quotient of both quantities) the highest tuning sensitivity is divided by the highest -value [see Fig. 4(c)], which leads to an excellent linearization of the PLL. With the 80 GHz VCO under investigation the resulting variation of the VCO loop gain is as low as 1:1.2 in an ultra-wide frequency band of 24 GHz, thus the loop lter can be designed for optimal lter characteristic and the gain variation can be neglected, which enables ultra-wideband FMCW frequency ramps. Compared to this, a straight PLL without offset mixing would result in a variation of 10:1 and even more if an offset-PLL with normal frequency position is used. It has to be considered, that some effects in the PLL, which are only inuenced by one of both quantities in the loop gain, still vary over the frequency ramp. For example modulation effects of the VCO (especially due to thermal supply noise or noise on the tuning voltage) are still stronger for a higher sensitivity at lower VCO frequencies. Otherwise, the fractional noise is stronger for smaller -values (due to the larger relative -variation), which would dominate at high VCO frequencies. But there the tuning sensitivity and thus the noise modulation is low resulting in constant fractional noise during the frequency ramp. III. TRANSCEIVER CHIP IMPLEMENTATION For a low-power implementation, a single-chip SiGe radar transceiver is used with the block diagram in Fig. 1. The transmitter part of this chip is based on [8]. The main oscillator
5Especially in a PLL with a xed -Divider and varied reference frequency (e.g. generated from a direct digital synthesizer (DDS)) the suppression of unwanted spurious frequencies within the loop bandwidth can be challenging.

a dielectric resonator (DRO), here a PLL is used for less mechanical production effort (placing and aligning the DRO) and better noise performance close to the carrier, thus increasing the long-term stability.
4Here, only the division factor of 4 of the prescaler appears in the main PLL, without the offset mixing a constant prescaler of 12 would have to be used for dividing the frequency of 80 GHz below 7 GHz, which can be handled by conventional fully programmable fractional-N PLL chips.



was obtained. The Gilbert-Cell do not use any LC-resonance circuits. Therefore, the behavior of the noise gure, gain, and compression point is ultra-wideband with less than 3 dB variation in the full frequency band. The conversion gain of 12 dB of the mixer is further increased using an external dc-blocked to 150, depending on IF amplier with adjustable gain ( the radar scenario and antenna gain). For on-chip matching of the mixer inputs, short series transmission lines with inductive behavior in combination with series DC-block capacitances are used, resulting in an RF-matching below 20 dB and a sufcient LO-matching below 10 dB (simulated, in the full frequency band of interest). B. Receive/Transmit Coupler Structure For monostatic radar operation, a passive integrated differential transmit/receive coupler structure is used. Commonly, an integrated rat-race coupler is the concept of choice (e.g. [5], [9]). However, here a combination of Wilkinson dividers is used. This separates the transmit and receive coupler and offers the opportunity to integrate attenuators6 into the transmit path between both Wilkinson dividers in order to prevent compression of the mixer due to strong reecting targets. The conceptual additional loss of 3 dB of transmit power compared to a single rat-race coupler [5] is acceptable and further reduces possible compression of the mixer and decreases reections. A transmission line-based Wilkinson divider (e.g. [26]) m with would result in a very large structure high losses. Here, a compact lumped element implementation is realized as a planar is used [Fig. 5(a)]. The inductor spiral inductor [see Fig. 5(b)] with approx. the ideal value pH. The capacitances have to be fF consmaller than the ideal value sidering the substrate capacitances of the spiral inductor. The overall size of the realized structure, including a bounding box, m m. is This results in the EM-simulated S-parameters in Fig. 5(c).7 The loss of the Wilkinson divider is approx. 0.3 dB (additionally to the ideal insertion loss of 3 dB). The matching at all three ports and the decoupling between them is below 17 dB in the full frequency band of interest (68 GHz to 93.6 GHz). C. mm-Wave Bond Matching The realization of an ultra-wideband well matched bond interface considering possible mass production constraints is a challenging design goal. Therefore, the chip (185 m thick) is placed inside a cavity in the mm-wave substrate for short differential bond wires.8 Using these optimized short bond wires 4 dB. Therefore, on-chip two planar results in a matching of spiral inductors, a series capacitance and a transmission line [see Fig. 6(a)] are used for matching the bond inductance and the pad capacitance to a 50 interface on both ports. Additionally,
6Different values of attenuation can be chosen by cutting fuses after fabrication. With this concept it is even possible to integrate an additional amplier in the transmit path for higher transmit power. 7Simulations of the full divider were performed using the 2.5D EM simulator for the silicon dioxide and a from Sonnet Software Inc. with . copper conductivity of 8The use of differential bond wires drastically reduces its inductive effects due to the resulting symmetry plane (that acts as an electric wall and increases the mutual inductance, cp. [18]).

Fig. 4. Schematic diagrams for illustration of the PLL linearization technique. The tuning sensitivity of the VCO itself is given in (a). In (b) the tuning sensitivity after 4 and mixing is compared to the necessary frequency divider for reaching the reference frequency of e.g. 25 MHz. Finally, the quotient of the downconverted tuning sensitivity and the -Divider (c) shows a very at behavior along the full tuning range.

output at 80 GHz is divided by four (dynamic divider) and afterwards mixed down using a second integrated local oscillator (VCO) around 24 GHz (offset-PLL). Additionally, a static 8 frequency divider is used for stabilization of the local oscillator (PLL2). Both control signals for the PLLs are below 7 GHz, which simplies the interfaces and enables the use of conventional PLL chips. Compared to [8], this 80 GHz oscillator has lower power dissipation at lower output power. All circuits are designed for a single common supply voltage of 5 V (given by the 80 GHz VCO). In the following sections, the receive mixer (Section III-A), coupler structures (Section III-B), mm-wave bond interface (Section III-C) and nally some overall results (Section III-D) are discussed. For further details on the transmitter components see [8]. The development of wideband components, which can utilize the full frequency band of the oscillator with a good overall performance was the main design goal in this work. A. Receive Mixer The receive mixer determines the dynamic range and the transmit/receive power level in a monostatic FMCW radar system. Thus, a wide dynamic range is an important design criterion. Therefore, a fully differential Gilbert-Cell is used. The dynamic range was improved by inductive degeneration in the RF input stage (for details see [25]). This enables a wide dynamic range with a moderate tail current of 9 mA (overall current consumption including bias networks: 13 mA). A noise gure of 12 dB only and a high input referred 1 dB compression point of 1.2 dBm at a LO drive power around 0 dBm (which can easily be generated using the on-chip 80 GHz VCO)



Fig. 6. Broadband matching network for bond wire and pad capacitance. (a) Schematic. (b) Simulated S-Parameters. The bond wire and its environment were simulated using a full 3D EM-Solver (CST Microwave Studio) with different wire lengths.

Fig. 5. Compact Wilkinson divider consisting of lumped elements. (a) Simplied schematic. (b) Realization with compact spiral inductors. (c) Simulated S-parameters (due to symmetry only four of the nine curves are plotted).

the inductance to ground can be used for biasing oras done herefor ESD protection of the sensitive mm-wave interface. The structure is optimized for various bond wire lengths using numerical Monte-Carlo techniques. The resulting values for matching in Fig. 6(b) are excellent, with an insertion loss of 1.2 dB, for the intended bond wire length of 300 m 15 dB in the full band) and stays below 10 dB for a wide ( variation of bond wires length between 200 m and 400 m. D. Results A photograph of the complete transceiver chip is given in Fig. 7. It occupies 3 mm , dened by the necessary padframe. Additional to the necessary RF-interfaces (cp. Fig. 1) and bias pads, many additional pads for testing are included. The largest circuits are both oscillators and the receive mixer, whereas the area occupied by the frequency dividers, PLL-mixers, Wilkinson dividers and matching is nearly negligible. Due to the low power implementation, the complete power consumption of the transceiver chip is below 0.5 W (Table I)a quite low value for a radar transceiver at frequencies around 80 GHz.

Fig. 7. Photograph of the realized 80 GHz transceiver chip. The overall chip size is 1.9 mm 1.6 mm (given by the number of pads).

IV. IMPLEMENTATION OF THE RADAR SYSTEM The transceiver chip is placed in a mm-wave substrate (Rogers RT/duroid 5880, 127 m thick, Fig. 8), which is mounted on a brass block for enhanced mechanical stability and thermal conductivity. The differential 80 GHz interface of the transceiver is combined using a rat-race coupler and is nally fed to a waveguide port (WR10), which is realized using the mm-wave substrate and brass block with an aluminum lid placed above the waveguide (upper left corner of Fig. 8). For radar measurements, various standard horn antennas can be




Fig. 9. Output power of the VCO, transceiver-chip and the complete radar system at the waveguide port (WR-10). VCO and chip outputs were measured on-wafer, whereas the waveguide output was measured using the mounted chip in the mm-wave substrate.

Fig. 10. Photograph of the PLL board. Connectors on the backside are used for connecting the mm-wave module. Fig. 8. Photograph of the mm-wave module. The chip and the mm-wave substrate are mounted on a brass block.

connected to the mm-wave module. Additionally, a low-noise IF-amplier and PLL-connectors are mounted on the substrate. For characterization of the realized mm-wave module the output power at the waveguide port was measured and compared with the output power of the VCO and the transceiver chip (see Fig. 9).9 The VCO delivers a quite high and at output power between 6 and 7 dBm in the full frequency range. Due to the losses of two Wilkinson dividers, transmission lines, and the interface matching, the output power of the transceiver chip is attenuated by 8 dB and varies between 3 and 1 dBm. Finally, the output power at the waveguide port is around 4 dBm and varies only by 3 dB in the complete ultra-wide frequency band of 26.5 GHz. The implementation of the PLL is based on conventional PLL chips on an additional FR4 board (see Fig. 10). For the 80 GHz PLL and the 24 GHz PLL, the Hittite ICs HMC701 and HMC704 were used, respectively. They consist of a fractional frequency divider, a low noise phase frequency detector, control blocks and (in case of the HMC701) an integrated fractional sweep generator. Both PLLs use a higher order active loop lter based on a low noise operational amplier (LT6202).10 The 24 bit fractional-N architecture allows for frequency steps as ne as 8 Hz and almost any desired frequency ramp duration from less than 1 ms up to more than 1 s.
9The frequency ranges of the curves differ, due to higher self heating in the on-chip measurements (VCO, Chip). Additionally, the matching network for the on-chip measurements had to be adjusted, which makes a complete comparison difcult.

The 24 GHz PLL limits the overall phase noise performance. To minimize its inuence, we applied the maximum possible full XCO frequency of 100 MHz in an integer-N xed frequency PLL. Its 4th order loop lter is chosen for optimal noise performance with a loop bandwidth of 740 kHz at 4th order. For the demanding 80 GHz PLL, a 5th order RLC loop lter with a loop bandwidth of 430 kHz and a reference frequency of 33 MHz was used.11 The simulated12 phase noise of the 80 GHz VCO at center and its noise contributions are plotted in Fig. 11. Close to the carrier (below 100 kHz), the phase noise is limited by the 24 GHz VCO.13 For higher offset frequencies, the phase noise is dominated by the phase noise of the 80 GHz VCO itself. A slight inuence of the fractional noise ( ) can be seen for offset frequencies around 2 MHz, as the suppression of the loop lter is not strong enough in this region. All other noise contributions can be neglected. The overall phase noise is below 80 dBc/Hz for all offset frequencies 1 kHz. For a perfectly constant open loop transfer function (cp. Section II-C), the three dominating curves in this diagram stay constant during the frequency ramp. However, for the real oscillator described in Section II-A the increased phase noise especially at lower oscillation frequency (approx. by 7 dBc/Hz) has to be considered. Additionally, the thermal noise of the loop
11A higher reference frequency is advantageous for reducing the phase noise but limits the frequency bandwidth of the PLL using the minimum possible -divider value (cp. (2)). 12The noise simulations were done using the phase noise simulator provided by Hittite Microwave Corporation. 13Further noise improvement can thus be achieved, if for the xed frequency 24 GHz PLL, a much higher reference frequency is used (e.g. 1 GHz), resulting in higher effort and current consumption.

lter uses an additional supply voltage (9.5 V) for generating the necessary high tuning voltage for the VCO.




Fig. 11. Simulation of the phase noise contributions of the 80 GHz oscillator and the total noise. TABLE II OVERVIEW OF THE POWER DISSIPATION OF THE RADAR SYNTHESIZER

Fig. 13. Measured spectrum at the mm-wave output around the center fre. The measurements were perquency in fractional mode formed using a spectrum analyzer (Agilent 8565E) with an external downconversion mixer (Agilent 11970W).

Fig. 14. Phase noise measurements of the stabilized VCO in the fractional-N PLL. The phase noise was measured using a spectrum analyzer at the 4 output by adding 12 dB. For each point of the curve four measurements are averaged.

Fig. 12. Photograph of the complete radar system using a standard horn antenna at the waveguide port.

lter is increased for higher tuning sensitivity (low oscillation frequencies) and the PFD noise increases with high -divider values (also low oscillation frequencies). Furthermore, there is a 16 bit analog-to-digital converter with 1 MSample/s (ADS8329) for digitizing the received signals, some control logic, an USB interface to a computer and power supply circuits on the PLL-board. The signal processing is done in the computer. In Table II the power dissipation of the components of the radar system is given. The total power dissipation is below 1.5 W for the complete radar system. Here, only the power dissipation of the components shown in Fig. 1 is considered excluding overhead for the supply voltage generation. A photograph of the complete system including the mm-wave module, the PLL board and a horn antenna is shown in Fig. 12. V. SYSTEM RESULTS For the results presented in this section the frequency of the offset-VCO is chosen as 24.8 GHz, allowing for a frequency range of 25.6 GHz. Compared to Fig. 4 the frequency range is

further increased at the cost of a moderately increased variation of the PLLs loop gain. However, it is still below 2:1. The frequency ramp duration was chosen to be 4 ms, which results in a high ramp slope of 6.6 GHz/ms. Fig. 13 shows a measured spectrum of the 80 GHz output without any spurious signals or disturbances. The measured phase noise of the PLL-stabilized 80 GHz VCO is given in Fig. 14 for various frequencies. The in-loop phase noise is between 90 and 85 dBc/Hz for the center frequency, which matches well to the simulations (cp. Fig. 11), and is nearly unchanged for high output frequencies of 90 GHz and even 93.6 GHz. For low output frequencies, the in-loop phase noise is slightly increased14 with a small rise around the loop bandwidth due to reduced phase margin, but it still stays below 80 dBc/Hz.15 All together, the phase noise is very low and constant in the full frequency range of the VCO (cp. [11], [14]). Only in [13] a comparable phase noise was achieved using a much higher reference frequency of 700 MHz. Thus, this radar system is well suited for stable radar measurements with a high dynamic range even with very fast frequency ramps. In Fig. 15, the received IF signal of a measurement setup with one corner reector as a strong target is given. A fast monotone oscillation can be surmised, as expected for this scenario. The
14The increased phase noise results partially from the increased lter noise due to the higher tuning sensitivity of the VCO. 15Due to divider value limitations of the used PLL synthesizers, for full bandwidth operation, the auxiliary oscillator was chosen as 24.8 GHz, which is not the optimum for PLL linearization (see Section II-C). This increases the loop gain variation from 1:1.2 (as in Section II-C) to 1:1.7, resulting in a reduced phase margin at lower frequencies.



Fig. 15. Measured IF signal using the full 25.6 GHz bandwidth.

Fig. 17. Deviation of multiple distance measurements (compared to the mean value). A simple pulse center algorithm was used for signal processing.

outperforms the state of the art [3], [4], [10] and shows that the ultra-wide bandwidth of the presented radar system is almost completely usable. To increase the dynamic range (especially better detection of small targets in the vicinity of large targets), typically window functions (e.g. Hann, Blackmann window) are used, which reduce the resolution. However, even with a Hann window the resolution is still 11.69 mm. Typically the repeatability of mono target radar measurements is much better than the resolution, as it mainly depends on the achieved phase noise. One hundred distance measurements of the same target were performed (Fig. 17), determining the position of the target with a simple pulse center algorithm. The deviation of the measured distance to the average distance is plotted. The maximum deviation is below 1 m with an excellent standard deviation of 0.36 m. VI. CONCLUSION In this paper, several techniques of radar systems with an ultra-wide bandwidth are discussed. Especially the use of an offset-PLL with a mixer in reverse frequency position enables to compensate the variation of the oscillators loop gain with the variation of the -divider for fractional frequency ramps. The mm-wave transceiver components of the 80 GHz radar system are full integrated on a SiGe chip, achieving an ultra-wide frequency bandwidth of 26.5 GHz, whereof 25.6 GHz can be stabilized in the PLL. A very constant performance of phase noise and output power was reached in the full system bandwidth due to carefully optimized ultra-wideband components. Overall, the radar system achieves an outstanding spatial resolution of 7.12 mm, which is in the region formerly only achievable using laser or ultrasonic techniques. The stability of the measured distance shows an excellent standard deviation as low as 0.36 m. ACKNOWLEDGMENT The authors would like to thank Inneon Technologies AG and its staff members for fabricating the chips, and H.-M. Rein and T. Musch for their helpful discussion regarding the realization of the integrated circuits and the PLL. REFERENCES
[1] C. Metz, J. Grubert, J. Heyen, A. F. Jacob, S. Janot, E. Lissel, G. Oberschmidt, and L. C. Stange, Fully integrated automotive radar sensor with versatile resolution, IEEE Trans. Microw. Theory Tech., vol. 49, no. 12, pp. 25602566, 2001.

Fig. 16. Spectrum of the measured IF signal (Fig. 15) in the range up to 3 m (a) and a detailed view of the target (b). No window function or amplitude correction is applied. A corner reector is placed 2 m behind the antenna. The achieved resolution (6 dB-width) of 7.12 mm is close to the ideal value of 7.05 mm.

envelope of the IF signal varies due to interfering reections of the antenna, but it is very at in the frequency range, which corresponds to the low variation of output power and conversion gain. Only after the spectrum [Fig. 16(a)] of this signal is derived from a simple discrete Fourier transformation (no window function or amplitude correction is used) it reveals the radar scenario. In close distance (below 0.1 m) the reections of the used horn antenna can be seen. A strong and narrow target is located approximately 2 m behind the antenna. The detailed view of the target [Fig. 16(b)] shows a good agreement of the main lobe with the ideal si-pulse, which let expect a sufciently high ramp linearity. The 6-dB width, dened as the spacial resolution of the system, is 7.12 mm, which is very close to the theoretical value of 7.05 mm for this bandwidth using a rectangular window in the frequency domain. Ringing after the main lobe is caused by a non-ideal corner reector. This ultra high resolution clearly



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Nils Pohl (S07M11) was born in Aachen, Germany, in 1980. He studied electrical engineering at the Ruhr-University Bochum, where he received the Dipl.-Ing. and Dr.-Ing. degrees in 2005 and 2010, respectively. From 2006 to 2011, he was a Research Assistant with the Institute of Integrated Systems, Ruhr-University Bochum working on system concepts and integrated circuits for mm-wave radar applications and antenna design. In 2011 he became assitant professor for Integrated Systems at the Ruhr-University Bochum. His current elds of research are concerned with frequency synthesis, millimeter wave radar systems around 80 GHz and above. Prof. Pohl is a member of the VDE and ITG. Timo Jaeschke (S07) was born in Hattingen, Germany, in 1984. He received the Dipl.-Ing degree in electrical engineering at the Ruhr-University Bochum in April 2011. Since May 2011, he has been a Research Assistant with the Institute of Integrated Systems, Ruhr-University Bochum. His current elds of research are concerned with frequency synthesis, fractional-N PLLs, integrated ultra wideband radar systems, high resolution SAR imaging and antenna arrays for various applications. Dipl.-Ing. Jaeschke is a member of VDE, ITG, and DGON. Klaus Aunger (M10) was born in Kirchbichl, Austria, in 1966. He received the diploma and the Ph.D. degrees in physics from the University of Innsbruck, Austria, in 1990 and 2001, respectively. From 1990 to 1991, he was a Teaching Assistant with the Institute of Theoretical Physics, University of Innsbruck. In 1991, he joined the Corporate Research and Development of Siemens AG, Munich, Germany, where he investigated noise in submicron bipolar transistors. Now he is with Inneon Technologies, the former semiconductor group of Siemens, Munich, working in the eld of device physics, technology development and modeling of advanced SiGe technologies for high-speed digital and analog circuits.