AXI

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1. Introduction [1] 2. How AXI Works [2] 2.1. Some Infrastructure IP 3. AXI Support in Xilinx Tools and IP [2] 3.1. System Generator 3.2. Core Generator 3.3. Xilinx AXI Infrastructure IP 3.3.1. Xilinx AXI Interconnect Core IP 4.1. Using Sysgen for migrating IP 5. References 4. Migrating to Xilinx AXI Protocols

1. Introduction [1]
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AXI = Advanced eXtensible Interface Part of AMBA (Advanced Microcontroller Bus Architecture)

Communications bet. processor core and peripherals

AXI - interface and protocol def., not a bus standard

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Should migrate from PLB46 for next-gen compatability. If designs only use Virtex-6 and Spartan-6, no need to do so. AXI does not define specs of Interconnects Only interface spec. 3 configs supported by Xilinx:

AXI4 Streaming: AXI4-Stream

Memory-mapped: Lite - reduced arch resources:

AXI4-Lite

Less HW

Suitability:

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Why use AXI? Higher performance Easier to use Enable ecosystem sharing Design Conversion:

Re-building embedded system is usually best IP is "drag-and-drop" Custom IP...:

If built by IP Wizard, can be migrated using a template: http://www.xilinx.com/support/answers/37425.htm If cannot be altered to AXI: Add the AXI-to-PLB bridge component See AXI reference guide,

UG761.

2. How AXI Works [2]

AXI spec. describe an interface btw a single AXI master and a single AXI slave.
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Master and slave are IP cores. Memory-mapped AXI masters and slaves can be connected using AXI Interconnect IP

Route transactions btw one or more AXI masters and slaves Read address Write address Read data Write data Write response

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AXI4 (w/ burst mode) and AXI4-Lite (single only) has 5 channels:

Data moves in both directions freely. Transfer sizes: AXI4: burst of up to 256 data transfer AXI4-Lite: only 1 data transfer

Read channels:

Write channels:

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Notes:
Separate data and address connections for Simultaneous, bidirectional data transfer.

Read and Write.

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AXI4 can achieve very high data throughput: Bursting: one address, up to 256 words of data data upsizing and downsizing multiple outstanding address Out-of-order transaction processing In hardware:

Different clk for each AXI master-slave pair Insertion of register slices (pipeline stages) Help timing closure

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AXI4-Lite: Single transfer mode, no streaming AXI4-Stream: Only a single channel for transmission of streaming data from 1 IP to another
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Same as Write Data channel of AXI4 Burst of unlimited amount of data Streamed transfers cannot be re-ordered.

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2.1. Some Infrastructure IP

Generic IPs that moves and transforms data around the system using general-purpose AXI4 interface, but does not interpret data:
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Register slices (pipelining) AXI FIFOs (for buffering / clock conversion) AXI Interconnect IP (connects memory mapped IP together) AXI DMA engines (memory-mapped to stream convertion) Memory-mapped protocol: All transactions involve the concept of a target address within system memory space and data to be transferred. AXI4-Stream protocol: Data-centric and data-flow paradigm Address not required Single unidirectional channel for a handshake data flow Combined design: Combine AXI4-Stream and AXI memory mapped IP together

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DMA engine move streams in and out of memory Processor work w/ DMA engines to decode packets

3. AXI Support in Xilinx Tools and IP [2]

How Xilinx tools can be used to build systems of interconnected Xilinx AXI IP
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XPS System Generator Deploy individual IPs using Coregen Debugging: using Chipscope in XPS Chipscope Pro Analyzer AXI core:

chipscope_axi_monitor Useful for AXI4 and AXI4-Lite

Probe any AXI, memory-mapped master or slave bus interface

Observe AXI signals going from pcore to AXI Interconnect core Ex: monitor MB processor instruction & data interface Memory transactions Each monitor core works independently

Chaining of trigger outs to enable system-level measurements Multi-level triggering Ex: master at 100 MHz, slave at 50 MHz multi-tiered triggering to analyzer transfer of data going from one clock domain to next. Latency bottlenecks

Steps for adding

chipscope_axi_monitor to monitor Bus: Connect core to Bus using Bus Name field Look for an "M" sign Add Chipscope ICON and connect In 'Ports' tab, set up MON_AXI_ACLK port of the core

to match the clk used by AXI interface being probed

Assign MON_AXI_TRIG_OUT port to connect to another chipscope_axi_monitor core.

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3.1. System Generator

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Sysgen support

AXI4 and AXI4-Stream AXI4 needs EDK Processor block AXI4-Stream supported in IPs found in Sysgen AXI4 block EDK Processor block

library Memory-mapped support through Connect HW circuits to MB Create HW that uses shared registers, shared FIFOs, and shared memories, and EDK Processor block manages memory connections to the interface. Port Groupings:
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Sysgen groups together and color-codes blocks of AXI4-Stream channel signals:

data_tready, data_tvalid, data_tdata_sine - 1 set signals for a stream channel phase_tready, phase_tvalid, phase_tdata - another set aresetn - Signals not part of any AXI4Stream channels has same background color as block.
Ex:

Data channels can be broken out into multiple channels (I and Q for examples):

Automatically byte-aligned

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3.2. Core Generator

Xilinx IP w/ AXI4 interface (master or slave) can be accessed directly from IP core catalog in Coregen, Project Navigator, and PlanAhead.

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3.3. Xilinx AXI Infrastructure IP

3.3.1. Xilinx AXI Interconnect Core IP axi_interconnect - connect 1 or more AXI memory-mapped
master devices to memory-mapped slave devices
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Standard: AMBA AXI v4 spec For memory-mapped transfers only. applicable

AXI4-Stream transfer not

AXI4-Stream IPs connected to one another, and to DMA

IP Encrypted, non-licensed free core.

4. Migrating to Xilinx AXI Protocols

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4.1. Using Sysgen for migrating IP

5. References
[1] Video tutorial: http://www.xilinx.com/training/embedded/how-to-converta-plb-based-embd-system-to-an-axi-based-system-video.htm [2] AXI Reference Guide - Xilinx UG761 (Mendeley)