Small Signal Parameters of MOSFET

EE 332

DEVICES AND CIRCUITS II

Lecture 8 Small-Signal Modeling and Linear Amplification (3)
Since gate is insulated from channel by gate-oxide input resistance of transistor is infinite. Small-signal parameters are controlled by the Q-point. For same operating point, MOSFET has higher transconductance and lower output resistance that BJT.

Transconductance: I D gm = y = = 2K n I 21 V V D GS TN 2 Output resistance: 1 +V 1 DS 1 = ro = y I I D D 22 Amplification factor for VDS<<1:

= gmro = f

+V DS 1 2Kn ID I D

Small Signal Operation of MOSFET

2 Kn v v V V v for TN DS GS TN 2 GS Kn 2 V i = I + i = V + 2 v gs V V + v gs 2 D D d GS 2 TN TN GS Kn 2 2 v gs V i = V + v gs d 2 TN GS i D =

Body Effect in Four-terminal MOSFET

Drain current depends on threshold voltage which in turn depends on vSB. Back-gate transconductance is: i i g = D = D mb v v BS Q po int SB Q po int

( (

) )

V v gs << 0 .2 V TN GS Since MOSFET can be biased with (VGS - VTN) equal to several volts, it can handle much larger values of vgs than corresponding values of vbe for BJT. Change in drain current that corresponds to small-signal operation is: i V 0 .2(V ) TN 0 .4 d = gm v = GS gs V V I I TN GS D D 2

For linearity, id should be proportional to vgs

i = D V TN

V TN = ( gm ) = gm v SB Q po int

0<<1 is called back-gate tranconductance parameter. Bulk terminal is a reverse-biased diode. Hence, no conductance from bulk terminal to other terminals.

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Small-Signal Model for PMOS Transistor

For pnp transistor v =V -v SG GG gg i = I -i C D d Positive signal voltage vgg reduces source-gate voltage of the PMOS transistor causing decrease in total current exiting drain, equivalent to increase in signal current entering drain.

Small-Signal Analysis of Complete C-S Amplifier: AC Equivalent

Ac equivalent circuit is constructed by assuming that all capacitances have zero impedance at signal frequency and dc voltage sources represent ac grounds. Assume that Q-point is already known.

=R R 1 2

Small-Signal Analysis of Complete C-E Amplifier: Small-Signal Equivalent

v v Avt = v d = v o = g m R L g gs
Overall voltage gain from source vi to output voltage across R3 is: v v v v gs gs o Av = vo = = A vt v gs v v i i i R G Av = g m R L +R R I G

C-S Amplifier Voltage Gain: Example

Problem: Calculate voltage gain Given data: n = 0.5 mA/V2, VTN = 1V, = 0.0133 V-1, Q-point is (1.45 mA, 3.86 V), R1 = 430 k, R2 = 560 k, R3 = 100 k, RD = 4.3 k, RI = 1 k. Assumptions: Transistor is in active region. Signals are low enough to be considered small signals. Analysis: gm = 2K I (1+ V ) = 1.23mS R G = R1 R = 243 k n DS 2 DS 1 +V ro = DS = 54.5k R L = ro R D R 3 = 3 . 83 k I D 2I R D = 0.48V G = 4.69 =13.4dB V 0.2 V v 0.2 Av = gmR i TN L GS Kn R +R G I

= ro R R D 3

Terminal voltage gain between gate and drain is:

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Small-Signal Model Simplification

If we assume

C-S Amplifier Input Resistance

R << R I G

Av Avt = g m R = g m r R R o L D 3 This implies that total signal voltage at input appears across gate-source terminals.
Generally R3 >> RD and load resistor << ro. Hence, total load resistance on drain is RD. For this case, common design allocates half the power supply for voltage drop across RD and (VGS - VTN ) =1V I R D D Av g m R = = V D DD V V TN GS 2 Also, if load resistor is forced to approach ro, RD and R3 are infinite, voltage gain is limited by amplification factor, f of MOSFET itself.

Input resistance of C-S amplifier is much larger than that of corresponding C-E amplifier.

v x = ix R G R =R G in

C-S Amplifier Output Resistance

Sample Analysis of C-S Amplifier

Analysis: Dc equivalent circuit is constructed.

For comparable bias points, output resitances of C-S and C-E amplifiers are similar. In this case, vgs=0.
Problem: Find voltage gain, input and output resistances. Given data: n = 500 A/V2, VTN = 1V, = 0.0167 V-1

I = 1

V DS 5 10 6

v Rout = x = R ro R D D As ro>> RD. ix

= 10 2 10 4 ( I + I ) D 1 DS Kn V I = (0 . 4V )2 D TN DS 2 V = 5V DS V = 2V I = 25 0 A D GS V

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Sample Analysis of C-S Amplifier (contd.)

Next we construct the ac equivalent and simplify it.
R =R R = 1M G1 G 2 in

Small Signal Parameters of JFET

i 1 =y = G 11 v r GS
gm = y

I +I = G SG V T Q point
= I V GS D V P 2

gm = 2Kn I (1+ V ) = 5.20 104S DS DS +V ro = DS = 260k I D 1

R out = ro R R = 18 . 2 k D G3 R vo in = 7 .93 Av = = gm ( Rout R ) 3 R + R v I i in

v i =I 1 GS D DSS V P

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i v

1+ v

DS

GS Q point

for v DS vGS V P
exp GS 1 i =I G SG V T

I 2 DSS (V V ) P V 2 GS P

i 1 =y = D 22 ro v DS

=
Q point

D +V DS 1

Small Signal Model of JFET

For small signal operation, condition on input is:
V vgs << 0.2 V P GS

Sample Analysis of JFET C-S Amplifier

Analysis: Dc equivalent circuit is constructed. G = 0, S = D. V = 2000 I 2 D GS V GS = (2 103)(110 3) 1 V GS ( 1) Choose VGS less negative than VP.

Since JFET is normally operated with gate junction reversebiased,

I = I SG G rg =

Amplification factor is given by: 1 +V I DS 2 DSS = gmro = 2 I f V V V D GS P P

Problem: Find voltage gain, input and output resistances. Given data: DSS = 1 mA, VP = -1V, = 0.02 V-1 Assumptions: Pinch-off region of operation.

V = 0 .5V GS I = 0 .250 mA D

12 = 27,000 I V DS

+V + 2000 I D DS S = 4 .75V

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Sample Analysis of JFET C-S Amplifier (contd.)

Next we construct the ac equivalent and simplify it.

Amplifier Power Dissipation

Static power dissipation in amplifiers is determined from their dc equivalent circuits.

R = R = 1M G in

gm =

2 I I (1+ V ) = 1.05mS DSS DS DS V P R out = ro R = 24 . 0 k D 1 +V R v in = 20 .3 ro = DS = 219k Av = o = gm ( Rout R ) 3 I v R + R DS i in I

Total power dissipated in C-B and E-B junctions is:

P =V I +V I where V =V +V D CE C BE B CE CB BE

Total power dissipated in transistor is:

P =V I +V I =V I D DS D GS G DS D Total power supplied is: P =V I S DD D

Total power supplied is:

P =V I +V I S CC C EE E

Amplifier Signal Range

0 .7 V v =V V sin t But v CE M CE CE V M V CE V BE

(t ) = I R + V sin t 0 R M C C C But V I R M C C

Also v

End of Lecture 8

min V R ,V I BE CE C C

Similarly for MOSFETs and JFETs,

V M M min I

R , (V (V V )) D D DS TN GS R , (V (V V )) D D DS P GS

min I

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