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Hardware Description
02 2007-03-29 00384267
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The information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but the statements, information, and recommendations in this document do not constitute a warranty of any kind, express or implied.
Contents
Contents
About This Document.....................................................................................................................1 1 Equipment Structure.................................................................................................................1-1 2 Cabinet.........................................................................................................................................2-1
2.1 Cabinet Type...................................................................................................................................................2-2 2.2 Cabinet Configuration.....................................................................................................................................2-2 2.2.1 Cabinet Indicator....................................................................................................................................2-3 2.2.2 DC PDU.................................................................................................................................................2-3 2.2.3 Other Configuration...............................................................................................................................2-4 2.3 Technical Specifications.................................................................................................................................2-5
3 Subrack.........................................................................................................................................3-1
3.1 Structure..........................................................................................................................................................3-2 3.2 Capacity...........................................................................................................................................................3-3 3.3 Slot Allocation.................................................................................................................................................3-4 3.4 Slot Allocation...............................................................................................................................................3-13 3.5 Technical Specifications...............................................................................................................................3-24
Contents
OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description 5.1.2 Function and Feature..............................................................................................................................5-4 5.1.3 Working Principle and Signal Flow.......................................................................................................5-5 5.1.4 Front Panel.............................................................................................................................................5-7 5.1.5 Valid Slots..............................................................................................................................................5-8 5.1.6 Board Feature Code................................................................................................................................5-9 5.1.7 Board Configuration Reference.............................................................................................................5-9 5.1.8 Technical Specifications........................................................................................................................5-9
5.2 SL1A.............................................................................................................................................................5-11 5.2.1 Version Description..............................................................................................................................5-11 5.2.2 Function and Feature............................................................................................................................5-11 5.2.3 Working Principle and Signal Flow.....................................................................................................5-12 5.2.4 Front Panel...........................................................................................................................................5-14 5.2.5 Valid Slots............................................................................................................................................5-15 5.2.6 Board Feature Code..............................................................................................................................5-15 5.2.7 Board Configuration Reference...........................................................................................................5-15 5.2.8 Technical Specifications......................................................................................................................5-15 5.3 SLQ1.............................................................................................................................................................5-17 5.3.1 Version Description..............................................................................................................................5-17 5.3.2 Function and Feature............................................................................................................................5-18 5.3.3 Working Principle and Signal Flow.....................................................................................................5-19 5.3.4 Front Panel...........................................................................................................................................5-21 5.3.5 Valid Slots............................................................................................................................................5-22 5.3.6 Board Feature Code..............................................................................................................................5-23 5.3.7 Board Configuration Reference...........................................................................................................5-23 5.3.8 Technical Specifications......................................................................................................................5-24 5.4 SLQ1A..........................................................................................................................................................5-25 5.4.1 Version Description..............................................................................................................................5-26 5.4.2 Function and Feature............................................................................................................................5-26 5.4.3 Working Principle and Signal Flow.....................................................................................................5-27 5.4.4 Front Panel...........................................................................................................................................5-28 5.4.5 Valid Slots............................................................................................................................................5-30 5.4.6 Board Feature Code..............................................................................................................................5-30 5.4.7 Board Configuration Reference...........................................................................................................5-30 5.4.8 Technical Specifications......................................................................................................................5-30 5.5 SLO1.............................................................................................................................................................5-32 5.5.1 Version Description..............................................................................................................................5-32 5.5.2 Function and Feature............................................................................................................................5-32 5.5.3 Working Principle and Signal Flow.....................................................................................................5-33 5.5.4 Front Panel...........................................................................................................................................5-35 5.5.5 Valid Slots............................................................................................................................................5-37 5.5.6 Board Feature Code..............................................................................................................................5-37 5.5.7 Board Configuration Reference...........................................................................................................5-37 ii Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
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5.5.8 Technical Specifications......................................................................................................................5-38 5.6 SLT1..............................................................................................................................................................5-39 5.6.1 Version Description..............................................................................................................................5-39 5.6.2 Function and Feature............................................................................................................................5-39 5.6.3 Working Principle and Signal Flow.....................................................................................................5-40 5.6.4 Front Panel...........................................................................................................................................5-42 5.6.5 Valid Slots............................................................................................................................................5-44 5.6.6 Board Configuration Reference...........................................................................................................5-44 5.6.7 Technical Specifications......................................................................................................................5-44 5.7 SEP1..............................................................................................................................................................5-45 5.7.1 Version Description..............................................................................................................................5-46 5.7.2 Function and Feature............................................................................................................................5-46 5.7.3 Working Principle and Signal Flow.....................................................................................................5-47 5.7.4 Front Panel...........................................................................................................................................5-50 5.7.5 Valid Slots............................................................................................................................................5-52 5.7.6 TPS Protection for the Board...............................................................................................................5-52 5.7.7 Board Configuration Reference...........................................................................................................5-53 5.7.8 Technical Specifications......................................................................................................................5-54 5.8 SL4................................................................................................................................................................5-54 5.8.1 Version Description..............................................................................................................................5-55 5.8.2 Function and Feature............................................................................................................................5-55 5.8.3 Working Principle and Signal Flow.....................................................................................................5-56 5.8.4 Front Panel...........................................................................................................................................5-58 5.8.5 Valid Slots............................................................................................................................................5-60 5.8.6 Board Feature Code..............................................................................................................................5-60 5.8.7 Board Configuration Reference...........................................................................................................5-61 5.8.8 Technical Specifications......................................................................................................................5-61 5.9 SL4A.............................................................................................................................................................5-62 5.9.1 Version Description..............................................................................................................................5-63 5.9.2 Function and Feature............................................................................................................................5-63 5.9.3 Working Principle and Signal Flow.....................................................................................................5-64 5.9.4 Front Panel...........................................................................................................................................5-65 5.9.5 Valid Slots............................................................................................................................................5-67 5.9.6 Board Feature Code..............................................................................................................................5-67 5.9.7 Board Configuration Reference...........................................................................................................5-67 5.9.8 Technical Specifications......................................................................................................................5-67 5.10 SLD4...........................................................................................................................................................5-68 5.10.1 Version Description............................................................................................................................5-69 5.10.2 Function and Feature..........................................................................................................................5-70 5.10.3 Working Principle and Signal Flow...................................................................................................5-71 5.10.4 Front Panel.........................................................................................................................................5-73 5.10.5 Valid Slots..........................................................................................................................................5-74 Issue 02 (2007-03-29) Huawei Proprietary and Confidential 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Contents
OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description 5.10.6 Board Feature Code............................................................................................................................5-75 5.10.7 Board Configuration Reference.........................................................................................................5-75 5.10.8 Technical Specifications....................................................................................................................5-76
5.11 SLD4A........................................................................................................................................................5-77 5.11.1 Version Description............................................................................................................................5-77 5.11.2 Function and Feature..........................................................................................................................5-77 5.11.3 Working Principle and Signal Flow...................................................................................................5-78 5.11.4 Front Panel.........................................................................................................................................5-79 5.11.5 Valid Slots..........................................................................................................................................5-81 5.11.6 Board Feature Code............................................................................................................................5-81 5.11.7 Board Configuration Reference.........................................................................................................5-81 5.11.8 Technical Specifications....................................................................................................................5-81 5.12 SLQ4...........................................................................................................................................................5-83 5.12.1 Version Description............................................................................................................................5-83 5.12.2 Function and Feature..........................................................................................................................5-84 5.12.3 Working Principle and Signal Flow...................................................................................................5-85 5.12.4 Front Panel.........................................................................................................................................5-87 5.12.5 Valid Slots..........................................................................................................................................5-88 5.12.6 Board Feature Code............................................................................................................................5-88 5.12.7 Board Configuration Reference.........................................................................................................5-89 5.12.8 Technical Specifications....................................................................................................................5-89 5.13 SLQ4A........................................................................................................................................................5-90 5.13.1 Version Description............................................................................................................................5-90 5.13.2 Function and Feature..........................................................................................................................5-91 5.13.3 Working Principle and Signal Flow...................................................................................................5-92 5.13.4 Front Panel.........................................................................................................................................5-93 5.13.5 Valid Slots..........................................................................................................................................5-94 5.13.6 Board Feature Code............................................................................................................................5-94 5.13.7 Board Configuration Reference.........................................................................................................5-94 5.13.8 Technical Specifications....................................................................................................................5-95 5.14 SL16............................................................................................................................................................5-96 5.14.1 Version Description............................................................................................................................5-96 5.14.2 Function and Feature..........................................................................................................................5-97 5.14.3 Working Principle and Signal Flow...................................................................................................5-98 5.14.4 Front Panel.......................................................................................................................................5-100 5.14.5 Valid Slots........................................................................................................................................5-102 5.14.6 Board Feature Code..........................................................................................................................5-102 5.14.7 Board Configuration Reference.......................................................................................................5-102 5.14.8 Technical Specifications..................................................................................................................5-102 5.15 SL16A.......................................................................................................................................................5-104 5.15.1 Version Description..........................................................................................................................5-105 5.15.2 Function and Feature........................................................................................................................5-105 iv Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
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5.15.3 Working Principle and Signal Flow.................................................................................................5-106 5.15.4 Front Panel.......................................................................................................................................5-109 5.15.5 Valid Slots........................................................................................................................................5-110 5.15.6 Board Feature Code..........................................................................................................................5-110 5.15.7 Board Configuration Reference.......................................................................................................5-111 5.15.8 Technical Specifications..................................................................................................................5-111 5.16 SF16..........................................................................................................................................................5-112 5.16.1 Version Description..........................................................................................................................5-113 5.16.2 Function and Feature........................................................................................................................5-113 5.16.3 Working Principle and Signal Flow.................................................................................................5-114 5.16.4 Front Panel.......................................................................................................................................5-116 5.16.5 Valid Slots........................................................................................................................................5-118 5.16.6 Board Configuration Reference.......................................................................................................5-118 5.16.7 Technical Specifications..................................................................................................................5-118
Contents
OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description 6.3.8 Board Configuration Reference...........................................................................................................6-26 6.3.9 Technical Specifications......................................................................................................................6-26
6.4 PQM .............................................................................................................................................................6-27 6.4.1 Version Description..............................................................................................................................6-27 6.4.2 Function and Feature............................................................................................................................6-27 6.4.3 Working Principle and Signal Flow.....................................................................................................6-28 6.4.4 Front Panel...........................................................................................................................................6-31 6.4.5 Valid Slots............................................................................................................................................6-32 6.4.6 TPS Protection for the Board...............................................................................................................6-32 6.4.7 Board Configuration Reference...........................................................................................................6-34 6.4.8 Technical Specifications......................................................................................................................6-34 6.5 PL3................................................................................................................................................................6-35 6.5.1 Version Description..............................................................................................................................6-35 6.5.2 Function and Feature............................................................................................................................6-36 6.5.3 Working Principle and Signal Flow.....................................................................................................6-36 6.5.4 Front Panel...........................................................................................................................................6-39 6.5.5 Valid Slots............................................................................................................................................6-40 6.5.6 TPS Protection for the Board...............................................................................................................6-40 6.5.7 Board Configuration Reference...........................................................................................................6-42 6.5.8 Technical Specifications......................................................................................................................6-42 6.6 PL3A.............................................................................................................................................................6-43 6.6.1 Version Description..............................................................................................................................6-43 6.6.2 Function and Feature............................................................................................................................6-44 6.6.3 Working Principle and Signal Flow.....................................................................................................6-45 6.6.4 Front Panel...........................................................................................................................................6-47 6.6.5 Valid Slots............................................................................................................................................6-48 6.6.6 Board Configuration Reference...........................................................................................................6-49 6.6.7 Technical Specifications......................................................................................................................6-49 6.7 PD3................................................................................................................................................................6-50 6.7.1 Version Description..............................................................................................................................6-50 6.7.2 Function and Feature............................................................................................................................6-51 6.7.3 Working Principle and Signal Flow.....................................................................................................6-51 6.7.4 Front Panel...........................................................................................................................................6-54 6.7.5 Valid Slots............................................................................................................................................6-55 6.7.6 TPS Protection for the Board...............................................................................................................6-55 6.7.7 Board Configuration Reference...........................................................................................................6-57 6.7.8 Technical Specifications......................................................................................................................6-57 6.8 PQ3................................................................................................................................................................6-57 6.8.1 Version Description..............................................................................................................................6-58 6.8.2 Function and Feature............................................................................................................................6-58 6.8.3 Working Principle and Signal Flow.....................................................................................................6-59 6.8.4 Front Panel...........................................................................................................................................6-61 vi Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
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6.8.5 Valid Slots............................................................................................................................................6-62 6.8.6 TPS Protection for the Board...............................................................................................................6-63 6.8.7 Board Configuration Reference...........................................................................................................6-64 6.8.8 Technical Specifications......................................................................................................................6-65 6.9 DX1...............................................................................................................................................................6-65 6.9.1 Version Description..............................................................................................................................6-66 6.9.2 Function and Feature............................................................................................................................6-66 6.9.3 Working Principle and Signal Flow.....................................................................................................6-66 6.9.4 Front Panel...........................................................................................................................................6-68 6.9.5 Valid Slots............................................................................................................................................6-69 6.9.6 Board Feature Code..............................................................................................................................6-69 6.9.7 TPS Protection for the Board...............................................................................................................6-70 6.9.8 Board Configuration Reference...........................................................................................................6-71 6.9.9 Technical Specifications......................................................................................................................6-71 6.10 DXA............................................................................................................................................................6-72 6.10.1 Version Description............................................................................................................................6-72 6.10.2 Function and Feature..........................................................................................................................6-73 6.10.3 Working Principle and Signal Flow...................................................................................................6-73 6.10.4 Front Panel.........................................................................................................................................6-74 6.10.5 Valid Slots..........................................................................................................................................6-75 6.10.6 Board Configuration Reference.........................................................................................................6-76 6.10.7 Technical Specifications....................................................................................................................6-76 6.11 SPQ4............................................................................................................................................................6-76 6.11.1 Version Description............................................................................................................................6-77 6.11.2 Function and Feature..........................................................................................................................6-77 6.11.3 Working Principle and Signal Flow...................................................................................................6-78 6.11.4 Front Panel.........................................................................................................................................6-82 6.11.5 Valid Slots..........................................................................................................................................6-83 6.11.6 TPS Protection for the Board.............................................................................................................6-84 6.11.7 Board Configuration Reference.........................................................................................................6-85 6.11.8 Technical Specifications....................................................................................................................6-85
Contents
OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description 7.2.2 Function and Feature..............................................................................................................................7-9 7.2.3 Working Principle and Signal Flow.....................................................................................................7-11 7.2.4 Front Panel...........................................................................................................................................7-12 7.2.5 Valid Slots............................................................................................................................................7-14 7.2.6 Board Configuration Reference...........................................................................................................7-15 7.2.7 Technical Specifications......................................................................................................................7-15
7.3 EFT8A...........................................................................................................................................................7-16 7.3.1 Version Description..............................................................................................................................7-16 7.3.2 Function and Feature............................................................................................................................7-16 7.3.3 Working Principle and Signal Flow.....................................................................................................7-17 7.3.4 Front Panel...........................................................................................................................................7-19 7.3.5 Valid Slots............................................................................................................................................7-21 7.3.6 Board Configuration Reference...........................................................................................................7-22 7.3.7 Technical Specifications......................................................................................................................7-22 7.4 EGT2.............................................................................................................................................................7-22 7.4.1 Version Description..............................................................................................................................7-23 7.4.2 Function and Feature............................................................................................................................7-23 7.4.3 Working Principle and Signal Flow.....................................................................................................7-24 7.4.4 Front Panel...........................................................................................................................................7-26 7.4.5 Valid Slots............................................................................................................................................7-28 7.4.6 Board Feature Code..............................................................................................................................7-28 7.4.7 Board Configuration Reference...........................................................................................................7-28 7.4.8 Technical Specifications......................................................................................................................7-28 7.5 EFS0..............................................................................................................................................................7-30 7.5.1 Version Description..............................................................................................................................7-30 7.5.2 Function and Feature............................................................................................................................7-31 7.5.3 Working Principle and Signal Flow.....................................................................................................7-33 7.5.4 Front Panel...........................................................................................................................................7-36 7.5.5 Valid Slots............................................................................................................................................7-37 7.5.6 TPS Protection......................................................................................................................................7-37 7.5.7 Board Configuration Reference...........................................................................................................7-38 7.5.8 Technical Specifications......................................................................................................................7-38 7.6 EFS4..............................................................................................................................................................7-38 7.6.1 Version Description..............................................................................................................................7-39 7.6.2 Function and Feature............................................................................................................................7-39 7.6.3 Working Principle and Signal Flow.....................................................................................................7-41 7.6.4 Front Panel...........................................................................................................................................7-44 7.6.5 Valid Slots............................................................................................................................................7-46 7.6.6 Board Configuration Reference...........................................................................................................7-46 7.6.7 Technical Specifications......................................................................................................................7-46 7.7 EGS2.............................................................................................................................................................7-46 7.7.1 Version Description..............................................................................................................................7-47 viii Huawei Proprietary and Confidential Copyright Huawei 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7.7.2 Function and Feature............................................................................................................................7-47 7.7.3 Working Principle and Signal Flow.....................................................................................................7-50 7.7.4 Front Panel...........................................................................................................................................7-52 7.7.5 Valid Slots............................................................................................................................................7-54 7.7.6 Board Feature Code..............................................................................................................................7-54 7.7.7 Board Configuration Reference...........................................................................................................7-54 7.7.8 Technical Specifications......................................................................................................................7-54 7.8 EMS4.............................................................................................................................................................7-55 7.8.1 Version Description..............................................................................................................................7-56 7.8.2 Function and Feature............................................................................................................................7-56 7.8.3 Working Principle and Signal Flow.....................................................................................................7-59 7.8.4 Front Panel...........................................................................................................................................7-61 7.8.5 Valid Slots............................................................................................................................................7-63 7.8.6 Board Feature Code..............................................................................................................................7-64 7.8.7 Board Protection...................................................................................................................................7-64 7.8.8 Board Configuration Reference...........................................................................................................7-67 7.8.9 Technical Specifications......................................................................................................................7-68 7.9 EGS4.............................................................................................................................................................7-69 7.9.1 Version Description..............................................................................................................................7-69 7.9.2 Function and Feature............................................................................................................................7-70 7.9.3 Working Principle and Signal Flow.....................................................................................................7-72 7.9.4 Front Panel...........................................................................................................................................7-75 7.9.5 Valid Slots............................................................................................................................................7-77 7.9.6 Board Feature Code..............................................................................................................................7-77 7.9.7 Board Protection...................................................................................................................................7-77 7.9.8 Board Configuration Reference...........................................................................................................7-80 7.9.9 Technical Specifications......................................................................................................................7-81 7.10 EGS4A........................................................................................................................................................7-82 7.10.1 Version Description............................................................................................................................7-82 7.10.2 Function and Feature..........................................................................................................................7-82 7.10.3 Working Principle and Signal Flow...................................................................................................7-84 7.10.4 Front Panel.........................................................................................................................................7-87 7.10.5 Valid Slots..........................................................................................................................................7-89 7.10.6 Board Feature Code............................................................................................................................7-89 7.10.7 Board Protection.................................................................................................................................7-89 7.10.8 Board Configuration Reference.........................................................................................................7-91 7.10.9 Technical Specifications....................................................................................................................7-92 7.11 EGR2...........................................................................................................................................................7-93 7.11.1 Version Description............................................................................................................................7-93 7.11.2 Function and Feature..........................................................................................................................7-93 7.11.3 Working Principle and Signal Flow...................................................................................................7-96 7.11.4 Front Panel.........................................................................................................................................7-98 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright Huawei 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OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description 7.11.5 Valid Slots........................................................................................................................................7-100 7.11.6 Board Feature Code..........................................................................................................................7-100 7.11.7 Board Configuration Reference.......................................................................................................7-100 7.11.8 Technical Specifications..................................................................................................................7-100
7.12 EMR0........................................................................................................................................................7-101 7.12.1 Version Description..........................................................................................................................7-102 7.12.2 Function and Feature........................................................................................................................7-103 7.12.3 Working Principle and Signal Flow.................................................................................................7-106 7.12.4 Front Panel.......................................................................................................................................7-108 7.12.5 Valid Slots........................................................................................................................................7-111 7.12.6 Board Feature Code..........................................................................................................................7-112 7.12.7 Board Configuration Reference.......................................................................................................7-112 7.12.8 Technical Specifications..................................................................................................................7-112 7.13 ADL4.........................................................................................................................................................7-113 7.13.1 Version Description..........................................................................................................................7-114 7.13.2 Function and Feature........................................................................................................................7-114 7.13.3 Working Principle and Signal Flow.................................................................................................7-115 7.13.4 Front Panel.......................................................................................................................................7-117 7.13.5 Valid Slots........................................................................................................................................7-119 7.13.6 Board Feature Code..........................................................................................................................7-119 7.13.7 Board Configuration Reference.......................................................................................................7-119 7.13.8 Technical Specifications..................................................................................................................7-120 7.14 ADQ1........................................................................................................................................................7-121 7.14.1 Version Description..........................................................................................................................7-121 7.14.2 Function and Feature........................................................................................................................7-121 7.14.3 Working Principle and Signal Flow.................................................................................................7-122 7.14.4 Front Panel.......................................................................................................................................7-124 7.14.5 Valid Slots........................................................................................................................................7-126 7.14.6 Board Feature Code..........................................................................................................................7-126 7.14.7 Board Configuration Reference.......................................................................................................7-126 7.14.8 Technical Specifications..................................................................................................................7-127 7.15 IDL4..........................................................................................................................................................7-128 7.15.1 Version Description..........................................................................................................................7-128 7.15.2 Function and Feature........................................................................................................................7-128 7.15.3 Working Principle ...........................................................................................................................7-130 7.15.4 Front Panel.......................................................................................................................................7-132 7.15.5 Valid Slots........................................................................................................................................7-134 7.15.6 Board Feature Code..........................................................................................................................7-134 7.15.7 Board Protection...............................................................................................................................7-134 7.15.8 Board Configuration Reference.......................................................................................................7-134 7.15.9 Technical Specifications..................................................................................................................7-135 7.16 IDQ1..........................................................................................................................................................7-136 x Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
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7.16.1 Version Description..........................................................................................................................7-136 7.16.2 Function and Feature........................................................................................................................7-136 7.16.3 Working Principle and Signal Flow.................................................................................................7-138 7.16.4 Front Panel.......................................................................................................................................7-140 7.16.5 Valid Slots........................................................................................................................................7-142 7.16.6 Board Feature Code..........................................................................................................................7-142 7.16.7 Board Protection...............................................................................................................................7-142 7.16.8 Board Configuration Reference.......................................................................................................7-142 7.16.9 Technical Specifications..................................................................................................................7-143 7.17 MST4.........................................................................................................................................................7-144 7.17.1 Version Description..........................................................................................................................7-144 7.17.2 Function and Feature........................................................................................................................7-144 7.17.3 Working Principle and Signal Flow.................................................................................................7-146 7.17.4 Front Panel.......................................................................................................................................7-148 7.17.5 Valid Slots........................................................................................................................................7-149 7.17.6 Board Feature Code..........................................................................................................................7-149 7.17.7 Board Configuration Reference.......................................................................................................7-150 7.17.8 Technical Specifications..................................................................................................................7-150
Contents
OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description 8.4.2 Function and Feature............................................................................................................................8-13 8.4.3 Working Principle and Signal Flow.....................................................................................................8-14 8.4.4 Front Panel...........................................................................................................................................8-14 8.4.5 Valid Slots............................................................................................................................................8-15 8.4.6 Technical Specifications......................................................................................................................8-15
8.5 D75S..............................................................................................................................................................8-16 8.5.1 Version Description..............................................................................................................................8-16 8.5.2 Function and Feature............................................................................................................................8-16 8.5.3 Working Principle and Signal Flow.....................................................................................................8-16 8.5.4 Front Panel...........................................................................................................................................8-17 8.5.5 Valid Slots............................................................................................................................................8-19 8.5.6 Technical Specifications......................................................................................................................8-20 8.6 D34S..............................................................................................................................................................8-20 8.6.1 Version Description..............................................................................................................................8-20 8.6.2 Function and Feature............................................................................................................................8-20 8.6.3 Working Principle and Signal Flow.....................................................................................................8-20 8.6.4 Front Panel...........................................................................................................................................8-21 8.6.5 Valid Slots............................................................................................................................................8-22 8.6.6 Technical Specifications......................................................................................................................8-22 8.7 C34S..............................................................................................................................................................8-23 8.7.1 Version Description..............................................................................................................................8-24 8.7.2 Function and Feature............................................................................................................................8-24 8.7.3 Working Principle and Signal Flow.....................................................................................................8-24 8.7.4 Front Panel...........................................................................................................................................8-25 8.7.5 Valid Slots............................................................................................................................................8-26 8.7.6 Technical Specifications......................................................................................................................8-26 8.8 EU04..............................................................................................................................................................8-27 8.8.1 Version Description..............................................................................................................................8-27 8.8.2 Function and Feature............................................................................................................................8-27 8.8.3 Working Principle and Signal Flow.....................................................................................................8-27 8.8.4 Front Panel...........................................................................................................................................8-28 8.8.5 Valid Slots............................................................................................................................................8-29 8.8.6 Technical Specifications......................................................................................................................8-30 8.9 EU08..............................................................................................................................................................8-30 8.9.1 Version Description..............................................................................................................................8-31 8.9.2 Function and Feature............................................................................................................................8-31 8.9.3 Working Principle and Signal Flow.....................................................................................................8-31 8.9.4 Front Panel...........................................................................................................................................8-32 8.9.5 Valid Slots............................................................................................................................................8-33 8.9.6 Technical Specifications......................................................................................................................8-33 8.10 OU08 ..........................................................................................................................................................8-34 8.10.1 Version Description............................................................................................................................8-34 xii Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
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8.10.2 Function and Feature..........................................................................................................................8-35 8.10.3 Working Principle and Signal Flow...................................................................................................8-35 8.10.4 Front Panel.........................................................................................................................................8-36 8.10.5 Valid Slots..........................................................................................................................................8-38 8.10.6 Technical Specifications....................................................................................................................8-38 8.11 MU04..........................................................................................................................................................8-39 8.11.1 Version Description............................................................................................................................8-39 8.11.2 Function and Feature..........................................................................................................................8-39 8.11.3 Working Principle and Signal Flow...................................................................................................8-40 8.11.4 Front Panel.........................................................................................................................................8-40 8.11.5 Valid Slots..........................................................................................................................................8-41 8.11.6 Technical Specifications....................................................................................................................8-42 8.12 TSB4............................................................................................................................................................8-42 8.12.1 Version Description............................................................................................................................8-43 8.12.2 Function and Feature..........................................................................................................................8-43 8.12.3 Working Principle and Signal Flow...................................................................................................8-43 8.12.4 Front Panel.........................................................................................................................................8-44 8.12.5 Valid Slots..........................................................................................................................................8-45 8.12.6 Technical Specifications....................................................................................................................8-45 8.13 TSB8............................................................................................................................................................8-46 8.13.1 Version Description............................................................................................................................8-46 8.13.2 Function and Feature..........................................................................................................................8-46 8.13.3 Working Principle and Signal Flow...................................................................................................8-46 8.13.4 Front Panel.........................................................................................................................................8-47 8.13.5 Valid Slots..........................................................................................................................................8-48 8.13.6 Technical Specifications....................................................................................................................8-50 8.14 EFF8............................................................................................................................................................8-50 8.14.1 Version Description............................................................................................................................8-51 8.14.2 Function and Feature..........................................................................................................................8-51 8.14.3 Working Principle and Signal Flow...................................................................................................8-51 8.14.4 Front Panel.........................................................................................................................................8-52 8.14.5 Valid Slots..........................................................................................................................................8-53 8.14.6 Technical Specifications....................................................................................................................8-54 8.15 ETF8............................................................................................................................................................8-55 8.15.1 Version Description............................................................................................................................8-55 8.15.2 Function and Feature..........................................................................................................................8-55 8.15.3 Working Principle and Signal Flow...................................................................................................8-56 8.15.4 Front Panel.........................................................................................................................................8-56 8.15.5 Valid Slots..........................................................................................................................................8-58 8.15.6 Technical Specifications....................................................................................................................8-59 8.16 ETS8............................................................................................................................................................8-60 8.16.1 Version Description............................................................................................................................8-60 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., 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OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description 8.16.2 Function and Feature..........................................................................................................................8-60 8.16.3 Working Principle and Signal Flow...................................................................................................8-60 8.16.4 Front Panel......................................................................................................................................... 8-61 8.16.5 Valid Slots..........................................................................................................................................8-63 8.16.6 Technical Specifications.................................................................................................................... 8-63
8.17 DM12.......................................................................................................................................................... 8-64 8.17.1 Version Description............................................................................................................................8-64 8.17.2 Function and Feature..........................................................................................................................8-64 8.17.3 Working Principle and Signal Flow...................................................................................................8-65 8.17.4 Front Panel......................................................................................................................................... 8-65 8.17.5 Valid Slots..........................................................................................................................................8-68 8.17.6 Technical Specifications.................................................................................................................... 8-68
Contents
9.3.9 Technical Specifications......................................................................................................................9-55 9.4 CXLL1..........................................................................................................................................................9-56 9.4.1 Version Description..............................................................................................................................9-57 9.4.2 Function and Feature............................................................................................................................9-57 9.4.3 Working Principle and Signal Flow.....................................................................................................9-60 9.4.4 Jumper and DIP Switch........................................................................................................................9-65 9.4.5 Front Panel...........................................................................................................................................9-66 9.4.6 Valid Slots............................................................................................................................................9-68 9.4.7 Board Feature Code..............................................................................................................................9-68 9.4.8 Board Configuration Reference...........................................................................................................9-69 9.4.9 Technical Specifications......................................................................................................................9-69 9.5 CXLL4..........................................................................................................................................................9-71 9.5.1 Version Description..............................................................................................................................9-71 9.5.2 Function and Feature............................................................................................................................9-71 9.5.3 Working Principle and Signal Flow.....................................................................................................9-74 9.5.4 Jumper and DIP Switch........................................................................................................................9-79 9.5.5 Front Panel...........................................................................................................................................9-80 9.5.6 Valid Slots............................................................................................................................................9-82 9.5.7 Board Feature Code..............................................................................................................................9-82 9.5.8 Board Configuration Reference...........................................................................................................9-83 9.5.9 Technical Specifications......................................................................................................................9-83 9.6 CXLL16........................................................................................................................................................9-85 9.6.1 Version Description..............................................................................................................................9-85 9.6.2 Function and Feature............................................................................................................................9-85 9.6.3 Working Principle and Signal Flow.....................................................................................................9-88 9.6.4 Jumper and DIP Switch........................................................................................................................9-93 9.6.5 Front Panel...........................................................................................................................................9-94 9.6.6 Valid Slots............................................................................................................................................9-96 9.6.7 Board Feature Code..............................................................................................................................9-96 9.6.8 Board Configuration Reference...........................................................................................................9-97 9.6.9 Technical Specifications......................................................................................................................9-97 9.7 CXLD1..........................................................................................................................................................9-99 9.7.1 Version Description..............................................................................................................................9-99 9.7.2 Function and Feature............................................................................................................................9-99 9.7.3 Working Principle and Signal Flow...................................................................................................9-102 9.7.4 Jumper and DIP Switch......................................................................................................................9-107 9.7.5 Front Panel.........................................................................................................................................9-108 9.7.6 Valid Slots..........................................................................................................................................9-110 9.7.7 Board Feature Code............................................................................................................................9-110 9.7.8 Board Configuration Reference.........................................................................................................9-111 9.7.9 Technical Specifications....................................................................................................................9-111 9.8 CXLD4........................................................................................................................................................9-113 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright 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OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description 9.8.1 Version Description............................................................................................................................9-113 9.8.2 Function and Feature..........................................................................................................................9-113 9.8.3 Working Principle and Signal Flow...................................................................................................9-116 9.8.4 Jumper and DIP Switch......................................................................................................................9-121 9.8.5 Front Panel.........................................................................................................................................9-122 9.8.6 Valid Slots..........................................................................................................................................9-124 9.8.7 Board Feature Code............................................................................................................................9-124 9.8.8 Board Configuration Reference.........................................................................................................9-125 9.8.9 Technical Specifications....................................................................................................................9-125
9.9 CXLQ1........................................................................................................................................................9-127 9.9.1 Version Description............................................................................................................................9-127 9.9.2 Function and Feature..........................................................................................................................9-127 9.9.3 Working Principle and Signal Flow...................................................................................................9-130 9.9.4 Jumper and DIP Switch......................................................................................................................9-135 9.9.5 Front Panel.........................................................................................................................................9-136 9.9.6 Valid Slots..........................................................................................................................................9-138 9.9.7 Board Feature Code............................................................................................................................9-138 9.9.8 Board Configuration Reference.........................................................................................................9-139 9.9.9 Technical Specifications....................................................................................................................9-139 9.10 CXLQ4......................................................................................................................................................9-141 9.10.1 Version Description..........................................................................................................................9-141 9.10.2 Function and Feature........................................................................................................................9-141 9.10.3 Working Principle and Signal Flow.................................................................................................9-144 9.10.4 Jumper and DIP Switch....................................................................................................................9-149 9.10.5 Front Panel.......................................................................................................................................9-150 9.10.6 Valid Slots........................................................................................................................................9-152 9.10.7 Board Feature Code..........................................................................................................................9-152 9.10.8 Board Configuration Reference.......................................................................................................9-153 9.10.9 Technical Specifications..................................................................................................................9-153
10 Auxiliary Boards.....................................................................................................................10-1
10.1 EOW............................................................................................................................................................10-2 10.1.1 Version Description............................................................................................................................10-2 10.1.2 Function and Feature..........................................................................................................................10-2 10.1.3 Working Principle and Signal Flow...................................................................................................10-3 10.1.4 Front Panel......................................................................................................................................... 10-4 10.1.5 Valid Slots..........................................................................................................................................10-6 10.1.6 Technical Specifications.................................................................................................................... 10-6 10.2 AUX............................................................................................................................................................10-6 10.2.1 Version Description............................................................................................................................10-6 10.2.2 Function and Feature..........................................................................................................................10-7 10.2.3 Working Principle and Signal Flow...................................................................................................10-7 10.2.4 Front Panel.......................................................................................................................................10-11 xvi Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
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10.2.5 Valid Slots........................................................................................................................................10-14 10.2.6 Technical Specifications..................................................................................................................10-14 10.3 AMU..........................................................................................................................................................10-14 10.3.1 Version Description..........................................................................................................................10-15 10.3.2 Function and Feature........................................................................................................................10-15 10.3.3 Working Principle and Signal Flow.................................................................................................10-15 10.3.4 Front Panel.......................................................................................................................................10-17 10.3.5 Valid Slots........................................................................................................................................10-20 10.3.6 Technical Specifications..................................................................................................................10-20 10.4 FAN...........................................................................................................................................................10-20 10.4.1 Version Description..........................................................................................................................10-20 10.4.2 Function and Feature........................................................................................................................10-20 10.4.3 Working Principle and Signal Flow.................................................................................................10-21 10.4.4 Front Panel.......................................................................................................................................10-21 10.4.5 Valid Slots........................................................................................................................................10-22 10.4.6 Technical Specifications..................................................................................................................10-22
Contents
OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description 11.4.1 Version Description..........................................................................................................................11-21 11.4.2 Function and Feature........................................................................................................................11-21 11.4.3 Working Principle and Signal Flow.................................................................................................11-23 11.4.4 Front Panel.......................................................................................................................................11-24 11.4.5 Valid Slots........................................................................................................................................11-25 11.4.6 Technical Specifications..................................................................................................................11-25
11.5 MR2B........................................................................................................................................................11-26 11.5.1 Version Description..........................................................................................................................11-27 11.5.2 Function and Feature........................................................................................................................11-27 11.5.3 Working Principle and Signal Flow.................................................................................................11-28 11.5.4 Front Panel.......................................................................................................................................11-29 11.5.5 Valid Slots........................................................................................................................................11-30 11.5.6 Technical Specifications..................................................................................................................11-30 11.6 MR2C........................................................................................................................................................11-31 11.6.1 Version Description..........................................................................................................................11-32 11.6.2 Function and Feature........................................................................................................................11-32 11.6.3 Working Principle and Signal Flow.................................................................................................11-33 11.6.4 Front Panel.......................................................................................................................................11-34 11.6.5 Valid Slots........................................................................................................................................11-36 11.6.6 Technical Specifications..................................................................................................................11-36 11.7 MR4...........................................................................................................................................................11-37 11.7.1 Version Description..........................................................................................................................11-37 11.7.2 Function and Feature........................................................................................................................11-37 11.7.3 Working Principle and Signal Flow.................................................................................................11-38 11.7.4 Front Panel.......................................................................................................................................11-39 11.7.5 Valid Slots........................................................................................................................................11-40 11.7.6 Board Feature Code..........................................................................................................................11-40 11.7.7 Technical Specifications..................................................................................................................11-41 11.8 LWX..........................................................................................................................................................11-42 11.8.1 Version Description..........................................................................................................................11-43 11.8.2 Function and Feature........................................................................................................................11-43 11.8.3 Working Principle and Signal Flow.................................................................................................11-44 11.8.4 Front Panel.......................................................................................................................................11-46 11.8.5 Valid Slots........................................................................................................................................11-48 11.8.6 Board Feature Code..........................................................................................................................11-48 11.8.7 Technical Specifications..................................................................................................................11-48 11.9 OBU1........................................................................................................................................................11-51 11.9.1 Version Description..........................................................................................................................11-52 11.9.2 Function and Feature........................................................................................................................11-52 11.9.3 Working Principle and Signal Flow.................................................................................................11-53 11.9.4 Front Panel.......................................................................................................................................11-54 11.9.5 Valid Slots........................................................................................................................................11-56 xviii Huawei Proprietary and Confidential Copyright Huawei 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11.9.6 Board Feature Code..........................................................................................................................11-56 11.9.7 Technical Specifications..................................................................................................................11-56 11.10 FIB...........................................................................................................................................................11-58 11.10.1 Version Description........................................................................................................................11-58 11.10.2 Function and Feature......................................................................................................................11-58 11.10.3 Working Principle and Signal Flow...............................................................................................11-59 11.10.4 Front Panel.....................................................................................................................................11-59 11.10.5 Valid Slots......................................................................................................................................11-60 11.10.6 Technical Specifications................................................................................................................11-61
Contents
13.2 PIU..............................................................................................................................................................13-7 13.2.1 Version Description............................................................................................................................13-8 13.2.2 Function and Feature..........................................................................................................................13-8 13.2.3 Working Principle and Signal Flow...................................................................................................13-8 13.2.4 Front Panel.........................................................................................................................................13-9 13.2.5 Valid Slots........................................................................................................................................13-10 13.2.6 Technical Specifications..................................................................................................................13-10 13.3 PIUA..........................................................................................................................................................13-11 13.3.1 Version Description..........................................................................................................................13-11 13.3.2 Function and Feature........................................................................................................................13-12 13.3.3 Working Principle and Signal Flow.................................................................................................13-12 13.3.4 Front Panel.......................................................................................................................................13-13 13.3.5 Valid Slots........................................................................................................................................13-14 13.3.6 Technical Specifications..................................................................................................................13-14
14 Cables.......................................................................................................................................14-1
14.1 Fiber Jumper................................................................................................................................................14-2 14.1.1 Types of Fiber Jumpers......................................................................................................................14-2 14.1.2 Connector...........................................................................................................................................14-3 14.2 Power Cables and Grounding Cables..........................................................................................................14-5 14.2.1 Cabinet 48 V/BGND/PGND Power Cable.......................................................................................14-5 14.2.2 Equipment 48 V/60 V Power Cable/PGND Grounding Cable......................................................14-7 14.2.3 UPM Power Cable..............................................................................................................................14-9 14.3 Alarm Cable..............................................................................................................................................14-10 14.3.1 Alarm Input/Output Cable................................................................................................................14-10 14.4 Management Cable....................................................................................................................................14-12 14.4.1 OAM Serial Port Cable....................................................................................................................14-13 14.4.2 Serial 14/F1/F&f Serial Port Cable................................................................................................14-14 14.4.3 RS232/RS422 Serial Port Cable.......................................................................................................14-15 14.4.4 Ordinary Telephone Wire.................................................................................................................14-17 14.4.5 COA Concatenating Cable...............................................................................................................14-18 14.4.6 Straight Through Cable....................................................................................................................14-19 14.4.7 Crossover Cable...............................................................................................................................14-20 14.5 Signal Cable..............................................................................................................................................14-21 14.5.1 75-ohm 8 x E1 Cable........................................................................................................................14-22 14.5.2 75-ohm 16 x E1 Cable......................................................................................................................14-24 14.5.3 120-ohm 8 x E1 Cable......................................................................................................................14-26 14.5.4 120-ohm 16 x E1 Cable....................................................................................................................14-28 14.5.5 E3/T3/STM-1 Cable.........................................................................................................................14-31 14.5.6 Framed E1 Cable..............................................................................................................................14-32 14.5.7 N x 64 kbit/s Cables.........................................................................................................................14-32 14.6 Clock Cable...............................................................................................................................................14-49 14.6.1 Clock Cable......................................................................................................................................14-49 xx Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
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B Labels..........................................................................................................................................B-1
B.1 Safety Label...................................................................................................................................................B-2 B.1.1 Label Description..................................................................................................................................B-2 B.1.2 Label Position.......................................................................................................................................B-3 B.2 Optical Module Labels...................................................................................................................................B-5 B.3 Engineering Labels........................................................................................................................................B-7
C Power Consumption and Weight of Boards........................................................................C-1 D Board Version Configuration................................................................................................D-1 E Board Loopbacks.......................................................................................................................E-1 F Board Configuration Reference..............................................................................................F-1
F.1 SDH Processing Boards..................................................................................................................................F-2 F.2 PDH Processing Board...................................................................................................................................F-2 F.3 Data Processing Board....................................................................................................................................F-4 F.3.1 SDH Parameters.....................................................................................................................................F-5 F.3.2 Ethernet Parameters...............................................................................................................................F-6 F.3.3 ATM Parameter.....................................................................................................................................F-7 F.4 Cross-Connect and Timing Unit.....................................................................................................................F-8
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Figures
Figures
Figure 1-1 Appearance of the OptiX OSN 1500A...............................................................................................1-1 Figure 1-2 Appearance of the OptiX OSN 1500B...............................................................................................1-1 Figure 2-1 ETSI cabinet.......................................................................................................................................2-2 Figure 2-2 Appearance of the DC PDU...............................................................................................................2-4 Figure 3-1 Structure of the OptiX OSN 1500A subrack......................................................................................3-2 Figure 3-2 Structure of the OptiX OSN 1500B subrack......................................................................................3-3 Figure 3-3 Slot access capacity of the OptiX OSN 1500A..................................................................................3-4 Figure 3-4 Slot access capacity of the OptiX OSN 1500B..................................................................................3-4 Figure 3-5 Slot layout of the OptiX OSN 1500A subrack...................................................................................3-5 Figure 3-6 Slot layout of the OptiX OSN 1500A subrack after the division of slots..........................................3-5 Figure 3-7 Slot layout of the OptiX OSN 1500B subrack.................................................................................3-13 Figure 3-8 Slot layout of the OptiX OSN 1500B subrack (after the division of slots)......................................3-13 Figure 4-1 Barcode of a board..............................................................................................................................4-3 Figure 5-1 Block diagram for the working principle of the SL1..........................................................................5-5 Figure 5-2 Front panel of the N1SL1/N2SL1......................................................................................................5-7 Figure 5-3 Front panel of the R1SL1...................................................................................................................5-8 Figure 5-4 Block diagram for the working principle of the SL1A.....................................................................5-13 Figure 5-5 Front panel of the SL1A...................................................................................................................5-14 Figure 5-6 Block diagram for the working principle of the SLQ1.....................................................................5-19 Figure 5-7 Front panel of the N1SLQ1/N2SLQ1...............................................................................................5-21 Figure 5-8 Front panel of the R1SLQ1..............................................................................................................5-22 Figure 5-9 Block diagram for the working principle of the SLQ1A board........................................................5-27 Figure 5-10 Front panel of the SLQ1A board....................................................................................................5-29 Figure 5-11 Block diagram for the working principle of the SLO1...................................................................5-34 Figure 5-12 Front panel of the SLO1.................................................................................................................5-36 Figure 5-13 Block diagram for the working principle of the SLT1...................................................................5-41 Figure 5-14 Front panel of the SLT1..................................................................................................................5-43 Figure 5-15 Block diagram for the working principle of the SEP1...................................................................5-48 Figure 5-16 Block diagram for the working principle of the SEP used with the EU08.....................................5-48 Figure 5-17 Block diagram for the working principle of the SEP used with the OU08....................................5-49 Figure 5-18 Front panel of the SEP1..................................................................................................................5-51 Figure 5-19 Principle of the TPS protection for the SEP1 ................................................................................5-52 Figure 5-20 Slot configuration for the 1:1 TPS protection for the SEP1...........................................................5-53 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd xxiii
Figures
Figure 5-21 Block diagram for the working principle of the SL4......................................................................5-57 Figure 5-22 Front panel of the N1SL4/N2SL4..................................................................................................5-59 Figure 5-23 Front panel of the R1SL4...............................................................................................................5-59 Figure 5-24 Block diagram for the working principle of the SL4A...................................................................5-64 Figure 5-25 Front panel of the SL4A board.......................................................................................................5-66 Figure 5-26 Block diagram for the working principle of the SLD4...................................................................5-71 Figure 5-27 Front panel of the N1SLD4/N2SLD4.............................................................................................5-73 Figure 5-28 Front panel of the R1SLD4............................................................................................................5-74 Figure 5-29 Block diagram for the working principle of the SL4A board.........................................................5-79 Figure 5-30 Front panel of the SLD4A board....................................................................................................5-80 Figure 5-31 Block diagram for the working principle of the SLQ4...................................................................5-85 Figure 5-32 Front panel of the SLQ4.................................................................................................................5-87 Figure 5-33 Block diagram for the working principle of the SLQ4A................................................................5-92 Figure 5-34 Front panel of the SLQ4A board....................................................................................................5-93 Figure 5-35 Block diagram for the working principle of the SL16....................................................................5-99 Figure 5-36 Front panel of the SL16................................................................................................................5-101 Figure 5-37 Block diagram for the working principle of the N1SL16A and N2SL16A..................................5-107 Figure 5-38 Block diagram for the working principle of the N3SL16A..........................................................5-107 Figure 5-39 Front panel of the SL16A.............................................................................................................5-109 Figure 5-40 Block diagram for the working principle of the SF16..................................................................5-114 Figure 5-41 Front panel of the SF16................................................................................................................5-117 Figure 6-1 Block diagram for the functions of the PL1.......................................................................................6-4 Figure 6-2 Block diagram of the E1 mapping/demapping...................................................................................6-5 Figure 6-3 Front panel of the PL1........................................................................................................................6-6 Figure 6-4 Block diagram for the functions of the PD1.....................................................................................6-11 Figure 6-5 Block diagram of the E1 mapping/ demapping ...............................................................................6-11 Figure 6-6 Front panel of the PD1......................................................................................................................6-13 Figure 6-7 Principle of the TPS protection for the PD1 in the OptiX OSN 1500A subrack..............................6-15 Figure 6-8 Principle of the TPS protection for the PD1 in the OptiX OSN 1500B subrack..............................6-16 Figure 6-9 Slot configuration for the 1:1 TPS protection for the PD1 in the OptiX OSN 1500A subrack........6-16 Figure 6-10 Block diagram for the functions of the PQ1...................................................................................6-20 Figure 6-11 Block diagram of the E1/T1 mapping/ demapping ........................................................................6-21 Figure 6-12 Front panel of the PQ1....................................................................................................................6-23 Figure 6-13 Principle of the TPS protection for the PQ1 in the OptiX OSN 1500B subrack............................6-25 Figure 6-14 Slot configuration for 1:2 TPS protection of the PQ1....................................................................6-26 Figure 6-15 Block diagram for the functions of the PQM.................................................................................6-29 Figure 6-16 Block diagram of the E1/T1 mapping/ demapping ........................................................................6-29 Figure 6-17 Front panel of the PQM..................................................................................................................6-31 Figure 6-18 Principle of the TPS protection for the PQM in the OptiX OSN 1500B subrack..........................6-33 Figure 6-19 Slot configuration for the 1:2 TPS protection for the PQM in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-34 Figure 6-20 Block diagram for the functions of the PL3...................................................................................6-37 Figure 6-21 Block diagram of the E3/T3 mapping/demapping .........................................................................6-37 xxiv Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
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Figure 6-22 Front panel of the PL3....................................................................................................................6-39 Figure 6-23 Principle of the TPS protection for the PL3 in the OptiX OSN 1500B subrack............................6-41 Figure 6-24 Slot configuration for the 1:1 TPS protection for the PL3 in the OptiX OSN 1500B subrack......6-42 Figure 6-25 Block diagram for the functions of the PL3A................................................................................6-45 Figure 6-26 Block diagram of the E3/T3 mapping/demapping .........................................................................6-46 Figure 6-27 Front panel of the PL3A.................................................................................................................6-48 Figure 6-28 Block diagram for the functions of the PD3...................................................................................6-52 Figure 6-29 Block diagram of the E3/T3 mapping/demapping .........................................................................6-52 Figure 6-30 Front panel of the PD3....................................................................................................................6-54 Figure 6-31 Principle of the TPS protection for the PD3 in the OptiX OSN 1500B subrack............................6-55 Figure 6-32 Slot configuration for the 1:1 TPS protection for the PD3 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-56 Figure 6-33 Block diagram for the functions of the PQ3...................................................................................6-59 Figure 6-34 Block diagram of the E3/T3 mapping/demapping .........................................................................6-60 Figure 6-35 Front panel of the PQ3....................................................................................................................6-62 Figure 6-36 Principle of the TPS protection for the PQ3 in the OptiX OSN 1500B subrack............................6-63 Figure 6-37 Slot configuration for the 1:1 TPS protection for the PQ3 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-64 Figure 6-38 Block diagram for the functions of the DX1..................................................................................6-67 Figure 6-39 Front panel of the DX1...................................................................................................................6-68 Figure 6-40 Principle of the TPS protection for the DX1 in the OptiX OSN 1500B subrack...........................6-70 Figure 6-41 Slot configuration for the 1:2 TPS protection for the DX1 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-71 Figure 6-42 Block diagram for the functions of the DXA.................................................................................6-73 Figure 6-43 Front panel of the DXA..................................................................................................................6-75 Figure 6-44 Block diagram for the functions of the SPQ4.................................................................................6-79 Figure 6-45 Block diagram of the 140M mapping/demapping .........................................................................6-79 Figure 6-46 Block diagram of the SDH overhead processing module...............................................................6-80 Figure 6-47 Front panel of the SPQ4.................................................................................................................6-83 Figure 6-48 Principle of the TPS protection for the SPQ4 in the OptiX OSN 1500B subrack.........................6-84 Figure 6-49 Slot configuration for the 1:1 TPS protection for the SPQ4...........................................................6-85 Figure 7-1 Block diagram for the functions of the EFT4.....................................................................................7-5 Figure 7-2 Front panel of the EFT4......................................................................................................................7-7 Figure 7-3 Block diagram for the functions of the EFT8...................................................................................7-11 Figure 7-4 Front panel of the EFT8....................................................................................................................7-13 Figure 7-5 Block diagram for the functions of the EFT8A................................................................................7-18 Figure 7-6 Front panel of the EFT8A.................................................................................................................7-20 Figure 7-7 Block diagram for the functions of the EGT2..................................................................................7-25 Figure 7-8 Front panel of the EGT2...................................................................................................................7-27 Figure 7-9 Block diagram for the functions of the EFS0...................................................................................7-34 Figure 7-10 Front panel of the EFS0..................................................................................................................7-36 Figure 7-11 Slot configuration for the 1:1 TPS protection for the EFS0 in the OptiX OSN 1500B subrack .............................................................................................................................................................................7-38 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd xxv
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Figure 7-12 Block diagram for the functions of the EFS4.................................................................................7-42 Figure 7-13 Front panel of the EFS4..................................................................................................................7-44 Figure 7-14 Block diagram for the functions of the EGS2................................................................................7-50 Figure 7-15 Front panel of the EGS2.................................................................................................................7-53 Figure 7-16 Block diagram for the functions of the EMS4................................................................................7-59 Figure 7-17 Front panel of the EMS4................................................................................................................7-62 Figure 7-18 Normal working of the EMS4........................................................................................................7-65 Figure 7-19 Principle of the BPS protection for the EMS4...............................................................................7-66 Figure 7-20 Principle of the PPS protection for the EMS4................................................................................7-67 Figure 7-21 Block diagram for the functions of the EGS4................................................................................7-73 Figure 7-22 Front panel of the EGS4.................................................................................................................7-76 Figure 7-23 Normal working of the EGS4.........................................................................................................7-78 Figure 7-24 Principle of the BPS protection for the EGS4................................................................................7-79 Figure 7-25 Principle of the PPS protection for the EGS4.................................................................................7-80 Figure 7-26 Block diagram for the functions of the EGS4A..............................................................................7-85 Figure 7-27 Front panel of the EGS4A..............................................................................................................7-88 Figure 7-28 Normal working of the EGS4A......................................................................................................7-90 Figure 7-29 Principle of the BPS protection for the EGS4A.............................................................................7-91 Figure 7-30 Block diagram for the functions of the EGR2................................................................................7-96 Figure 7-31 Front panel of the EGR2.................................................................................................................7-99 Figure 7-32 Block diagram for the functions of the EMR0.............................................................................7-106 Figure 7-33 Front panel of the N1EMR0.........................................................................................................7-109 Figure 7-34 Front panel of the N2EMR0.........................................................................................................7-110 Figure 7-35 Block diagram for the functions of the ADL4..............................................................................7-116 Figure 7-36 Front panel of the ADL4.............................................................................................................. 7-118 Figure 7-37 Block diagram for the functions of the ADQ1............................................................................. 7-123 Figure 7-38 Front panel of the ADQ1..............................................................................................................7-125 Figure 7-39 Block diagram for the functions of the IDL4............................................................................... 7-131 Figure 7-40 Front panel of the IDL4................................................................................................................7-133 Figure 7-41 Block diagram for the functions of the IDQ1...............................................................................7-139 Figure 7-42 Front panel of the IDQ1................................................................................................................7-141 Figure 7-43 Block diagram for the functions of the MST4..............................................................................7-146 Figure 7-44 Front panel of the MST4.............................................................................................................. 7-148 Figure 8-1 Block diagram for the functions of the L12S.....................................................................................8-3 Figure 8-2 Front panel of the L12S......................................................................................................................8-4 Figure 8-3 Block diagram for the functions of the D12B....................................................................................8-6 Figure 8-4 Front panel of the D12B.....................................................................................................................8-7 Figure 8-5 Block diagram for the functions of the D12S...................................................................................8-10 Figure 8-6 Front panel of the D12S....................................................................................................................8-11 Figure 8-7 Block diagram for the functions of the L75S...................................................................................8-14 Figure 8-8 Front panel of the L75S....................................................................................................................8-15 Figure 8-9 Block diagram for the functions of the D75S...................................................................................8-17 xxvi Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
Figures
Figure 8-10 Front panel of the D75S..................................................................................................................8-18 Figure 8-11 Block diagram for the functions of the D34S.................................................................................8-21 Figure 8-12 Front panel of the D34S..................................................................................................................8-22 Figure 8-13 Block diagram for the functions of the C34S.................................................................................8-24 Figure 8-14 Front panel of the C34S..................................................................................................................8-25 Figure 8-15 Block diagram for the functions of the EU04.................................................................................8-28 Figure 8-16 Front panel of the EU04.................................................................................................................8-29 Figure 8-17 Block diagram for the functions of the EU08.................................................................................8-31 Figure 8-18 Front panel of the EU08.................................................................................................................8-32 Figure 8-19 Block diagram for the functions of the OU08................................................................................8-35 Figure 8-20 Front panel of the N1OU08............................................................................................................8-36 Figure 8-21 Front panel of the N2OU08............................................................................................................8-37 Figure 8-22 Block diagram for the functions of the MU04................................................................................8-40 Figure 8-23 Front panel of the MU04................................................................................................................8-41 Figure 8-24 Block diagram for the functions of the TSB4.................................................................................8-43 Figure 8-25 Front panel of the TSB4.................................................................................................................8-44 Figure 8-26 Block diagram for the functions of the TSB8.................................................................................8-47 Figure 8-27 Front panel of the TSB8.................................................................................................................8-48 Figure 8-28 Block diagram for the functions of the EFF8.................................................................................8-51 Figure 8-29 Front panel of the EFF8..................................................................................................................8-52 Figure 8-30 Block diagram for the functions of the ETF8.................................................................................8-56 Figure 8-31 Front panel of the ETF8..................................................................................................................8-57 Figure 8-32 Block diagram for the functions of the ETS8.................................................................................8-61 Figure 8-33 Front panel of the ETS8..................................................................................................................8-62 Figure 8-34 Block diagram for the functions of the DM12................................................................................8-65 Figure 8-35 Front panel of the DM12................................................................................................................8-66 Figure 9-1 Block diagram for the functions of the Q2CXL1...............................................................................9-7 Figure 9-2 Block diagram for the functions of the Q3CXL1 board.....................................................................9-8 Figure 9-3 Block diagram of higher and lower order cross-connect modules..................................................9-11 Figure 9-4 Jumper and DIP switch of the CXL1 board.....................................................................................9-13 Figure 9-5 Front panel of the Q2CXL1..............................................................................................................9-15 Figure 9-6 Front panel the Q3CXL1 board .......................................................................................................9-16 Figure 9-7 Block diagram for the functions of the Q2CXL4.............................................................................9-25 Figure 9-8 Block diagram for the functions of the Q3CXL4 board...................................................................9-26 Figure 9-9 Block diagram of higher and lower order cross-connect modules..................................................9-29 Figure 9-10 Jumper and DIP switch of the CXL4 board...................................................................................9-31 Figure 9-11 Front panel of the Q2CXL4............................................................................................................9-33 Figure 9-12 Front panel the Q3CXL4 board .....................................................................................................9-34 Figure 9-13 Block diagram for the functions of the Q2CXL16.........................................................................9-43 Figure 9-14 Block diagram for the functions of the Q3CXL16 board...............................................................9-44 Figure 9-15 Block diagram of higher and lower order cross-connect modules................................................9-47 Figure 9-16 Jumper and DIP switch of the CXL16 board.................................................................................9-49 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd xxvii
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Figure 9-17 Front panel of the Q2CXL16..........................................................................................................9-51 Figure 9-18 Front panel the Q3CXL16 board ...................................................................................................9-52 Figure 9-19 Block diagram for the functions of the CXLL1..............................................................................9-61 Figure 9-20 Block diagram of higher and lower order cross-connect modules................................................9-64 Figure 9-21 Jumper and DIP switch of the CXL board.....................................................................................9-65 Figure 9-22 Front panel the CXLL1 board .......................................................................................................9-67 Figure 9-23 Block diagram for the functions of the CXLL4..............................................................................9-75 Figure 9-24 Block diagram of higher and lower order cross-connect modules................................................9-78 Figure 9-25 Jumper and DIP switch of the CXL board.....................................................................................9-79 Figure 9-26 Front panel the CXLL4 board .......................................................................................................9-81 Figure 9-27 Block diagram for the functions of the CXLL16............................................................................9-89 Figure 9-28 Block diagram of higher and lower order cross-connect modules................................................9-92 Figure 9-29 Jumper and DIP switch of the CXL board.....................................................................................9-93 Figure 9-30 Front panel the CXLL16 board .....................................................................................................9-95 Figure 9-31 Block diagram for the functions of the CXLD1...........................................................................9-103 Figure 9-32 Block diagram of higher and lower order cross-connect modules..............................................9-106 Figure 9-33 Jumper and DIP switch of the CXL board...................................................................................9-107 Figure 9-34 Front panel the CXLD1 board .....................................................................................................9-109 Figure 9-35 Block diagram for the functions of the CXLD4...........................................................................9-117 Figure 9-36 Block diagram of higher and lower order cross-connect modules..............................................9-120 Figure 9-37 Jumper and DIP switch of the CXLD4 board...............................................................................9-121 Figure 9-38 Front panel the CXLD4 board .....................................................................................................9-123 Figure 9-39 Block diagram for the functions of the CXLQ1...........................................................................9-131 Figure 9-40 Block diagram of higher and lower order cross-connect modules..............................................9-134 Figure 9-41 Jumper and DIP switch of the CXLQ1 board...............................................................................9-135 Figure 9-42 Front panel the CXLQ1 board .....................................................................................................9-137 Figure 9-43 Block diagram for the functions of the CXLQ4...........................................................................9-145 Figure 9-44 Block diagram of higher and lower order cross-connect modules..............................................9-148 Figure 9-45 Jumper and DIP switch of the CXLQ4 board...............................................................................9-149 Figure 9-46 Front panel the CXLQ4 board .....................................................................................................9-151 Figure 10-1 Block diagram for the functions of the EOW.................................................................................10-3 Figure 10-2 Front panel of the EOW..................................................................................................................10-4 Figure 10-3 Block diagram for the functions of the R1AUX.............................................................................10-8 Figure 10-4 Block diagram for the functions of the R2AUX.............................................................................10-9 Figure 10-5 Front panel of the AUX................................................................................................................10-11 Figure 10-6 Block diagram for the functions of the AMU...............................................................................10-16 Figure 10-7 Positions of orderwire bytes in the SDH frame............................................................................10-16 Figure 10-8 Front panel of the AMU...............................................................................................................10-17 Figure 10-9 Connection of the cabinet alarm indicators..................................................................................10-19 Figure 10-10 Block diagram for the functions of the FAN..............................................................................10-21 Figure 10-11 Front panel of the FAN...............................................................................................................10-22 Figure 11-1 Block diagram for the functions of the CMR2...............................................................................11-4 xxviii Huawei Proprietary and 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Figure 11-2 Front panel of the CMR2................................................................................................................11-6 Figure 11-3 Block diagram for the functions of the CMR4.............................................................................11-10 Figure 11-4 Front panel of the CMR4..............................................................................................................11-12 Figure 11-5 Block diagram for the functions of the MR2................................................................................11-17 Figure 11-6 Front panel of the MR2................................................................................................................ 11-18 Figure 11-7 MR2A used as the OTM station...................................................................................................11-22 Figure 11-8 MR2A and LWX used as the two-channel wavelength adding/dropping OADM station...........11-22 Figure 11-9 Block diagram for the functions of the MR2A.............................................................................11-23 Figure 11-10 Front panel of the MR2A............................................................................................................11-24 Figure 11-11 MR2B used as the OTM station.................................................................................................11-27 Figure 11-12 MR2B and LWX used as the two-channel wavelength adding/dropping OADM station......... 11-28 Figure 11-13 Block diagram for the functions of the MR2B...........................................................................11-28 Figure 11-14 Front panel of the MR2B............................................................................................................11-29 Figure 11-15 MR2C used as the OTM station.................................................................................................11-32 Figure 11-16 Two-channel wavelength adding/dropping OADM station realized by the MR2C and LWX ...........................................................................................................................................................................11-33 Figure 11-17 Block diagram for the functions of the MR2C...........................................................................11-33 Figure 11-18 Front panel of the MR2C............................................................................................................11-35 Figure 11-19 Block diagram for the functions of the MR4..............................................................................11-38 Figure 11-20 Front panel of the MR4.............................................................................................................. 11-39 Figure 11-21 Block diagram for the functions of the LWX.............................................................................11-45 Figure 11-22 Front panel of the LWX..............................................................................................................11-47 Figure 11-23 Block diagram for the functions of the OBU1............................................................................11-53 Figure 11-24 Front panel of the OBU1............................................................................................................11-55 Figure 11-25 Location of the FIB in the optical transmission system............................................................. 11-58 Figure 11-26 Block diagram for the working principle of the FIB..................................................................11-59 Figure 11-27 Front panel of the FIB................................................................................................................ 11-60 Figure 12-1 Location of the BA in the optical transmission system..................................................................12-2 Figure 12-2 Block diagram for the functions of the BA2..................................................................................12-4 Figure 12-3 Front panel of the single-interface BA2.........................................................................................12-6 Figure 12-4 Front panel of the double-interface BA2........................................................................................12-7 Figure 12-5 Location of the BA and PA in the optical transmission system...................................................12-11 Figure 12-6 Block diagram for the working principle of the N1BPA..............................................................12-12 Figure 12-7 Block diagram for the working principle of the N2BPA..............................................................12-13 Figure 12-8 Front panel of the BPA.................................................................................................................12-14 Figure 12-9 Appearance of the case-shaped 61COA and N1COA (PA)......................................................... 12-18 Figure 12-10 Appearance of the case-shaped 62COA.....................................................................................12-19 Figure 12-11 Application of the optical Raman amplifier (62COA)...............................................................12-19 Figure 12-12 Block diagram for the functions of the 61COA and N1COA.................................................... 12-21 Figure 12-13 Front panel of the 61COA and N1COA.....................................................................................12-22 Figure 12-14 Front panel of the 62COA..........................................................................................................12-23 Figure 12-15 SC/PC fiber connector................................................................................................................12-24 Figure 12-16 LSH flange and fiber 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Figure 12-17 Position of the 61COA in the ETSI cabinet...............................................................................12-27 Figure 13-1 Appearance of the power supply case............................................................................................13-2 Figure 13-2 Rear view of the UPM....................................................................................................................13-4 Figure 13-3 Block diagram for the functions of the PIU....................................................................................13-9 Figure 13-4 Front panel of the PIU..................................................................................................................13-10 Figure 13-5 Block diagram for the functions of the PIUA...............................................................................13-12 Figure 13-6 Front panel of the PIUA...............................................................................................................13-13 Figure 14-1 LC/PC optical connector................................................................................................................14-3 Figure 14-2 SC/PC optical connector.................................................................................................................14-4 Figure 14-3 FC/PC optical connector.................................................................................................................14-4 Figure 14-4 LSH/APC optical connector...........................................................................................................14-5 Figure 14-5 Cabinet 48 V power cable and BGND power grounding cable....................................................14-6 Figure 14-6 Cabinet PGND protection grounding cable (JG2)..........................................................................14-6 Figure 14-7 Cabinet PGND protection grounding cable (OT)...........................................................................14-6 Figure 14-8 Structure of the equipment 48 V/60 V Power Cable..................................................................14-8 Figure 14-9 PGND power cable.........................................................................................................................14-8 Figure 14-10 Structure of the UPM power cable...............................................................................................14-9 Figure 14-11 Structure of the alarm input/output cable...................................................................................14-11 Figure 14-12 Structure of the OAM serial port cable.......................................................................................14-13 Figure 14-13 Structure of the Serial 14/F1/F&f serial port cable..................................................................14-14 Figure 14-14 Structure of the RS232/RS422 serial port cable.........................................................................14-16 Figure 14-15 Structure of the ordinary telephone wire....................................................................................14-17 Figure 14-16 Structure of the COA concatenating cable.................................................................................14-18 Figure 14-17 Structure of the straight through cable........................................................................................14-19 Figure 14-18 Structure of the crossover cable..................................................................................................14-20 Figure 14-19 Structure of the 75-ohm 8 x E1 cable.........................................................................................14-22 Figure 14-20 Structure of the 75-ohm 16 x E1 cable.......................................................................................14-24 Figure 14-21 Structure of the 120-ohm 8 x E1 cable.......................................................................................14-27 Figure 14-22 Structure of the 120-ohm 16 x E1 cable.....................................................................................14-29 Figure 14-23 Structure of the E3/T3/STM-1 cable..........................................................................................14-31 Figure 14-24 Structure of the V.35 DCE cable................................................................................................14-34 Figure 14-25 Structure of the V.35 DTE cable................................................................................................14-35 Figure 14-26 Structure of the V.24 DCE cable................................................................................................14-37 Figure 14-27 Structure of the V.24 DTE cable................................................................................................14-38 Figure 14-28 Structure of the X.21 DCE cable................................................................................................14-40 Figure 14-29 Structure of the X.21 DTE cable................................................................................................14-41 Figure 14-30 Structure of the RS449 DCE cable.............................................................................................14-42 Figure 14-31 Structure of the RS449 DTE cable.............................................................................................14-44 Figure 14-32 Structure of the RS530 DCE cable.............................................................................................14-46 Figure 14-33 Structure of the RS530 DTE cable.............................................................................................14-48 Figure 14-34 Structure of the 75-ohm clock cable...........................................................................................14-50 Figure 14-35 Structure of the 120-ohm clock cable.........................................................................................14-50 xxx Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
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Figure 14-36 Structure of the one-channel clock transfer cable (75 ohms to 120 ohms)................................14-51 Figure 14-37 Structure of the two-channel clock transfer cable (75 ohms to 120 ohms)................................14-52 Figure B-1 Labels on the OptiX OSN 1500B subrack........................................................................................B-4 Figure B-2 Labels on the OptiX OSN 1500A subrack........................................................................................B-4 Figure B-3 Labels on a board..............................................................................................................................B-5 Figure B-4 Optical module labels........................................................................................................................B-5
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Tables
Table 2-1 Indicators on the ETSI cabinet.............................................................................................................2-3 Table 2-2 Connection of power terminals at side A and side B...........................................................................2-4 Table 2-3 Technical specifications of the ETSI cabinet.......................................................................................2-5 Table 3-1 Mapping relation between slots for the interface boards and slots for the processing boards of the OptiX OSN 1500A...........................................................................................................................................................3-5 Table 3-2 CXL series boards and their valid slots of the OptiX OSN 1500A.....................................................3-6 Table 3-3 SDH processing boards and their valid slots of the OptiX OSN 1500A.............................................3-7 Table 3-4 PDH processing boards and their valid slots of the OptiX OSN 1500A.............................................3-8 Table 3-5 Interface Boards and their valid slots of the OptiX OSN 1500A.........................................................3-9 Table 3-6 Data processing boards and their valid slots of the OptiX OSN 1500A..............................................3-9 Table 3-7 WDM boards and their valid slots of the OptiX OSN 1500A...........................................................3-11 Table 3-8 Optical booster amplifier boards and their valid slots of the OptiX OSN 1500A.............................3-12 Table 3-9 Auxiliary boards and their valid slots of the OptiX OSN 1500A......................................................3-12 Table 3-10 Mapping relation between slots for the interface boards and slots for the processing boards of the OptiX OSN 1500B.........................................................................................................................................................3-14 Table 3-11 CXL series boards and their valid slots for the OptiX OSN 1500B................................................3-14 Table 3-12 SDH processing boards and their valid slots for the OptiX OSN 1500B........................................3-15 Table 3-13 PDH processing boards and their valid slots for the OptiX OSN 1500B........................................3-17 Table 3-14 Interface/protection switching boards and their valid slots for the OptiX OSN 1500B..................3-18 Table 3-15 Data processing boards and their valid slots for the OptiX OSN 1500B.........................................3-19 Table 3-16 WDM boards and their valid slots for the OptiX OSN 1500B........................................................3-23 Table 3-17 Optical booster amplifier boards and their valid slots for the OptiX OSN 1500B..........................3-23 Table 3-18 Auxiliary boards and their valid slots for the OptiX OSN 1500B...................................................3-24 Table 3-19 Technical specifications of the OptiX OSN 1500A subrack............................................................3-24 Table 3-20 Maximum power consumption of the OptiX OSN 1500A subrack.................................................3-24 Table 3-21 Technical specifications of the OptiX OSN 1500B subrack............................................................3-25 Table 3-22 Maximum power consumption of the OptiX OSN 1500B subrack.................................................3-25 Table 4-1 Appearance and dimensions of boards for the OptiX OSN 1500........................................................4-2 Table 4-2 SDH processing boards for the OptiX OSN 1500A.............................................................................4-4 Table 4-3 SDH processing boards for the OptiX OSN 1500B.............................................................................4-5 Table 4-4 PDH processing boards for the OptiX OSN 1500A.............................................................................4-7 Table 4-5 PDH processing boards for the OptiX OSN 1500B.............................................................................4-7 Table 4-6 Data processing boards for the OptiX OSN 1500A.............................................................................4-8 Table 4-7 Data processing boards for the OptiX OSN 1500B.............................................................................4-8 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd xxxiii
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OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description Table 4-8 Interface boards and switching boards supported by the OptiX OSN 1500A.....................................4-9 Table 4-9 Interface boards and switching boards supported by the OptiX OSN 1500B......................................4-9 Table 4-10 Cross-connect boards and SCC boards supported by the OptiX OSN 1500A and the OptiX OSN 1500B .............................................................................................................................................................................4-10 Table 4-11 Auxiliary boards supported by the OptiX OSN 1500A and the OptiX OSN 1500B......................4-11 Table 4-12 Optical add/drop multiplexing boards supported by the OptiX OSN 1500A..................................4-11 Table 4-13 Optical add/drop multiplexing boards supported by the OptiX OSN 1500B..................................4-11 Table 4-14 Optical amplifier boards and dispersion compensation boards supported by the OptiX OSN 1500A/B .............................................................................................................................................................................4-12 Table 5-1 Version Description of the SL1............................................................................................................5-3 Table 5-2 Functions and features of the SL1........................................................................................................5-4 Table 5-3 Optical interfaces of the SL1................................................................................................................5-8 Table 5-4 Relation between the board feature code and the optical interface type..............................................5-9 Table 5-5 Specifications of the optical interfaces of the SL1.............................................................................5-10 Table 5-6 Functions and features of the SL16A board.......................................................................................5-12 Table 5-7 Optical interfaces of the SL1A...........................................................................................................5-15 Table 5-8 Relation between the board feature code and optical interface type of the SL1A.............................5-15 Table 5-9 Specifications of the optical interfaces of the SL1A board................................................................5-16 Table 5-10 Version Description of the SLQ1.....................................................................................................5-18 Table 5-11 Functions and features of the SLQ1.................................................................................................5-18 Table 5-12 Optical interfaces of the SLQ1.........................................................................................................5-22 Table 5-13 Relation between the board feature code and the optical interface type..........................................5-23 Table 5-14 Specifications of the optical interfaces of the SLQ1........................................................................5-24 Table 5-15 Functions and features of the SLQ1A board....................................................................................5-26 Table 5-16 Optical interfaces of the SLQ1A board............................................................................................5-29 Table 5-17 Relation between the board feature code and optical interface type of the SLQ1A........................5-30 Table 5-18 Specifications of the optical interfaces of the SLQ1A board...........................................................5-31 Table 5-19 Functions and features of the SLO1 board.......................................................................................5-33 Table 5-20 Optical interfaces of the SLO1.........................................................................................................5-36 Table 5-21 Relation between the board feature code and the optical interface type..........................................5-37 Table 5-22 Specifications of the optical interfaces of the SLO1........................................................................5-38 Table 5-23 Functions and features of the SLT1.................................................................................................5-39 Table 5-24 Optical interfaces of the SLT1.........................................................................................................5-43 Table 5-25 Specifications of the optical interfaces of the SLT1........................................................................5-44 Table 5-26 Functions and features of the SEP1.................................................................................................5-46 Table 5-27 Access capabilities for the SEP1......................................................................................................5-47 Table 5-28 Electrical interfaces of the SEP1......................................................................................................5-52 Table 5-29 Slots for the SEP1, EU08 and TSB8................................................................................................5-53 Table 5-30 Technical specifications of the SEP1 board.....................................................................................5-54 Table 5-31 Version Description of the SL4........................................................................................................5-55 Table 5-32 Functions and features of the SL4....................................................................................................5-56 Table 5-33 Optical interfaces of the SL4............................................................................................................5-60 Table 5-34 Relation between the board feature code and the optical interface type of the SL4........................5-60
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Table 5-35 Specifications of the optical interfaces of the SL4...........................................................................5-61 Table 5-36 Functions and features of the SL4A.................................................................................................5-63 Table 5-37 Optical interfaces of the SL4A.........................................................................................................5-66 Table 5-38 Relation between the board feature code and optical interface type of the SL4A...........................5-67 Table 5-39 Specifications of the optical interfaces of the SL4A board..............................................................5-68 Table 5-40 Version Description of the SLD4.....................................................................................................5-69 Table 5-41 Functions and features of the SLD4.................................................................................................5-70 Table 5-42 Optical interfaces of the SLD4.........................................................................................................5-74 Table 5-43 Relation between the board feature code and the optical interface type of the SLD4.....................5-75 Table 5-44 Specifications of the optical interfaces of the SLD4........................................................................5-76 Table 5-45 Functions and features of the SLD4A board....................................................................................5-78 Table 5-46 Optical interfaces of the SLD4A board............................................................................................5-80 Table 5-47 Relation between the board feature code and optical interface type of the SLD4A........................5-81 Table 5-48 Specifications of the optical interfaces of the SLD4A board...........................................................5-82 Table 5-49 Version Description of the SLQ4.....................................................................................................5-83 Table 5-50 Functions and features of the SLQ4.................................................................................................5-84 Table 5-51 Optical interfaces of the SLQ4.........................................................................................................5-88 Table 5-52 Relation between the board feature code and the optical interface type of the SLQ4.....................5-88 Table 5-53 Specifications of the optical interfaces of the SLQ4........................................................................5-89 Table 5-54 Functions and features of the SLQ4A board....................................................................................5-91 Table 5-55 Optical interfaces of the SLQ4A board............................................................................................5-94 Table 5-56 Relation between the board feature code and optical interface type of the SLQ4A........................5-94 Table 5-57 Specifications of the optical interfaces of the SLQ4A board...........................................................5-95 Table 5-58 Version Description of the SL16......................................................................................................5-97 Table 5-59 Functions and features of the SL16..................................................................................................5-97 Table 5-60 Optical interfaces of the SL16........................................................................................................5-101 Table 5-61 Relation between the board feature code and the optical interface type for the SL16...................5-102 Table 5-62 Specifications of the optical interfaces of the SL16.......................................................................5-103 Table 5-63 Specifications of the ITU-T G.692-compliant optical interfaces that output standard wavelengths ...........................................................................................................................................................................5-103 Table 5-64 Version Description of the SL16A.................................................................................................5-105 Table 5-65 Functions and features of the SL16A.............................................................................................5-106 Table 5-66 Optical interfaces of the SL16A.....................................................................................................5-110 Table 5-67 Relation between the board feature code and the optical interface type........................................5-110 Table 5-68 Specifications of the optical interfaces of the SL16A....................................................................5-111 Table 5-69 Functions and features of the SF16................................................................................................5-113 Table 5-70 Optical interfaces of the SF16........................................................................................................5-118 Table 5-71 Specifications of the optical interfaces of the SF16.......................................................................5-118 Table 5-72 Specifications of the ITU-T G.692-compliant optical interfaces that output standard wavelengths ...........................................................................................................................................................................5-119 Table 6-1 Functions and features of the PL1........................................................................................................6-3 Table 6-2 Interfaces on the front panel of the PL1...............................................................................................6-7 Table 6-3 Relation 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OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description Table 6-4 Specifications of the electrical interfaces of the PL1...........................................................................6-8 Table 6-5 Version Description of the PD1...........................................................................................................6-9 Table 6-6 Functions and features of the PD1.....................................................................................................6-10 Table 6-7 Valid slots for the PD1 and corresponding slots for the L75S and L12S in the OptiX OSN 1500A subrack .............................................................................................................................................................................6-14 Table 6-8 Valid slots for the PD1 and corresponding slots for the D75S and D12S in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-14 Table 6-9 Relation between the board feature code and the interface impedance type.....................................6-15 Table 6-10 Slot configuration for the 1:2 TPS protection for the PD1 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-17 Table 6-11 Version Description of the PQ1.......................................................................................................6-19 Table 6-12 Functions and features of the PQ1...................................................................................................6-19 Table 6-13 Valid slots for the PQ1 and corresponding slots for the D75S, D12S or D12B in the OptiX OSN 1500B subrack................................................................................................................................................................6-24 Table 6-14 Relation between the board feature code and the interface impedance type...................................6-24 Table 6-15 Slot configuration for the 1:2 TPS protection for the PQ1 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-25 Table 6-16 Functions and features of the PQM..................................................................................................6-27 Table 6-17 Valid slots for the PQM and corresponding slots for the D12S and D12B in the OptiX OSN 1500B subrack................................................................................................................................................................6-32 Table 6-18 Slot configuration for the 1:2 TPS protection for the PQM in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-33 Table 6-19 Version description of the PL3........................................................................................................6-35 Table 6-20 Functions and features of the PL3....................................................................................................6-36 Table 6-21 Valid slots for the PL3 and corresponding slots for the C34S in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-40 Table 6-22 Slot configuration for the 1:1 TPS protection for the PL3 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-41 Table 6-23 Slots for the PL3, C34S and TSB8 in the OptiX OSN 1500B subrack...........................................6-42 Table 6-24 Version description of the PL3A......................................................................................................6-44 Table 6-25 Functions and features of the PL3A.................................................................................................6-44 Table 6-26 Specifications of the electrical interfaces of the PL3A....................................................................6-49 Table 6-27 Version Description of the PD3.......................................................................................................6-50 Table 6-28 Functions and features of the PD3...................................................................................................6-51 Table 6-29 Valid slots for the PD3 and corresponding slots for the D34S in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-55 Table 6-30 Slot configuration for the 1:1 TPS protection for the PD3 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-56 Table 6-31 Slots for the PD3, D34S and TSB8 in the OptiX OSN 1500B subrack...........................................6-56 Table 6-32 Functions and features of the PQ3...................................................................................................6-58 Table 6-33 Valid slots for the PQ3 and corresponding slots for the D34S in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-63 Table 6-34 Slot configuration for the 1:1 TPS protection for the PQ3 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-64 Table 6-35 Slots for the PQ3, D34S and TSB8 in the OptiX OSN 1500B subrack...........................................6-64 Table 6-36 Functions and features of the DX1...................................................................................................6-66
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Table 6-37 Valid slots for the DX1 and corresponding slots for the DM12 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-69 Table 6-38 Relation between the board feature code and the interface impedance type...................................6-69 Table 6-39 Slots for the DX1 and DM12 in the OptiX OSN 1500B subrack....................................................6-71 Table 6-40 Functions and features of the DXA..................................................................................................6-73 Table 6-41 Version Description of the SPQ4.....................................................................................................6-77 Table 6-42 Functions and features of the SPQ4.................................................................................................6-77 Table 6-43 Valid slots for the SPQ4 and corresponding slots for the MU04 in the OptiX OSN 1500B subrack .............................................................................................................................................................................6-84 Table 6-44 Slots for the SPQ4, MU04 and TSB8 in the OptiX OSN 1500B subrack.......................................6-85 Table 7-1 Functions and features of the EFT4.....................................................................................................7-3 Table 7-2 Optical interfaces of the EFT4.............................................................................................................7-7 Table 7-3 Pins of the RJ-45 of the EFT4..............................................................................................................7-8 Table 7-4 Functions and features of the EFT8.....................................................................................................7-9 Table 7-5 Optical interfaces of the EFT8...........................................................................................................7-14 Table 7-6 Pins of the RJ-45 of the EFT8............................................................................................................7-14 Table 7-7 Valid slots for the EFT8 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500A .............................................................................................................................................................................7-15 Table 7-8 Valid slots for the EFT8 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500B .............................................................................................................................................................................7-15 Table 7-9 Functions and features of the EFT8A................................................................................................7-16 Table 7-10 Optical interfaces of the EFT8A......................................................................................................7-21 Table 7-11 Pins of the RJ-45 of the EFT8A.......................................................................................................7-21 Table 7-12 Functions and features of the EGT2.................................................................................................7-23 Table 7-13 Optical interfaces of the EGT2.........................................................................................................7-28 Table 7-14 Relation between the board feature code and the optical interface type..........................................7-28 Table 7-15 Specifications of the optical interfaces of the EGT2........................................................................7-29 Table 7-16 Version Description of the EFS0.....................................................................................................7-30 Table 7-17 Functions and features of the EFS0.................................................................................................7-31 Table 7-18 Valid slots for the EFS0 and corresponding slots for the ETF8, EFF8 and ETS8 in the OptiX OSN 1500B subrack.....................................................................................................................................................7-37 Table 7-19 Version Description of the EFS4.....................................................................................................7-39 Table 7-20 Functions and features of the EFS4.................................................................................................7-40 Table 7-21 Optical interfaces of the EFS4.........................................................................................................7-45 Table 7-22 Pins of the RJ-45 of the EFS4..........................................................................................................7-45 Table 7-23 Version Description of the EGS2.....................................................................................................7-47 Table 7-24 Functions and features of the EGS2.................................................................................................7-48 Table 7-25 Optical interfaces of the EGS2.........................................................................................................7-54 Table 7-26 Relation between the board feature code and the optical interface type..........................................7-54 Table 7-27 Specifications of the optical interfaces of the EGS2........................................................................7-55 Table 7-28 Functions and features of the EMS4................................................................................................7-56 Table 7-29 Optical interfaces of the EMS4........................................................................................................7-63 Table 7-30 Valid slots for the EMS4 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500A subrack................................................................................................................................................................7-63 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd xxxvii
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OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description Table 7-31 Valid slots for the EMS4 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500B subrack................................................................................................................................................................7-63 Table 7-32 Relation between the board feature code and the optical interface type..........................................7-64 Table 7-33 Specifications of the optical interfaces of the EMS4.......................................................................7-68 Table 7-34 Version Description of the EGS4.....................................................................................................7-70 Table 7-35 Functions and features of the EGS4.................................................................................................7-70 Table 7-36 Optical interfaces of the EGS4.........................................................................................................7-77 Table 7-37 Relation between the board feature code and the optical interface type..........................................7-77 Table 7-38 Specifications of the optical interfaces of the EGS4........................................................................7-81 Table 7-39 Functions and features of the EGS4A..............................................................................................7-83 Table 7-40 Optical interfaces of the EGS4A......................................................................................................7-89 Table 7-41 Relation between the board feature code and the optical interface type..........................................7-89 Table 7-42 Specifications of the optical interfaces of the EGS4A.....................................................................7-92 Table 7-43 Functions and features of the EGR2................................................................................................7-93 Table 7-44 Optical interfaces of the EGR2 .....................................................................................................7-100 Table 7-45 Relation between the board feature code and the optical interface type........................................7-100 Table 7-46 Specifications of the interfaces of the EGR2.................................................................................7-101 Table 7-47 Version description of the EMR0..................................................................................................7-102 Table 7-48 Comparison of features of the N1EMR0 and N2EMR0................................................................7-102 Table 7-49 Functions and features of the EMR0..............................................................................................7-103 Table 7-50 Optical interfaces of the EMR0 .....................................................................................................7-111 Table 7-51 Valid slots for the EMR0 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500A subrack..............................................................................................................................................................7-111 Table 7-52 Valid slots for the EMR0 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500B subrack..............................................................................................................................................................7-111 Table 7-53 Relation between the board feature code and the optical interface type........................................7-112 Table 7-54 Specifications of the optical interfaces of the EMR0.....................................................................7-113 Table 7-55 Functions and features of the ADL4..............................................................................................7-114 Table 7-56 Optical interface of the ADL4 .......................................................................................................7-119 Table 7-57 Relation between the board feature code and the optical interface type........................................7-119 Table 7-58 Specifications of the optical interfaces of the ADL4.....................................................................7-120 Table 7-59 Functions and features of the ADQ1..............................................................................................7-121 Table 7-60 Optical interfaces of the ADQ1 .....................................................................................................7-126 Table 7-61 Relation between the board feature code and the optical interface type........................................7-126 Table 7-62 Specifications of the optical interfaces of the ADQ1.....................................................................7-127 Table 7-63 Functions and features of the IDL4................................................................................................7-129 Table 7-64 Optical interface of the IDL4 ........................................................................................................7-134 Table 7-65 Relation between the board feature code and the optical interface type........................................7-134 Table 7-66 Specifications of the optical interfaces of the IDL4.......................................................................7-135 Table 7-67 Functions and features of the IDQ1...............................................................................................7-137 Table 7-68 Optical interfaces of the IDQ1 ......................................................................................................7-142 Table 7-69 Relation between the board feature code and the optical interface type........................................7-142 Table 7-70 Specifications of the optical interfaces of the IDQ1......................................................................7-143
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Table 7-71 Functions and features of the MST4..............................................................................................7-145 Table 7-72 Services and service rates provided by the MST4.........................................................................7-145 Table 7-73 Optical interfaces of the MST4......................................................................................................7-149 Table 7-74 Relation between the board feature code and service type............................................................7-149 Table 7-75 Specifications of the optical interfaces of the MST4.....................................................................7-150 Table 8-1 Valid slots for the PD1 and corresponding slots for the L12S in the OptiX OSN 1500A subrack ...............................................................................................................................................................................8-5 Table 8-2 Interfaces on the front panel of the D12B............................................................................................8-7 Table 8-3 Pins of the DB44 interfaces of the D12B.............................................................................................8-8 Table 8-4 Valid slots for the PQ1/PQM and corresponding slots for the D12B in the OptiX OSN 1500B subrack ...............................................................................................................................................................................8-8 Table 8-5 Interfaces on the front panel of the D12S..........................................................................................8-11 Table 8-6 Pins of the DB44 interfaces of the D12S...........................................................................................8-12 Table 8-7 Valid slots for the PQ1/PQM and corresponding slots for the D12S in the OptiX OSN 1500B subrack .............................................................................................................................................................................8-12 Table 8-8 Valid slots for the PD1 and corresponding slots for the L75S...........................................................8-15 Table 8-9 Interfaces on the front panel of the D75S..........................................................................................8-18 Table 8-10 Pins of the DB44 interfaces of the D75S.........................................................................................8-19 Table 8-11 Valid slots for the PQ1 and corresponding slots for the D75S in the OptiX OSN 1500B subrack .............................................................................................................................................................................8-19 Table 8-12 Interfaces of the D34S......................................................................................................................8-22 Table 8-13 Specifications of the electrical interfaces of the D34S....................................................................8-23 Table 8-14 Interfaces of the C34S......................................................................................................................8-25 Table 8-15 Valid slots for the PL3 and corresponding slots for the C34S in the OptiX OSN 1500B subrack .............................................................................................................................................................................8-26 Table 8-16 Specifications of the electrical interfaces of the C34S.....................................................................8-26 Table 8-17 Interfaces of the EU04.....................................................................................................................8-29 Table 8-18 Valid slots for the SEP and corresponding slots for the EU04........................................................8-30 Table 8-19 Specifications of the electrical interfaces of the EU04....................................................................8-30 Table 8-20 Interfaces of the EU08.....................................................................................................................8-33 Table 8-21 Valid slots for the SEP and corresponding slots for the EU08........................................................8-33 Table 8-22 Specifications of the electrical interfaces of the EU08....................................................................8-33 Table 8-23 Version description of the OU08.....................................................................................................8-35 Table 8-24 Interfaces of the N1OU08................................................................................................................8-37 Table 8-25 Interfaces of the N2OU08................................................................................................................8-38 Table 8-26 Valid slots for the SEP and corresponding slots for the OU08........................................................8-38 Table 8-27 Specifications of the optical interfaces of the OU08........................................................................8-38 Table 8-28 Interfaces of the MU04....................................................................................................................8-41 Table 8-29 Valid slots for the SPQ4 and corresponding slots for the MU04.....................................................8-42 Table 8-30 Specifications of the electrical interfaces of the MU04...................................................................8-42 Table 8-31 Valid slots for the TSB4 and corresponding slots for the SPQ4 and MU04....................................8-45 Table 8-32 Valid slots for the TSB4 and corresponding slots for the SEP and EU04.......................................8-45 Table 8-33 Valid slots for the TSB4 and corresponding slots for the EFS0 and ETS8.....................................8-45 Table 8-34 Valid slots for the TSB8 and corresponding slots for the SPQ4 and MU04....................................8-48 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd xxxix
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OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description Table 8-35 Valid slots for the TSB8 and corresponding slots for the PD3 and D34S.......................................8-49 Table 8-36 Valid slots for the TSB8 and corresponding slots for the SEP and EU04.......................................8-49 Table 8-37 Valid slots for the TSB8 and corresponding slots for the SEP and EU08.......................................8-49 Table 8-38 Valid slots for the TSB8 and corresponding slots for the EFS0 and ETS8.....................................8-49 Table 8-39 Valid slots for the TSB8 and corresponding slots for the PL3 and C34S........................................8-50 Table 8-40 Valid slots for the TSB8 and corresponding slots for the PQ3 and D34S.......................................8-50 Table 8-41 Interfaces of the EFF8......................................................................................................................8-53 Table 8-42 Valid slots for the EFT8 and corresponding slots for the EFF8......................................................8-53 Table 8-43 Valid slots for the EFS0 and corresponding slots for the EFF8.......................................................8-53 Table 8-44 Valid slots for the EMS4 and corresponding slots for the EFF8.....................................................8-54 Table 8-45 Valid slots for the EMR0 and corresponding slots for the EFF8.....................................................8-54 Table 8-46 Specifications of the optical interfaces of the EFF8........................................................................8-54 Table 8-47 Interfaces of the ETF8......................................................................................................................8-57 Table 8-48 Pins of the RJ-45 connector of the ETF8.........................................................................................8-58 Table 8-49 Valid slots for the EFT8 and corresponding slots for the ETF8......................................................8-58 Table 8-50 Valid slots for the EFS0 and corresponding slots for the ETF8......................................................8-59 Table 8-51 Valid slots for the EMS4 and corresponding slots for the ETF8.....................................................8-59 Table 8-52 Valid slots for the EMR0 and corresponding slots for the ETF8.....................................................8-59 Table 8-53 Specifications of the electrical interfaces of the ETF8....................................................................8-59 Table 8-54 Interfaces of the ETS8......................................................................................................................8-62 Table 8-55 Pins of the RJ-45 connector of the ETS8.........................................................................................8-63 Table 8-56 Valid slots for the EFS0 and corresponding slots for the ETS8......................................................8-63 Table 8-57 Specifications of the electrical interfaces of the ETS8....................................................................8-63 Table 8-58 Interfaces on the front panel of the DM12.......................................................................................8-66 Table 8-59 Pins of the DB44 interfaces of the DM12........................................................................................8-67 Table 8-60 Pins of the DB28 interfaces of the DM12........................................................................................8-68 Table 8-61 Valid slots for the DX1 and corresponding slots for the DM12......................................................8-68 Table 9-1 Version description of the CXL1 board...............................................................................................9-4 Table 9-2 Function and feature of the SDH processing unit of the CXL1...........................................................9-4 Table 9-3 Function and feature of the SCC unit of the CXL1............................................................................. 9-5 Table 9-4 Function and feature of the cross-connect unit of the CXL1...............................................................9-6 Table 9-5 Function and feature of the clock unit of the CXL1............................................................................ 9-6 Table 9-6 Jumper on the CXL1 board................................................................................................................9-13 Table 9-7 DIP switch on the CXL1 board..........................................................................................................9-13 Table 9-8 Description of the DIP switch SW1...................................................................................................9-14 Table 9-9 Optical interface and switches on the CXL1......................................................................................9-17 Table 9-10 Relation between the board feature code and the optical interface type..........................................9-18 Table 9-11 Logical slots displayed on the T2000 for the CXL1........................................................................9-19 Table 9-12 Specifications for the optical interfaces of the CXL1......................................................................9-19 Table 9-13 Version description of the CXL4 board...........................................................................................9-21 Table 9-14 Function and feature of the SDH processing unit of the CXL4.......................................................9-22 Table 9-15 Function and feature of the SCC unit of the CXL4.........................................................................9-23
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Table 9-16 Function and feature of the cross-connect unit of the CXL4...........................................................9-24 Table 9-17 Function and feature of the clock unit of the CXL4........................................................................9-24 Table 9-18 Jumper on the CXL4 board..............................................................................................................9-31 Table 9-19 DIP switch on the CXL4 board........................................................................................................9-31 Table 9-20 Description of DIP switch SW1.......................................................................................................9-32 Table 9-21 Optical interface and switches on the CXL4....................................................................................9-35 Table 9-22 Relation between the board feature code and the optical interface type..........................................9-36 Table 9-23 Logical slots displayed on the T2000 for the CXL4........................................................................9-37 Table 9-24 Specifications for the optical interfaces of the CXL4......................................................................9-37 Table 9-25 Version description of the CXL16 board.........................................................................................9-39 Table 9-26 Function and feature of the SDH processing unit of the CXL16.....................................................9-40 Table 9-27 Function and feature of the SCC unit of the CXL16.......................................................................9-41 Table 9-28 Function and feature of the cross-connect unit of the CXL16.........................................................9-42 Table 9-29 Function and feature of the clock unit of the CXL16......................................................................9-42 Table 9-30 Jumper on the CXL16 board............................................................................................................9-49 Table 9-31 DIP switch on the CXL16 board......................................................................................................9-49 Table 9-32 Description of the DIP switch SW1.................................................................................................9-50 Table 9-33 Optical interface and switches on the CXL16..................................................................................9-53 Table 9-34 Relation between the board feature code and the optical interface type..........................................9-54 Table 9-35 Logical slots displayed on the T2000 for the CXL16......................................................................9-54 Table 9-36 Specifications for the optical interfaces of the CXL16....................................................................9-55 Table 9-37 Function and feature of the SDH processing unit of the CXLL1.....................................................9-57 Table 9-38 Function and feature of the SCC unit of the CXLL1.......................................................................9-58 Table 9-39 Function and feature of the cross-connect unit of the CXLL1.........................................................9-59 Table 9-40 Function and feature of the clock unit of the CXLL1......................................................................9-59 Table 9-41 Jumper on the CXL board................................................................................................................9-66 Table 9-42 DIP switch on the CXL board..........................................................................................................9-66 Table 9-43 Description of the DIP switch SW2.................................................................................................9-66 Table 9-44 Optical interface and switches on the CXLL1.................................................................................9-68 Table 9-45 Relation between the board feature code and the optical interface type..........................................9-69 Table 9-46 Logical slots displayed on the T2000 for the CXLL1......................................................................9-69 Table 9-47 Specifications for the optical interfaces of the CXLL1....................................................................9-70 Table 9-48 Function and feature of the SDH processing unit of the CXLL4.....................................................9-72 Table 9-49 Function and feature of the SCC unit of the CXLL4.......................................................................9-73 Table 9-50 Function and feature of the cross-connect unit of the CXLL4.........................................................9-73 Table 9-51 Function and feature of the clock unit of the CXLL4......................................................................9-74 Table 9-52 Jumper on the CXL board................................................................................................................9-80 Table 9-53 DIP switch on the CXL board..........................................................................................................9-80 Table 9-54 Description of DIP switch SW2.......................................................................................................9-80 Table 9-55 Optical interface and switches on the CXLL4.................................................................................9-82 Table 9-56 Relation between the board feature code and the optical interface type..........................................9-83 Table 9-57 Logical slots displayed on the T2000 for the CXLL4......................................................................9-83 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright 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OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description Table 9-58 Specifications for the optical interfaces of the CXLL4....................................................................9-84 Table 9-59 Function and feature of the SDH processing unit of the CXLL16...................................................9-86 Table 9-60 Function and feature of the SCC unit of the CXLL16.....................................................................9-87 Table 9-61 Function and feature of the cross-connect unit of the CXLL16.......................................................9-87 Table 9-62 Function and feature of the clock unit of the CXLL16....................................................................9-88 Table 9-63 Jumper on the CXL board................................................................................................................9-94 Table 9-64 DIP switch on the CXL board..........................................................................................................9-94 Table 9-65 Description of the DIP switch SW2.................................................................................................9-94 Table 9-66 Optical interface and switches on the CXLL16...............................................................................9-96 Table 9-67 Relation between the board feature code and the optical interface type..........................................9-97 Table 9-68 Logical slots displayed on the T2000 for the CXLL16....................................................................9-97 Table 9-69 Specifications for the optical interfaces of the CXLL16..................................................................9-98 Table 9-70 Function and feature of the SDH processing unit of the CXLD1..................................................9-100 Table 9-71 Function and feature of the SCC unit of the CXLD1.....................................................................9-100 Table 9-72 Function and feature of the cross-connect unit of the CXLD1......................................................9-101 Table 9-73 Function and feature of the clock unit of the CXLD1....................................................................9-102 Table 9-74 Jumper on the CXL board..............................................................................................................9-108 Table 9-75 DIP switch on the CXL board........................................................................................................9-108 Table 9-76 Description of DIP switch SW2.....................................................................................................9-108 Table 9-77 Optical interface and switches on the CXLD1...............................................................................9-110 Table 9-78 Relation between the board feature code and the optical interface type........................................9-111 Table 9-79 Logical slots displayed on the T2000 for the CXLD1...................................................................9-111 Table 9-80 Specifications for the optical interfaces of the CXLD1.................................................................9-112 Table 9-81 Function and feature of the SDH processing unit of the CXLD4..................................................9-114 Table 9-82 Function and feature of the SCC unit of the CXLD4.....................................................................9-115 Table 9-83 Function and feature of the cross-connect unit of the CXLD4......................................................9-115 Table 9-84 Function and feature of the clock unit of the CXLD4....................................................................9-116 Table 9-85 Jumper on the CXLD4 board.........................................................................................................9-122 Table 9-86 DIP switch on the CXLD4 board...................................................................................................9-122 Table 9-87 Description of DIP switch SW2.....................................................................................................9-122 Table 9-88 Optical interface and switches on the CXLD4...............................................................................9-124 Table 9-89 Relation between the board feature code and the optical interface type........................................9-125 Table 9-90 Logical slots displayed on the T2000 for the CXLD1...................................................................9-125 Table 9-91 Specifications for the optical interfaces of the CXLD4.................................................................9-126 Table 9-92 Function and feature of the SDH processing unit of the CXLQ1..................................................9-128 Table 9-93 Function and feature of the SCC unit of the CXLQ1.....................................................................9-129 Table 9-94 Function and feature of the cross-connect unit of the CXLQ1......................................................9-129 Table 9-95 Function and feature of the clock unit of the CXLQ1....................................................................9-130 Table 9-96 Jumper on the CXLQ1 board.........................................................................................................9-136 Table 9-97 DIP switch on the CXLQ1 board...................................................................................................9-136 Table 9-98 Description of DIP switch SW2.....................................................................................................9-136 Table 9-99 Optical interface and switches on the CXLQ1...............................................................................9-138
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Table 9-100 Relation between the board feature code and the optical interface type......................................9-139 Table 9-101 Logical slots displayed on the T2000 for the CXLQ1.................................................................9-139 Table 9-102 Specifications for the optical interfaces of the CXLQ1...............................................................9-140 Table 9-103 Function and feature of the SDH processing unit of the CXLQ4................................................9-142 Table 9-104 Function and feature of the SCC unit of the CXLQ4...................................................................9-143 Table 9-105 Function and feature of the cross-connect unit of the CXLQ4....................................................9-143 Table 9-106 Function and feature of the clock unit of the CXLQ4..................................................................9-144 Table 9-107 Jumper on the CXLQ4 board.......................................................................................................9-150 Table 9-108 DIP switch on the CXLQ4 board.................................................................................................9-150 Table 9-109 Description of DIP switch SW2...................................................................................................9-150 Table 9-110 Optical interface and switches on the CXLQ4.............................................................................9-152 Table 9-111 Relation between the board feature code and the optical interface type......................................9-153 Table 9-112 Logical slots displayed on the T2000 for the CXLQ1.................................................................9-153 Table 9-113 Specifications for the optical interfaces of the CXLQ4...............................................................9-154 Table 10-1 Functions and features of the EOW.................................................................................................10-2 Table 10-2 Interfaces on the front panel of the EOW........................................................................................10-5 Table 10-3 Pins of the PHONE interface of the EOW.......................................................................................10-5 Table 10-4 Pins of the S1, S2, S3 and S4 interfaces of the EOW......................................................................10-5 Table 10-5 Functions and features of the AUX..................................................................................................10-7 Table 10-6 Interfaces on the front panel of the AUX.......................................................................................10-12 Table 10-7 Pins of the CLK interface of the AUX...........................................................................................10-12 Table 10-8 Pins of the ETH and COM interfaces of the AUX.........................................................................10-12 Table 10-9 Pins of the ALM interface of the AUX..........................................................................................10-13 Table 10-10 Pins of the OAM interface of the AUX.......................................................................................10-13 Table 10-11 Pins of the F&f interface of the AUX..........................................................................................10-14 Table 10-12 Functions and features of the AMU.............................................................................................10-15 Table 10-13 Interfaces on the front panel of the AMU....................................................................................10-17 Table 10-14 Pins of the PHONE interface of the AMU...................................................................................10-18 Table 10-15 Pins of the S1 and S2 interfaces of the AMU..............................................................................10-18 Table 10-16 Pins of the LAMP1 and LAMP2 interfaces of the AMU.............................................................10-19 Table 10-17 Functions and features of the FAN..............................................................................................10-21 Table 11-1 Functions and features of the CMR2...............................................................................................11-3 Table 11-2 Optical interfaces of the CMR2.......................................................................................................11-7 Table 11-3 Feature code of the CMR2...............................................................................................................11-7 Table 11-4 Specifications of the optical interfaces of the CMR2......................................................................11-8 Table 11-5 Functions and features of the CMR4.............................................................................................11-10 Table 11-6 Optical interfaces of the CMR4.....................................................................................................11-13 Table 11-7 Feature code of the CMR4.............................................................................................................11-13 Table 11-8 Specifications of the optical interfaces of the CMR4....................................................................11-14 Table 11-9 Functions and features of the MR2................................................................................................11-16 Table 11-10 Optical interfaces of the MR2......................................................................................................11-19 Table 11-11 Feature code of the MR2..............................................................................................................11-19 Issue 02 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OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description Table 11-12 Specifications of the optical interfaces of the MR2.....................................................................11-20 Table 11-13 Functions and features of the MR2A...........................................................................................11-22 Table 11-14 Optical interfaces of the MR2A...................................................................................................11-25 Table 11-15 Specifications of the optical interfaces of the MR2A..................................................................11-25 Table 11-16 Functions and features of the MR2B...........................................................................................11-27 Table 11-17 Optical interfaces of the MR2B...................................................................................................11-30 Table 11-18 Specifications of the optical interfaces of the MR2B..................................................................11-30 Table 11-19 Functions and features of the MR2C...........................................................................................11-32 Table 11-20 Optical interfaces of the MR2C...................................................................................................11-35 Table 11-21 Specifications of the optical interfaces of the MR2C..................................................................11-36 Table 11-22 Functions and features of the MR4..............................................................................................11-37 Table 11-23 Optical interfaces of the MR4......................................................................................................11-40 Table 11-24 Board feature code.......................................................................................................................11-41 Table 11-25 Specifications of the optical interfaces of the MR4.....................................................................11-41 Table 11-26 Functions and features of the LWX.............................................................................................11-43 Table 11-27 Optical interfaces on the front panel of the LWX........................................................................11-48 Table 11-28 Relation between the board feature code and the receive/transmit scheme.................................11-48 Table 11-29 Specifications of the client-side optical interfaces of the LWX...................................................11-49 Table 11-30 Specifications of the WDM-side optical interfaces of the LWX.................................................11-50 Table 11-31 Functions and features of the OBU1............................................................................................11-52 Table 11-32 Optical interfaces of the OBU1....................................................................................................11-56 Table 11-33 Feature code of the OBU1............................................................................................................11-56 Table 11-34 Specifications of optical interfaces of the OBU1.........................................................................11-57 Table 11-35 Functions and features of the FIB................................................................................................11-59 Table 11-36 Optical interfaces of the FIB .......................................................................................................11-60 Table 11-37 Specifications of the optical interfaces of the FIB.......................................................................11-61 Table 12-1 Functions and features of the BA2...................................................................................................12-3 Table 12-2 Optical interfaces of the single-interface BA2.................................................................................12-8 Table 12-3 Optical interfaces of the double-interface BA2................................................................................12-8 Table 12-4 Relation between the board feature code and output optical power for the BA2............................12-9 Table 12-5 Specifications of the optical interfaces of the BA2..........................................................................12-9 Table 12-6 Version description of the BPA board...........................................................................................12-10 Table 12-7 Functions and features of the BPA.................................................................................................12-11 Table 12-8 Optical interfaces of the BPA .......................................................................................................12-14 Table 12-9 Relation between the board feature code and output optical power of the BPA...........................12-15 Table 12-10 Specifications for the optical interfaces of the BPA....................................................................12-16 Table 12-11 Version Description of the COA..................................................................................................12-17 Table 12-12 Functions and features of the 61COA and N1COA.....................................................................12-18 Table 12-13 Functions and features of the 62COA..........................................................................................12-20 Table 12-14 Pins of the RS232 interface..........................................................................................................12-25 Table 12-15 Pins of the MONITOR-1 and MONITOR-2 interfaces...............................................................12-25 Table 12-16 Pins of the RJ-45 connector of the 62COA..................................................................................12-26
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Table 12-17 Relation between the board feature code and output optical power for the 61COA...................12-27 Table 12-18 Specifications of the optical interfaces of the COA.....................................................................12-28 Table 13-1 Functions and features of the UPM..................................................................................................13-3 Table 13-2 Interfaces on the rear panel of the UPM.......................................................................................... 13-5 Table 13-3 Pins of the RS232 interface of the UPM..........................................................................................13-5 Table 13-4 Specifications of the power supply of the UPM.............................................................................. 13-6 Table 13-5 Functions and features of the PIU....................................................................................................13-8 Table 13-6 Interfaces on the front panel of the PIU.........................................................................................13-10 Table 13-7 Functions and features of the PIUA...............................................................................................13-12 Table 13-8 Interfaces and switch on the front panel of the PIUA....................................................................13-14 Table 14-1 Types of fiber jumpers.....................................................................................................................14-2 Table 14-2 Types of connectors......................................................................................................................... 14-3 Table 14-3 Equipment 48 V/60 V power cable..............................................................................................14-8 Table 14-4 Connection of the UPM power cable...............................................................................................14-9 Table 14-5 Specifications of the UPM power cable.........................................................................................14-10 Table 14-6 Pin assignment of the alarm input/output cable.............................................................................14-11 Table 14-7 Pin assignment of the OAM serial port cable................................................................................14-13 Table 14-8 Pin assignment of the Serial 14/F1/F&f serial port cable............................................................14-15 Table 14-9 Pin assignment of the RS232/RS422 serial port cable...................................................................14-16 Table 14-10 Pin assignment of the ordinary telephone wire............................................................................14-17 Table 14-11 Pin assignment of the COA concatenating cable.........................................................................14-18 Table 14-12 Pin assignment of the straight through cable...............................................................................14-19 Table 14-13 Pin assignment of the crossover cable.........................................................................................14-21 Table 14-14 Pin assignment of the 75-ohm 8 x E1 cable.................................................................................14-23 Table 14-15 Pin assignment of the 75-ohm 16 x E1 cable...............................................................................14-24 Table 14-16 Pin assignment of the 120-ohm E1 cable.....................................................................................14-27 Table 14-17 Pin assignment of the 120-ohm 16 x E1 cable.............................................................................14-29 Table 14-18 Pin assignment of the DB28 connector of the DM12..................................................................14-32 Table 14-19 Pin assignment of the V.35 DCE cable........................................................................................14-34 Table 14-20 Pin assignment of the V.35 DTE cable........................................................................................14-36 Table 14-21 Pin assignment of the V.24 DCE cable........................................................................................14-37 Table 14-22 Technical specifications of the V.24 DCE cable..........................................................................14-38 Table 14-23 Pin assignment of the V.24 DTE cable........................................................................................14-38 Table 14-24 Technical specifications of the V.24 DTE cable..........................................................................14-39 Table 14-25 Pin assignment of the X.21 DCE cable........................................................................................14-40 Table 14-26 Technical specifications of the X.21 DCE cable..........................................................................14-40 Table 14-27 Pin assignment of the X.21 DTE cable........................................................................................14-41 Table 14-28 Technical specifications of the X.12 DTE cable..........................................................................14-42 Table 14-29 Pin assignment of the RS449 DCE cable.....................................................................................14-43 Table 14-30 Specifications of the RS449 DCE cable.......................................................................................14-43 Table 14-31 Pin assignment of the RS449 DTE cable.....................................................................................14-44 Table 14-32 Specifications of the RS449 DTE cable.......................................................................................14-45 Issue 02 (2007-03-29) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd xlv
Tables
OptiX OSN 1500 Intelligent Optical Transmission System Hardware Description Table 14-33 Pin assignment of the RS530 DCE cable.....................................................................................14-46 Table 14-34 Specifications of the RS530 DCE cable.......................................................................................14-47 Table 14-35 Pin assignment of the RS530 DTE cable.....................................................................................14-48 Table 14-36 Specifications of the RS530 DTE cable.......................................................................................14-49 Table 14-37 Pin assignment of the 120-ohm clock cable.................................................................................14-50 Table 14-38 Pin assignment of the two-channel clock transfer cable (75 ohms to 120 ohms)........................14-52 Table B-1 Labels on the equipment.....................................................................................................................B-2 Table B-2 Optical module code and type mapping table.....................................................................................B-5 Table B-3 Huawei specifications for engineering labels.....................................................................................B-7 Table C-1 Power consumption and weight of the boards....................................................................................C-1 Table D-1 Board versions that are compatible with the OptiX OSN products....................................................D-1 Table E-1 Loopbacks of the SDH boards for the OptiX OSN equipment...........................................................E-1 Table E-2 the capability of inserting the AUAIS to port.....................................................................................E-3 Table E-3 Loopbacks of the PDH boards for the OptiX OSN equipment...........................................................E-4 Table E-4 Loopbacks of the Ethernet boards for the OptiX OSN equipment.....................................................E-5 Table E-5 Loopbacks of the ATM/IMA boards for the OptiX OSN equipment.................................................E-6 Table F-1 Mapping relation between the service type and setting of the C2.......................................................F-2 Table F-2 Mapping relation between the service type and setting of the C2.......................................................F-3 Table F-3 Mapping relation between the service type and setting of the V5.......................................................F-3 Table F-4 Mapping relation between the service type and setting of the V5.......................................................F-6
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Product Versions
The following table lists the product versions related to this document. Product Name OptiX OSN 1500 OptiX iManager T2000 Version V100R008 V200R006C03
Intended Audience
The intended audiences of this document are:
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Organization
This document describes the cabinet, subrack, boards and each unit of the boards in terms of the function and working principle. Chapter 1 Equipment Structure Description This chapter describes the structure of the equipment.
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Chapter 2 Cabinet
Description This chapter describes the dimensions, appearance and technical specifications of the cabinet. This chapter also describes the configuration of the equipment in each cabinet. This chapter describes the structure of the subrack. This chapter describes the classification of boards and appearance of the boards. This chapter describes the SDH processing boards in terms of the function, principle, front panel, interface and technical specifications. This chapter describes the PDH processing boards in terms of the function, principle, front panel, interface and technical specifications. This chapter describes the data processing boards in terms of the function, principle, front panel, interface and technical specifications. This chapter describes the interface boards and switching boards in terms of the function, principle, front panel, interface and technical specifications. This chapter describes the cross-connect and system control boards in terms of the function, principle, front panel, interface and technical specifications. This chapter describes the auxiliary boards in terms of the function, principle, front panel, interface and technical specifications. This chapter describes the WDM processing boards in terms of the function, principle, front panel, interface and technical specifications. This chapter describes the optical amplifier boards and dispersion compensation boards in terms of the function, principle, front panel, interface and technical specifications. This chapter describes the power interface boards in terms of the function, principle, front panel, interface and technical specifications. This chapter describes the external cables and internal cables in terms of the structure, appearance, pin assignment and technical specifications. This appendix describes the indication of the equipment and board alarm indicators.
8 Interface Boards and Switching Boards 9 Cross-Connect and System Control Boards 10 Auxiliary Boards
12 Optical Amplifier Boards and Dispersion Compensation Boards 13 Power Interface Boards
14 Cables
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Chapter B Labels C Power Consumption and Weight of Boards D Board Version Configuration E Board Loopbacks F Board Configuration Reference G Glossary H Acronyms and Abbreviations
Description This appendix describes the safety labels, optical module labels and engineering labels. This appendix describes the power consumption and weight of each board. This appendix describes the compatibility among the product versions. This appendix describes the loopback capabilities of the boards. This appendix describes the parameters that can be configured by using the T2000. This appendix lists the terms used in this document. This appendix lists the acronyms and abbreviations used in this document.
Conventions
Symbol Conventions
The following symbols may be found in this document. They are defined as follows. Symbol Description
DANGER
Indicates a hazard with a high level of risk which, if not avoided, will result in death or serious injury. Indicates a hazard with a medium or low level of risk which, if not avoided, could result in minor or moderate injury. Indicates a potentially hazardous situation that, if not avoided, could cause equipment damage, data loss, and performance degradation, or unexpected results. Indicates a tip that may help you solve a problem or save you time. Provides additional information to emphasize or supplement important points of the main text.
WARNING
CAUTION
TIP
NOTE
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General Conventions
Convention Times New Roman Boldface Italic Courier New Description Normal paragraphs are in Times New Roman. Names of files, directories, folders, and users are in boldface. For example, log in as user root. Book titles are in italics. Terminal display is in Courier New.
Command Conventions
Convention Boldface Italic [] { x | y | ... } [ x | y | ... ] { x | y | ... } * Description The keywords of a command line are in boldface. Command arguments are in italic. Items (keywords or arguments) in square brackets [ ] are optional. Alternative items are grouped in braces and separated by vertical bars. One is selected. Optional alternative items are grouped in square brackets and separated by vertical bars. One or none is selected. Alternative items are grouped in braces and separated by vertical bars. A minimum of one or a maximum of all can be selected.
GUI Conventions
Convention Boldface > Description Buttons, menus, parameters, tabs, window, and dialog titles are in boldface. For example, click OK. Multi-level menus are in boldface and separated by the > signs. For example, choose File > Create > Folder.
Keyboard Operation
Format Key Key 1+Key 2 Description Press the key. For example, press Enter and press Tab. Press the keys concurrently. For example, pressing Ctrl+Alt+A means the three keys should be pressed concurrently.
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Description Press the keys in turn. For example, pressing Alt, A means the two keys should be pressed in turn.
Mouse Operation
Action Click Double-click Drag Description Select and release the primary mouse button without moving the pointer. Press the primary mouse button twice continuously and quickly without moving the pointer. Press and hold the primary mouse button and move the pointer to a certain position.
Update History
Updates between document versions are cumulative. Therefore, the latest document version contains all updates made to previous versions.
This release of the document fixes several bugs, adds product labels. It also checks the parameters of the dimensions and weight.
The N3SL16, N3SL16A, N2PQ3, N2PD3, N2PL3, N2PL3A, TN11OBU1, TN11MR2, TN11MR4, TN11CMR2, TN11CMR4 are added. Appendix E "Board Loopbacks" and Appendix F "Board Configuration Reference" are added. The structure of the board description is adjusted and optimized. First the board version is described, and then the board function and feature, working principle and signal flow, front panel, valid slots, board feature code, board configuration reference, technical specifications and so on are described.
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1 Equipment Structure
Equipment Structure
The OptiX OSN 1500A and the OptiX OSN 1500B are both case-shaped equipment. The OptiX OSN 1500A/B subrack can be installed in a 300-mm or 600-mm ETSI cabinet, or a 19-inch cabinet. The OptiX OSN 1500A/B can also be installed against the wall. The OptiX OSN 1500A can be installed on the desk. Figure 1-1 shows the appearance of the OptiX OSN 1500A. Figure 1-1 Appearance of the OptiX OSN 1500A
Figure 1-2 shows the appearance of the OptiX OSN 1500B. Figure 1-2 Appearance of the OptiX OSN 1500B
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2
About This Chapter
The OptiX OSN subracks are installed in the cabinets.
Cabinet
2.1 Cabinet Type The OptiX OSN 1500 subrack can be installed in a 300-mm or 600-mm ETSI cabinet, 19-inch cabinet or the cabinet used for the access network equipment. The OptiX OSN 1500 subrack can be installed against the wall. 2.2 Cabinet Configuration On the top of the ETSI cabinet, there are cabinet indicators and a DC power distribution unit (PDU). 2.3 Technical Specifications The specifications of the cabinet cover the dimensions, weight and number of allowed subracks.
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2 Cabinet
300-mm deep ETSI cabinet 600-mm deep ETSI cabinet 19-inch cabinet Cabinet used for the access network equipment
H W D
1. Cabinet indicator
2. DC PDU
2.2.1 Cabinet Indicator The indicators on the ETSI cabinet are power supply indicators and alarm severity indicators. 2.2.2 DC PDU The DC PDU is on the top of the cabinet and used to supply power for the equipment. 2.2.3 Other Configuration
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2 Cabinet
Unlit
Lit
Unlit
Lit
Unlit
CAUTION
The cabinet indicators are driven by the subrack. The cabinet indicators can be lit only after the cables are correctly connected and the subrack is powered on.
2.2.2 DC PDU
The DC PDU is on the top of the cabinet and used to supply power for the equipment. Figure 2-2 shows the appearance of the DC PDU.
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2 Cabinet
2 3 4 5
3 2 OUTPUT
A
RTN1(+) RTN2(+) NEG1(-) NEG2(-)
B
ON OFF
32A
3 2 OUTPUT
ON OFF
32A 32A 20A 20A
INPUT
32A
20A
20A
1. Power terminal (A) 3. Power cable RTN2 (+) 5. Power cable NEG2 () 7. PGND
2. Power cable RTN1 (+) 4. Power cable NEG1 () 6. Power terminal (B) 8. Power switch
For the OptiX OSN 1500A, the power terminals at side A and side B supply power to the PIU boards at side A and side B of the subrack respectively. Table 2-2 shows the connections of the power terminals at side A and side B. For the OptiX OSN 1500B, the power terminals at sides A and B supply power to the PIU boards at the upper and lower subrack respectively. Table 2-2 Connection of power terminals at side A and side B Power Terminal at Side A 1 2 3 4 Corresponding Subrack and PIU Board The PIU board at side A of the first subrack The PIU board at side A of the second subrack The PIU board at side A of the third subrack The PIU board at side A of the fourth subrack Power Terminal at Side B 1 2 3 4 Corresponding Subrack and PIU Board The PIU board at side B of the first subrack The PIU board at side B of the second subrack The PIU board at side B of the third subrack The PIU board at side B of the fourth subrack
UPM
The UPM numbered GIE4805S can directly supply power to the OptiX OSN 1500. The UPM directly converts the 220 V mains supply to the 48 V DC power supply required by the
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communication equipment. If operators cannot provide the 48 V DC power supply for the equipment or require that the battery be used, the UPM can be applied.
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COA Fiber management spool, which is used to spool the redundant fibers inside the cabinet.
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3 Subrack
3
About This Chapter
Subrack
This chapter describes the cabinet in terms of the structure, capacity, slot allocation and technical specifications. 3.1 Structure The OptiX OSN 1500A subrack is of a one-layer structure. The subrack consists of the slot area for boards, power supply area, fan area and fiber routing area. The OptiX OSN 1500B subrack is of a two-layer structure. The subrack consists of the slot area for processing boards, slot area for interface boards, slot area for the auxiliary interface board, power supply area and fan area. 3.2 Capacity Both the OptiX OSN 1500A and the OptiX OSN 1500B have slots that can be divided into halfwidth slots. These slots have different service access capacities before and after the slot division. 3.3 Slot Allocation The OptiX OSN 1500A subrack has only one layer, where 12 slots are available before the division of slots. 3.4 Slot Allocation The OptiX OSN 1500B subrack has two layers. The upper layer of the subrack, where four slots are present, is the slot area for the interface boards and PIU boards. The lower layer of the subrack, where ten slots are available before the division of slots (including slots 4 and 5), is the slot area for the processing boards and auxiliary boards. 3.5 Technical Specifications The specifications of the subrack cover dimensions, weight and maximum power consumption.
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3 Subrack
3.1 Structure
The OptiX OSN 1500A subrack is of a one-layer structure. The subrack consists of the slot area for boards, power supply area, fan area and fiber routing area. The OptiX OSN 1500B subrack is of a two-layer structure. The subrack consists of the slot area for processing boards, slot area for interface boards, slot area for the auxiliary interface board, power supply area and fan area. Figure 3-1 shows the structure of the OptiX OSN 1500A subrack. Figure 3-1 Structure of the OptiX OSN 1500A subrack
2 3 4 6 5
H W D
Slot area for boards: This area is used to house the boards for the OptiX OSN 1500A. Fan area: This area is used to house one fan module, which dissipates heat generated by the equipment. Power supply area: This area is used to house two PIU boards, which are used to supply power for the equipment. Fiber routing area: This area is used to route fibers and cables in the subrack.
Figure 3-2 shows the structure of the OptiX OSN 1500B subrack.
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3 Subrack
4 4
H W
7 6
1. Slot area for interface boards 4. Slot area for processing boards 7. Mounting ear
2. Power supply area 5. Slot area for the auxiliary interface board
Slot area for interface boards: This area is used to house the tributary interface boards and Ethernet interface boards for the OptiX OSN 1500B. Slot area for processing boards: This area is used to house the line, tributary and Ethernet processing boards for the OptiX OSN 1500B. Fan area: This area is used to house one fan module, which dissipates heat generated by the equipment. Slot area for the auxiliary interface board: This area is used to house the auxiliary interface board, which provides alarm interfaces, orderwire phone interface, management and maintenance interface, and clock interface. Power supply area: This area is used to house two PIU boards, which are used to supply power for the equipment. Fiber routing area: This area is used to route fibers and cables in the subrack.
3.2 Capacity
Both the OptiX OSN 1500A and the OptiX OSN 1500B have slots that can be divided into halfwidth slots. These slots have different service access capacities before and after the slot division. In the OptiX OSN 1500A subrack, slots 12 and 13 can be divided into half-width slots. In the OptiX OSN 1500B subrack, slots 1113 can be divided into half-width slots. Figure 3-3 shows
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3 Subrack
the slot access capacity of the OptiX OSN 1500A. Figure 3-4 shows the slot access capacity of the OptiX OSN 1500B. In the OptiX OSN 1500A subrack, slots 12 and 13 can be divided into half-width slots.
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When slot 12 is divided, the two half-width slots are numbered slot 2 and slot 12. When slot 13 is divided, the two half-width slots are numbered slot 3 and slot 13. When slots 12 and 13 are not divided, the access capacity of each slot is 2.5 Gbit/s. When slots 12 and 13 are divided, the access capacity of each half-width slot is 1.25 Gbit/ s.
In the OptiX OSN 1500B subrack, slots 1113 can be divided into half-width slots.
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When slot 11 is divided, the two half-width slots are numbered slot 1 and slot 11. When slot 12 is divided, the two half-width slots are numbered slot 2 and slot 12. When slot 13 is divided, the two half-width slots are numbered slot 3 and slot 13. When slots 1113 are not divided, the access capacity of each slot is 2.5 Gbit/s. When slots 1113 are divided, the access capacity of each half-width slot is 1.25 Gbit/s.
3 Subrack
Figure 3-5 shows the slot layout of the OptiX OSN 1500A subrack. Figure 3-5 Slot layout of the OptiX OSN 1500A subrack
Slot 1 Slot 20 FAN Slot 12 Slot 13 Slot 4 Slot 5 CXL CXL Slot 11 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 EOW AUX
Slots 12 and 13 in the OptiX OSN 1500A subrack can be divided into two half-width slots. See Figure 3-6. Figure 3-6 Slot layout of the OptiX OSN 1500A subrack after the division of slots
Slot 1 Slot 20 FAN Slot 2 Slot 3 Slot 4 Slot 5 Slot 11 Slot 12 Slot 13 CXL CXL Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 EOW AUX
The slots in the OptiX OSN 1500A subrack are allocated as follows:
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Slots for integrated boards of the line, SCC, cross-connect and timing units: slots 45 Slots for processing boards before the division of slots: slots 69 and 1213 Slots for processing boards after the division of slots: slots 69, 1213, and 23 Slot for the orderwire board: slot 9 (also for the processing board) Slot for the auxiliary interface board: slot 10 Slots for PIU boards: slots 1 and 11 Slots for the fan board: slot 20
Mapping Relation Between Slots for Interface Boards and Slots for Processing Boards
Table 3-1 lists the mapping relation between slots for the interface boards and slots for the processing boards of the OptiX OSN 1500A. Table 3-1 Mapping relation between slots for the interface boards and slots for the processing boards of the OptiX OSN 1500A. Slots for Processing Boards Slot 12 Slots for Interface Boards Slots 6 and 7
3 Subrack
Table 3-2 CXL series boards and their valid slots of the OptiX OSN 1500A Board Q2CXL16, Q3CXL16 R1CXLL16 Full Name 1 x STM-16 integrated board of the SCC, cross-connect, timing and line units 1 x STM-16 integrated board of the SCC, cross-connect, timing and line units 1 x STM-4 integrated board of the SCC, cross-connect, timing and line units 1 x STM-4 integrated board of the SCC, cross-connect, timing and line units 2 x STM-4 integrated board of the SCC, cross-connect, timing and line units 4 x STM-4 integrated board of the SCC, cross-connect, timing and line units 1 x STM-1 integrated board of the SCC, cross-connect, timing and line units 1 x STM-1 integrated board of the SCC, cross-connect, timing and line units 2 x STM-1 integrated board of the SCC, cross-connect, timing and line units 4 x STM-1 integrated board of the SCC, cross-connect, timing and line units Valid Slots Slots 4 and 5
Slots 4 and 5
Q2CXL4, Q3CXL4
Slots 4 and 5
R1CXLL4
Slots 4 and 5
R1CXLD4
Slots 4 and 5
R1CXLQ4
Slots 4 and 5
Q2CXL1, Q3CXL1
Slots 4 and 5
R1CXLL1
Slots 4 and 5
R1CXLD1
Slots 4 and 5
R1CXLQ1
Slots 4 and 5
NOTE a: The CXL is a board that integrates the SCC, cross-connect, timing, and line units for the OptiX OSN 1500A. It is one physical board and can be housed in slot 4 or slot 5 on the subrack. On the T2000, the Q2/ Q3CXL is displayed as ECXL, GSCC and SL1/SL4/SL16, and the R1CXL is displayed as RCXL, GSCC and SLN/SLD41/SLQ41, seated in the logical slots 8081, 8283 and 45.
Table 3-3 lists the SDH processing boards and their valid slots of the OptiX OSN 1500A.
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Table 3-3 SDH processing boards and their valid slots of the OptiX OSN 1500A Board N1SL16, N2SL16, N3SL16 Full Name 1 x STM-16 optical interface board Valid Slots Valid slots when the crossconnect capacity is 20 Gbit/s: slots 12 and 13 If the cross-connect capacity is 15 Gbit/s, these slots are unavailable. N1SL16A, N2SL16A, N3SL16A 1 x STM-16 optical interface board Valid slots when the crossconnect capacity is 20 Gbit/s: slots 12 and 13. If the cross-connect capacity is 15 Gbit/s, these slots are unavailable. N1SF16 1 x STM-16 optical interface board (with FEC) Valid slots when the crossconnect capacity is 20 Gbit/s: slots 12 and 13 If the cross-connect capacity is 15 Gbit/s, these slots are unavailable. N1SLQ4, N2SLQ4, N1SLQ4A 4 x STM-4 optical interface board Valid slots when the crossconnect capacity is 20 Gbit/s: slots 12 and 13 If the cross-connect capacity is 15 Gbit/s, these slots are unavailable. N1SLD4, N1SLD4A, N2SLD4 R1SLD4 2 x STM-4 optical interface board Slots 12 and 13
Valid slots when the crossconnect capacity is 20 Gbit/s: slots 23, 69, and 1213 Valid slots when the crossconnect capacity is 15 Gbit/s: slots 1213
Slots 12 and 13 Valid slots when the crossconnect capacity is 20 Gbit/s: slot 2-3, 6-9, 12-13 Valid slots when the crossconnect capacity is 15 Gbit/s: slot 2, 6-8, 12-13
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Board N1SLT1
Valid Slots Valid slots when the crossconnect capacity is 20 Gbit/s: slots 12 and 13 If the cross-connect capacity is 15 Gbit/s, these slots are unavailable.
Valid slots when the crossconnect capacity is 20 Gbit/s: slot 2-3, 6-9, 12-13 Valid slots when the crossconnect capacity is 15 Gbit/s: slot 2, 6-8, 12-13
Slots 12 and 13 Valid slots when the crossconnect capacity is 20 Gbit/s: slot 2-3, 6-9, 12-13 Valid slots when the crossconnect capacity is 15 Gbit/s: slot 2, 6-8, 12-13
N1SEP1
Slots 12 and 13
Table 3-4 lists the PDH processing boards and their valid slots of the OptiX OSN 1500A. Table 3-4 PDH processing boards and their valid slots of the OptiX OSN 1500A Board N1PL3A (not used with the interface board) N2PL3A (not used with the interface board) R1PD1(A/B) Full Name 3 x E3/T3 processing board Valid Slots Slots 12 and 13
Slots 12 and 13
Slots 2 and 12
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Full Name 32 x E1 75-ohm/120-ohm processing board (half-width ) 16 x E1 75-ohm/120-ohm processing board (half-width)
Valid Slots Slots 2 and 12 Valid slots when the crossconnect capacity is 20 Gbit/s: slot 6-9 Valid slots when the crossconnect capacity is 15 Gbit/s: slot 6-8
N1DXA
Slots 12 and 13
Table 3-5 lists the interface boards and their valid slots of the OptiX OSN 1500A. Table 3-5 Interface Boards and their valid slots of the OptiX OSN 1500A Board R1L75S R1L12S Full Name 16 x EI 75-ohm interface board (half-width) 16 x E1 120-ohm interface board (half-width) Valid Slots Slots 6 and 7 Slots 6 and 7
Table 3-6 lists the data processing boards and their valid slots of the OptiX OSN 1500A. Table 3-6 Data processing boards and their valid slots of the OptiX OSN 1500A Board N1EMS4 Full Name 4 x GE Ethernet processing board with Lanswitch Valid Slots Valid slots when the crossconnect capacity is 20 Gbit/s: slot 12-13 (2.5 Gbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s) N2EGS2 2 x GE Ethernet processing board with Lanswitch Valid slots when the crossconnect capacity is 20 Gbit/s: slot 12-13 (2.5 Gbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s)
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Board N1EGS4
Valid Slots Valid slots when the crossconnect capacity is 20 Gbit/s: slot 12-13 (2.5 Gbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s)
N3EGS4
Valid slots when the crossconnect capacity is 20 Gbit/s: slot 12-13 (2.5 Gbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s)
N2EGS4A
Valid slots when the crossconnect capacity is 20 Gbit/s: slot 12-13 (2.5 Gbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s)
N1EGT2
Valid slots when the crossconnect capacity is 20 Gbit/s: slot 12-13 (2.5 Gbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s)
4 x FE Ethernet processing board with Lanswitch 4 x FE Ethernet processing board with Lanswitch 4 x FE Ethernet transparent transmission board (half-width)
Slots 12 and 13 Slots 12 and 13 (1.25 Gbit/s) Valid slots when the crossconnect capacity is 20 Gbit/s: slot 23, 69 and 1213 (622 Mbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 2, 68 and 1213 (622 Mbit/s)
8 x FE Ethernet transparent transmission board 8 x FE transparent transmission board (interfaces are available on the front panel)
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Board N2EGR2
Valid Slots Valid slots when the crossconnect capacity is 20 Gbit/s: slot 12-13 (2.5 Gbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s)
Valid slots when the crossconnect capacity is 20 Gbit/s: slot 12-13 (2.5 Gbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s)
1 x STM-4 ATM processing board 4 x STM-1 ATM processing board 1 x STM-4 IMA processing board 4 x STM-1 IMA processing board 4-channel multiservice (SAN or video service) transparent transmission board
Slots 12 and 13 (1.25 Gbit/s) Slots 12 and 13 (1.25 Gbit/s) Slots 12 and 13 (1.25 Gbit/s) Slots 12 and 13 (1.25 Gbit/s) Valid slots when the crossconnect capacity is 20 Gbit/s: slot 12-13 (2.5 Gbit/s) Valid slots when the crossconnect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s)
Table 3-7 lists the WDM boards and their valid slots of the OptiX OSN 1500A. Table 3-7 WDM boards and their valid slots of the OptiX OSN 1500A Board N1LWX TN11OBU1 N1FIB N1MR2A N1MR2B TN11MR2 Full Name Arbitrary rate access board Optical booster amplifier board Filter isolating board Arbitrary two-wavelength add/ drop board (processing board) Arbitrary two-wavelength add/ drop board (half-width) 2-channel optical add/drop multiplexing board
Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd
Valid Slots Slots 12 and 13 Slots 12 and 13 Slots 12 and 13 Slots 12 and 13 slot 2-3, 69 and 1213 (622 Mbit/s) Slots 12 and 13
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Full Name 4-channel optical add/drop multiplexing board 2-channel CWDM optical add/ drop multiplexing board 4-channel CWDM optical add/ drop multiplexing board
Table 3-8 lists the optical booster amplifier boards and their valid slots of the OptiX OSN 1500A. Table 3-8 Optical booster amplifier boards and their valid slots of the OptiX OSN 1500A Board N1BA2 N1BPA, N2BPA 61COA, 62COA, N1COA ROP Full Name 2-channel optical booster amplifier board 1-channel amplifier and 1channel preamplifier board COA board Single wavelength long-haul board (remote pumping) Valid Slots Slots 12 and 13 Slots 12 and 13 Slots 101 and 102 Slot 103 (external)
Table 3-9 lists the auxiliary boards and their valid slots of the OptiX OSN 1500A. Table 3-9 Auxiliary boards and their valid slots of the OptiX OSN 1500A Board R1AMU R1AUX R2AUX R1PIUA R1FAN R1EOW UPMa Full Name Orderwire processing or alarm concatenation board System auxiliary processing unit System auxiliary processing unit PIU board Fan board Orderwire communication board Uninterruptable power module Valid Slots Slot 9 Slot 10 Slot 10 Slots 1 and 11 Slot 20 Slot 9 Slot 50
a: The UPM is in case shape. On the T2000, it is displayed as CAU board seated in the logical slot 50.
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PIU
EOW AUX
Slots 11-13 in the OptiX OSN 1500B subrack can be divided. As shown in Figure 3-8, the divided slots are in the dashed area. The slots in the left portion of the original slots are slots 1-3, and the slots in the right portion of the original slots are slots 11-13. Figure 3-8 Slot layout of the OptiX OSN 1500B subrack (after the division of slots)
Slot 14 Slot 15 Slot 16 Slot 17 Slot 1 Slot 20 FAN Slot 2 Slot 3 Slot 4 Slot 5 Slot 11 Slot 12 Slot 13 CXL CXL Slot 18 PIU
PIU
EOW AUX
The slots in the OptiX OSN 1500B subrack are allocated as follows:
l l l l l l l
Slots for integrated boards of the line, SCC, cross-connect and timing units: slots 4-5 Slots for processing boards before the division of slots: slots 6-9 and 11-13 Slots for processing boards after the division of slots: slots 1-9 and 11-13 Slots for the interface boards: slots 14-17 Slot for the orderwire board: slot 9 (also for the processing board) Slot for the auxiliary interface board: slot 10 Slots for PIU boards: slots 18 and 19
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Mapping Relation Between Slots for Interface Boards and Slots for Processing Boards
Table 3-10 lists the mapping relation between slots for the interface boards and slots for the processing boards of the OptiX OSN 1500B. Table 3-10 Mapping relation between slots for the interface boards and slots for the processing boards of the OptiX OSN 1500B. Slots for Processing Boards Slot 2 Slot 7 Slot 12 Slots for Interface Boards Slot 14 Slot 15 Slots 14 and 15 Slots for Processing Boards Slot 3 Slot 8 Slot 13 Slots for Interface Boards Slot 16 Slot 17 Slots 16 and 17
The corresponding interface boards of the PD3, PL3, SEP, and SPQ4 can be housed only in slots of even numbers. For the OptiX OSN 1500B, the boards housed in slots 12 and 7 share the same interface board housed in slot 15, and the boards housed in slots 13 and 8 share the same interface board housed in slot 17. Therefore, when you configure the boards, ensure the following:
l
If slot 12 houses the N1EMS4 (used with an interface board) or R1PD1, slot 7 cannot house any board used with an interface board. If slot 13 houses the N1EMS4 (used with an interface board) or R1PD1, slot 8 cannot house any board used with an interface board.
Valid Slots Slots 4 and 5 Slots 4 and 5 Slots 4 and 5 Slots 4 and 5
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Full Name 2 x STM-4 integrated board of the SCC, crossconnect, timing and line units 4 x STM-4 integrated board of the SCC, crossconnect, timing and line units 1 x STM-1 integrated board of the SCC, crossconnect, timing and line units 1 x STM-1 integrated board of the SCC, crossconnect, timing and line units 2 x STM-1 integrated board of the SCC, crossconnect, timing and line units 4 x STM-1 integrated board of the SCC, crossconnect, timing and line units
Valid Slots Slots 4 and 5 Slots 4 and 5 Slots 4 and 5 Slots 4 and 5 Slots 4 and 5 Slots 4 and 5
NOTE a: The CXL is a board that integrates the SCC, cross-connect, timing, and line units for the OptiX OSN 1500B. It is one physical board and can be housed in slot 4 or slot 5 on the subrack. On the T2000, the Q2/ Q3CXL is displayed as ECXL, GSCC and SL1/SL4/SL16, and the R1CXL is displayed as RCXL, GSCC and SLN/SLD41/SLQ41, seated in the logical slots 8081, 8283 and 45.
Table 3-12 lists the SDH processing boards and their valid slots for the OptiX OSN 1500B. Table 3-12 SDH processing boards and their valid slots for the OptiX OSN 1500B Board N1SL16, N2SL16, N3SL16 Full Name 1 x STM-16 optical interface board Valid Slots Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 If the cross-connect capacity is 15 Gbit/s, these slots are unavailable. N1SL16A, N2SL16A, N3SL16A 1 x STM-16 optical interface board Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 If the cross-connect capacity is 15 Gbit/s, these slots are unavailable. 1 x STM-16 outband optical interface board (with FEC) Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 If the cross-connect capacity is 15 Gbit/s, these slots are unavailable.
N1SF16
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Valid Slots Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 If the cross-connect capacity is 15 Gbit/s, these slots are unavailable.
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 Valid slots if the cross-connect capacity is 15 Gbit/s: slots 12-13
Slots 11-13 Valid slots if the cross-connect capacity is 20 Gbit/s: slots 1-3, 11-13 (up to two optical interfaces can be configured), slots 6-9 (one optical interfaces can be configured). Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (one optical interfaces can be configured), slots 12-13 (up to two optical interfaces can be configured).
R1SL4
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 1-3, 6-9, 11-13 Valid slots if the cross-connect capacity is 15 Gbit/s: slots 6-8, 11-13
N1SLT1
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 If the cross-connect capacity is 15 Gbit/s, these slots are unavailable.
N2SLO1
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 Valid slots if the cross-connect capacity is 15 Gbit/s: slots 12-13
Slots 11-13
Slots 11-13
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Board R1SLQ1
Valid Slots Valid slots if the cross-connect capacity is 20 Gbit/s: slots 1-3, 6-9, 11-13 Valid slots if the cross-connect capacity is 15 Gbit/s: slots 6-8, 11-13
R1SL1
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 1-3, 6-9, 11-13 Valid slots if the cross-connect capacity is 15 Gbit/s: slots 6-8, 11-13
N1SEP (used with the interface board)a N1SEP1 (not used with the interface board)a
a: The SEP1 board is displayed as the SEP1 or SEP on the T2000, depending on the interfacing mode of the board. When the SEP1 provides interfaces on the front panel, it is displayed as the SEP1 on the T2000. When the SEP1 is used with an interface board, it is displayed as the SEP on the T2000.
Table 3-13 lists the PDH processing boards and their valid slots for the OptiX OSN 1500B. Table 3-13 PDH processing boards and their valid slots for the OptiX OSN 1500B Board N1SPQ4 N2SPQ4 (used with the interface board) R1PL1(A/B) (interfaces available on the front panel) N2PQ3 N1PD3 N2PD3 N2PL3 Full Name 4 x E4/STM-1 processing board 4 x E4/STM-1 processing board 16 x E1 75-ohm/120-ohm interface and processing board 12 x E3/T3 processing board 6 x E3/T3 processing board 6 x E3/T3 processing board 3 x E3/T3 processing board Valid Slots Slots 12 and 13 Slots 12 and 13 Slots 69
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Board N1PL3A (not used with the interface board) N2PL3A (not used with the interface board) N1PL3 N1PQ1(A/B) N2PQ1(A/B) R1PD1(A/B)
Slots 1113
3 x E3/T3 processing board 63 x E1 75-ohm/120-ohm processing board 63 x E1 75-ohm/120-ohm processing board 32 x E1 75-ohm/120-ohm processing board (half-width)
Slots 12 and 13 Slots 1113 Slots 1113 Valid slots if the cross-connect capacity is 20 Gbit/s: slots 1-3, 6-8, 11-13 Valid slots if the cross-connect capacity is 15 Gbit/s: slots 6-8, 11-13
R2PD1(A/B)
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 1-3, 6-8, 11-13 Valid slots if the cross-connect capacity is 15 Gbit/s: slots 6-8, 11-13
63 x E1/T1 processing board DDN service access and convergence board DDN service convergence and processing board
Table 3-14 lists the interface boards or protection switching boards and their valid slots for the OptiX OSN 1500B. Table 3-14 Interface/protection switching boards and their valid slots for the OptiX OSN 1500B Board N1EU08 N1OU08 N2OU08 Full Name 8 x STM-1 (e) electrical interface board 8 x STM-1 optical interface board 8 x STM-1 optical interface board Valid Slots Slots 14 and 16 Slots 14 and 16 Slots 14 and 16
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Board N1EU04 N1MU04 N1C34S N1D34S N1D75S N1D12S N1D12B N1DM12 N1TSB8 N1TSB4 N1ETF8 N1EFF8 N1ETS8
Full Name 4 x STM-1 (e) electrical interface board 4 x E4/STM-1 interface board 3 x 34M/45M electrical interface switching board 6 x 34M/45M electrical interface switching board 32 x E1/T1 75-ohm electrical interface switching board 32 x E1/T1 120-ohm electrical interface switching board 32 x E1/T1 120-ohm electrical interface board DDN service interface board 8-channel electrical interface switching board 4-channel electrical interface switching board 8 x FE Ethernet electrical interface board 8-channel Ethernet optical interface board 8 x 10/100M Ethernet twisted pair interface switching board
Valid Slots Slots 14 and 16 Slots 14 and 16 Slots 14 and 16 Slots 1417 Slots 14-17 Slots 14-17 Slots 14-17 Slots 14-17 Slots 14 and 15 Slot 14 Slots 1417 Slots 1417 Slots 14 and 16
Table 3-15 lists the data processing boards and their valid slots for the OptiX OSN 1500B. Table 3-15 Data processing boards and their valid slots for the OptiX OSN 1500B Board N1EMS4 (used with the interface board) Full Name 4 x GE and 16 x FE Ethernet processing board with Lanswitch Valid Slots Valid slots if the cross-connect capacity is 20 Gbit/s: slots 12-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slots 12-13 (1.25 Gbit/s)
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Valid Slots Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slots 12-13 (1.25 Gbit/s)
N1EGS4
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slots 12-13 (1.25 Gbit/s)
N3EGS4
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slots 12-13 (1.25 Gbit/s)
N2EGS4A
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slots 12-13 (1.25 Gbit/s)
N2EGS2
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slots 11 (622 Mbit/s), 12-13 (1.25 Gbit/s)
N1EGT2
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slots 11 (622 Mbit/s), 12-13 (1.25 Gbit/s)
N1EFS4
Slots 1113
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Board N2EFS4
Valid Slots Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (1.25 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slots 12-13 (1.25 Gbit/s)
N1EFS0 (used with the interface board) N2EFS0 (used with the interface board) N4EFS0 (used with the interface board)
8 x FE Ethernet processing board with Lanswitch 8 x FE Ethernet processing board with Lanswitch 8 x FE Ethernet processing board with Lanswitch
Slots 1213 (622 Mbit/s) Slots 1213 (1.25 Gbit/s) Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (1.25 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slots 12-13 (1.25 Gbit/s)
N1EFT8 (not used with the interface board) N1EFT8 (used with the interface board) N1EFT8A (interfaces available on the front panel) N2EGR2
8 x 10M/100M Ethernet transparent transmission board 16 x 10M/100M Ethernet transparent transmission board 8 x FE transparent transmission board 2 x GE Ethernet ring processing board
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slot 12-13 (1.25 Gbit/s)
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 12-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 12-13 (1.25 Gbit/s)
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slots 12-13 (1.25 Gbit/s)
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Valid Slots Valid slots if the cross-connect capacity is 20 Gbit/s: slots 1-3, 6-9, 11-13 (622 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slots 6-8, 11-13 (622 Gbit/s)
8-channel Ethernet optical interface board 8 x 10/100M Ethernet twisted pair interface switching board 4-channel multiservice transparent transmission board
Slots 1417 Slots 14 and 16 Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (2.5 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slots 11 (622 Mbit/s), 12-13 (1.25 Gbit/s)
N1ADQ1
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (1.25 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slots 12-13 (1.25 Gbit/s)
N1ADL4
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (1.25 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slot 11 (622 Mbit/s), slots 12-13 (1.25 Gbit/s)
N1IDQ1
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (1.25 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slots 12-13 (1.25 Gbit/s)
N1IDL4
Valid slots if the cross-connect capacity is 20 Gbit/s: slots 11-13 (1.25 Gbit/s) Valid slots if the cross-connect capacity is 15 Gbit/s: slots 12-13 (1.25 Gbit/s)
Table 3-16 lists the WDM boards and their valid slots for the OptiX OSN 1500B.
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Table 3-16 WDM boards and their valid slots for the OptiX OSN 1500B Board N1LWX N1MR2A N1MR2B N1MR2C TN11MR2 TN11MR4 TN11CMR2 TN11CMR4 Full Name Arbitrary rate access board Arbitrary two-wavelength add/ drop board Arbitrary two-wavelength add/ drop board (half-width) Arbitrary two-wavelength add/ drop board 2-channel optical add/drop multiplexing board 4-channel optical add/drop multiplexing board 2-channel CWDM optical add/ drop multiplexing board 4-channel CWDM optical add/ drop multiplexing board Valid Slots Slots 1113 Slots 1113 Slots 13, 69 and 1113 Slots 1417 Slots 1113 Slots 1113 Slots 1113 Slots 1113
Table 3-17 lists the optical booster amplifier boards and their valid slots for the OptiX OSN 1500B. Table 3-17 Optical booster amplifier boards and their valid slots for the OptiX OSN 1500B Board N1BA2 N1BPA, N2BPA TN11OBU1 N1FIB 61COA, 62COA, N1COA ROP Full Name 2-channel optical booster amplifier board Optical booster preamplifier board Optical booster amplifier board Filter isolating board COA board Single wavelength long-haul board (remote pumping) Valid Slots Slots 1113 Slots 1113 Slots 1113 Slots 12 and 13 Slots 101102 Slot 103 (external)
Table 3-18 lists the auxiliary boards and their valid slots for the OptiX OSN 1500B.
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Table 3-18 Auxiliary boards and their valid slots for the OptiX OSN 1500B Board R1AMU R1AUX R2AUX R1FAN R1EOW R1PIU UPMa Full Name Orderwire processing or alarm concatenation board System auxiliary processing unit System auxiliary interface board Fan board Orderwire communication board PIU board Uninterruptable power module Valid Slots Slot 9 Slot 10 Slot 10 Slot 20 Slot 9 Slots 1819 Slot 50
a: The UPM is in case shape. On the T2000, it is displayed as CAU board seated in the logical slot 50.
Table 3-20 lists power consumption of the OptiX OSN 1500A subrack. Table 3-20 Maximum power consumption of the OptiX OSN 1500A subrack Subrack Type OptiX OSN 1500A general subrack Maximum Power Consumption 200 W Fuse Capacity 20 A
Table 3-21 lists the technical specifications of the OptiX OSN 1500B subrack.
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Table 3-21 Technical specifications of the OptiX OSN 1500B subrack Dimensions (mm) 444 (W) x 263 (D) x 221 (H) Weight (kg) 9 (the backplane, fans and two PIU boards included)
Table 3-22 lists power consumption of the OptiX OSN 1500B subrack. Table 3-22 Maximum power consumption of the OptiX OSN 1500B subrack Subrack Type OptiX OSN 1500B general subrack Maximum Power Consumption 280 W Fuse Capacity 20 A
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4
About This Chapter
This chapter describes the appearance, barcode and classification of boards used for the OptiX OSN systems. 4.1 Appearance and Dimensions of Boards Different boards have different appearance and dimensions. 4.2 Description of the Barcode on the Board The barcode on the front panel of the board indicates the board version, name and board features. 4.3 Board Classification By function, the boards can be classified into SDH processing boards, PDH processing boards, data processing boards, WDM processing boards and auxiliary boards.
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Integrated board of the SCC, cross-connect and line units (CXL) 262.05 220 25.4
Note: The figure in the right cell illustrates the three dimensions. The height and width are measured for the front panel and the depth is measured for the printed circuit board (PCB).
CAUTION
Wear the anti-static wrist strap when holding the board with hands. Make sure that the anti-static wrist strap is well grounded. Otherwise, the static discharge may cause damage to the board.
DANGER
Avoid direct eye exposure to laser beams launched from the optical interface board or optical interfaces. Otherwise, damage may be caused to the eyes.
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CAUTION
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Do not directly insert the attenuators into the level optical modules. If the attenuators are required, use the attenautors at the ODF side. If a board requires an attenuator, insert the attenuator in the IN interface instead of the OUT interface. When performing the loopback, use attenuators to prevent damage to the optical modules.
16-character manufacturing code + board version + board name + board feature code 20-character manufacturing code + board version + board name + board feature code
The barcode is stuck on the front panel of a board. Figure 4-1 shows a barcode with 16-character manufacturing code. Figure 4-1 Barcode of a board
Bar code
0364401055000015 -SSN3SL16A01
Last 6-character serial code of BOM Internal code Board version Board name 5 Board feature code
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For details on the board feature code, see the section that describes the board feature code for each board.
Board N2SL16 N3SL16 N1SL16A N2SL16A N3SL16A N1SF16 N1SL4(A) N2SL4 R1SL4 N1SLQ4(A) N2SLQ4 N1SLD4(A) N2SLD4 R1SLD4 N1SLT1 N1SLQ1(A) N2SLQ1 R1SLQ1 N1SL1(A) N2SL1 R1SL1 N1SEP1 N2SLO1
Full Name 1 x STM-16 optical interface board 1 x STM-16 optical interface board 1 x STM-16 optical interface board 1 x STM-16 optical interface board 1 x STM-16 optical interface board 1 x STM-16 optical interface board (with FEC) 1 x STM-4 optical interface board 1 x STM-4 optical interface board 1 x STM-4 optical interface board (half-width) 1 x STM-4 optical interface board 4 x STM-4 optical interface board 2 x STM-4 optical interface board 2 x STM-4 optical interface board 2 x STM-4 optical interface board (half-width) 12 x STM-1 optical interface board 4 x STM-1 optical interface board 4 x STM-1 optical interface board 4 x STM-1 optical interface board (half-width) 1 x STM-1 optical interface board 1 x STM-1 optical interface board 1 x STM-1 optical interface board (half-width) 2 x STM-1 line processing board when interfaces are available on the front panel 8 x STM-1 optical interface board
Table 4-3 lists the SDH processing boards supported by the OptiX OSN 1500B. Table 4-3 SDH processing boards for the OptiX OSN 1500B Board N1SL16 N2SL16
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Full Name 1 x STM-16 optical interface board 1 x STM-16 optical interface board
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Board N3SL16 N1SL16A N2SL16A N3SL16A N1SF16 N1SL4(A) N2SL4 R1SL4 N1SLQ4(A) N2SLQ4 N1SLD4(A) N2SLD4 R1SLD4 N1SLT1 N1SLQ1(A) N2SLQ1 R1SLQ1 N1SL1(A) N2SL1 R1SL1 N1SEP1
Full Name 1 x STM-16 optical interface board 1 x STM-16 optical interface board 1 x STM-16 optical interface board 1 x STM-16 optical interface board 1 x STM-16 optical interface board (with FEC) 1 x STM-4 optical interface board 1 x STM-4 optical interface board 1 x STM-4 optical interface board (half-width) 4 x STM-4 optical interface board 4 x STM-4 optical interface board 2 x STM-4 optical interface board 2 x STM-4 optical interface board 2 x STM-4 optical interface board (half-width) 12 x STM-1 optical interface board 4 x STM-1 optical interface board 4 x STM-1 optical interface board 4 x STM-1 optical interface board (half-width) 1 x STM-1 optical interface board 1 x STM-1 optical interface board 1 x STM-1 optical interface board (half-width) 2 x STM-1 line processing board when interfaces are available on the front panel 8 x STM-1 line processing board when used with an interface board
N2SLO1
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Table 4-4 PDH processing boards for the OptiX OSN 1500A Board R1PL1 Full Name 16 x E1 processing board Board N1PL3A Full Name 3 x E3/T3 processing board (interfaces available on the front panel) 3 x E3/T3 processing board (interfaces available on the front panel) DDN service convergence board
R1PD1
32 x E1 processing board
N2PL3A
R2PD1
32 x E1 processing board
N1DXA
Table 4-5 lists the PDH processing boards supported by the OptiX OSN 1500B. Table 4-5 PDH processing boards for the OptiX OSN 1500B Board R1PL1 Full Name 16 x E1 processing board Board N2PL3A Full Name 3 x E3/T3 processing board (interfaces available on the front panel) 6 x E3/T3 processing board 6 x E3/T3 processing board 12 x E3/T3 processing board DDN service access and convergence board DDN service convergence board 4 x E4/STM-1 electrical processing board 4 x E4/STM-1 electrical processing board -
32 x E1 processing board 32 x E1 processing board 63 x E1 processing board 63 x E1 processing board 63 x E1/T1 processing board 3 x E3/T3 processing board 3 x E3/T3 processing board 3 x E3/T3 processing board (interfaces available on the front panel)
Table 4-6 Data processing boards for the OptiX OSN 1500A Board N1EFT4 Full Name 4 x FE Ethernet transparent transmission board (halfwidth) 8 x FE Ethernet transparent transmission board 4 x GE Ethernet convergence board 8 x FE Ethernet transparent transmission board 2 x GE Ethernet transparent transmission board 4 x FE Ethernet processing board with Lanswitch 4 x FE Ethernet processing board with Lanswitch 2 x GE Ethernet processing board with Lanswitch 4 x GE Ethernet transparent transmission and convergence board Board N1EGS4 Full Name 4 x GE Ethernet convergence board 4 x GE Ethernet convergence board 2 x GE Ethernet ring processing board 4 x FE and 1 x GE Ethernet ring processing board 1 x STM-4 ATM processing board 1 x STM-4 ATM processing board 1 x STM-4 ATM processing board 4 x STM-1 ATM processing board 4-port multi-service transparent transmission board
Table 4-7 lists the data processing boards supported by the OptiX OSN 1500B. Table 4-7 Data processing boards for the OptiX OSN 1500B Board N1EFT4 Full Name 4 x FE Ethernet transparent transmission board (halfwidth) 8 x FE or 16 x FE Ethernet transparent transmission board 8 x FE Ethernet transparent transmission board 4 x GE Ethernet convergence board 2 x GE Ethernet transparent transmission board Board N1EMS4 Full Name 4 x GE and 16 x FE Ethernet transparent transmission and convergence board 4 x GE Ethernet convergence board 4 x GE Ethernet convergence board 2 x GE Ethernet ring processing board 12 x FE and 1 x GE Ethernet ring processing board
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Full Name 8-port Fast Ethernet processing board with Lanswitch 8 x FE Ethernet processing board with Lanswitch 8 x FE Ethernet processing board with Lanswitch 4 x FE Ethernet processing board with Lanswitch 4 x FE Ethernet processing board with Lanswitch 2 x GE Ethernet processing board with Lanswitch
Full Name 1 x STM-4 ATM processing board 1 x STM-4 ATM processing board 1 x STM-4 ATM processing board 4 x STM-1 ATM processing board 4-port multi-service transparent transmission board -
Table 4-9 lists the interface boards and switching boards supported by the OptiX OSN 1500B. Table 4-9 Interface boards and switching boards supported by the OptiX OSN 1500B Board N1EU08 Full Name 8 x STM-1 electrical interface board 8 x STM-1 optical interface board (LC) 8 x STM-1 optical interface board (SC) Board N1D12S Full Name 32 x E1/T1 120-ohm electrical interface switching board 32 x E1/T1 120-ohm electrical interface board 8 x 100M Ethernet optical interface board
N1OU08 N2OU08
N1D12B N1EFF8
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Full Name 32 x E1/T1 75-ohm electrical interface switching board 4 x STM-1 electrical interface board 6 x E3/T3 electrical interface switching board 3 x E3/T3 electrical interface switching board 4 x STM-1 electrical interface board
Full Name 8 x 100M Ethernet twisted pair interface board 8 x 10/100M Ethernet twisted pair interface switching board DDN service interface board 4-channel electrical interface switching board 8-channel electrical interface switching board
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Table 4-11 Auxiliary boards supported by the OptiX OSN 1500A and the OptiX OSN 1500B Board R1EOW R1AMU Full Name Orderwire phone processing board Orderwire processing or alarm concatenation board Board R1AUX/ R2AUX R1FAN Full Name System auxiliary interface board Fan board
Table 4-13 lists the optical add/drop multiplexing boards supported by the OptiX OSN 1500B. Table 4-13 Optical add/drop multiplexing boards supported by the OptiX OSN 1500B Board TN11CMR2 TN11CMR4 TN11MR2 Full Name 2-channel optical add/drop multiplexing board 4-channel optical add/drop multiplexing board 2-channel optical add/drop multiplexing board Board N1MR2B N1MR2C N1LWX Full Name 2-channel optical add/drop multiplexing board 2-channel optical add/drop multiplexing board Arbitrary bit rate wavelength conversion board
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Full Name 42-channel optical add/drop multiplexing board 2-channel optical add/drop multiplexing board
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5
About This Chapter
This chapter describes the SDH processing boards at the STM-1, STM-4, and STM-16 levels. 5.1 SL1 This section describes the SL1, a 1 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.2 SL1A This section describes the SL1A, a 1 x STM-1 optical interface board, in terms of version, function, principle, front panel and technical specifications. 5.3 SLQ1 This section describes the SLQ1, a 4 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and parameters. 5.4 SLQ1A This section describes the SLQ1A, a 4 x STM-1 optical interface board, in terms of version, function, principle, front panel and technical specifications. 5.5 SLO1 This section describes the SLO1, an 8 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and parameters. 5.6 SLT1 This section describes the SLT1, a 12 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.7 SEP1 This section describes the SEP1 board, in terms of the version, function, working principle, front panel, and specifications. 5.8 SL4 This section describes the SL4, a 1 x STM-4 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.9 SL4A This section describes the SL4A, a 1 x STM-4 optical interface board, in terms of version, function, principle, front panel and technical specifications.
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5.10 SLD4 This section describes the SLD4, a 2 x STM-4 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.11 SLD4A This section describes the SLD4A, a 2 x STM-4 optical interface board, in terms of version, function, principle, front panel and technical specifications. 5.12 SLQ4 This section describes the SLQ4, a 4 x STM-4 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.13 SLQ4A This section describes the SLQ4A, a 4 x STM-4 optical interface board, in terms of version, function, principle, front panel and technical specifications. 5.14 SL16 This section describes the SL16, a 1 x STM-16 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.15 SL16A This section describes the SL16A, a 1 x STM-16 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.16 SF16 This section describes the SF16, a 1 x STM-16 optical interface board with the out-band FEC function, in terms of the version, function, working principle, front panel and specifications.
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5.1 SL1
This section describes the SL1, a 1 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.1.1 Version Description The SL1 board has three versions: R1, N1 and N2. The difference among the three versions lies in the support for the TCM function. The R1SL1 is a 1 x STM-1 optical interface board, which is housed in a divided slot in a subrack. 5.1.2 Function and Feature The SL1 is used to transmit and receive STM-1 optical signals, to perform O/E conversion for the STM-1 optical signals, to extract or insert overhead bytes, and to generate alarm signals. 5.1.3 Working Principle and Signal Flow The SL1 board consists of the O/E conversion module, CDR module, SDH overhead processing module, RST and so on. 5.1.4 Front Panel On the front panel of the N1L1/N2SL1, there are indicators, interfaces, barcode and laser safety class label. On the front panel of the R1SL1, there are indicators, interfaces and barcode. 5.1.5 Valid Slots The slots valid for the SL1 vary with the version of the board. 5.1.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SL1 indicates the optical interface type. 5.1.7 Board Configuration Reference You can use the T2000 to set parameters for the SL1. 5.1.8 Technical Specifications The technical specifications of the SL1 cover the optical interface specifications, board dimensions, weight and power consumption.
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Item Replaceability
NOTE
The N2SL1 board supports the TCM function, which are not supported by the N1SL1 or R1SL1 board. For this reason, when configuring MSP and SNCP, you cannot configure the N1SL1 or R1SL1 board as the protection board if the working board is N2SL1 configured with the TCM service . Otherwise, the service may be interrupted due to the switching operation.
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SL1 Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
Reference clock
Cross-connect unit
155Mbit/s 155Mbit/s
O/E O/E
S P I
155Mbit/s
CDR
155Mbit/s
K1 and K2 insertion/extration
155Mbit/s
K1 and K2
Cross-connect unit
....
155Mbit/s 155Mbit/s
....
155Mbit/s
Cross-connect unit A
RST
155Mbit/s 155Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
MST: multiplex section termination MSA: multiplex section adaptation CDR: clock and data recovery
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In the receive direction, the module converts the received optical signals into electrical signals. In the transmit direction, the module converts the electrical signals into SDH optical signals, and then sends optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides function to shut down the laser.
CDR Module
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RST
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In the receive direction, MST performs BIP-24 errored block count, multiplex sectionremote error indication (MS_REI) recovery, multiplex section-remote defect indication (MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. MST provides extraction or insertion of K1 byte and K2 byte. In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In the transmit direction, MST it performs administration unit group (AUG) assembly, AU-4 pointer generation, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
MST
MSA
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units.
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Controls the laser. Realizes the pass-through of orderwire and embedded control channel (ECC) bytes between the paired slots constituting the add/ drop multiplexer (ADM) when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
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DC/DC Converter
It provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
OUT
IN
SL1
Figure 5-3 shows the appearance of the front panel of the R1SL1.
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SL1
STAT ACT PROG SRV
OUT IN
SL1
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SL1. Table 5-3 lists the type and usage of the optical interfaces. Table 5-3 Optical interfaces of the SL1 Interfaces on the Front Panel IN OUT Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
The R1SL1 can be housed in any of slots 23, 69 and 1213 in the OptiX OSN 1500A subrack. The N1SL1 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The N2SL1 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The R1SL1 can be housed in any of slots 13, 69 and 1113 in the OptiX OSN 1500B subrack. The N1SL1 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. The N2SL1 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack.
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J0 J1 C2
Table 5-5 Specifications of the optical interfaces of the SL1 Item Nominal bit rate Line code Optical interface type Optical source type Working wavelengt h (nm) Launched optical power (dBm) Receiver sensitivity (dBm) Overload optical power (dBm) Min. extinction ratio (dB) Specification 155.52 Mbit/s NRZ I-1 S-1.1 L-1.1 L-1.2 Ve-1.2
MLM 12601360
MLM 12611360
SLM 14801580
SLM 14801580
15 to 8
15 to 8
5 to 0
5 to 0
3 to 0
23
28
34
34
34
10
10
10
8.2
8.2
10
10
10
Note: MLM indicates the multi-longitudinal mode and SLM indicates the single-longitudinal mode.
Mechanical Specifications
The mechanical specifications of the N1SL1/N2SL1 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.3
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1SL1/N2SL1 is 14 W. In the normal temperature (25), the maximum power consumption of the R1SL1 is 10.3 W.
5.2 SL1A
This section describes the SL1A, a 1 x STM-1 optical interface board, in terms of version, function, principle, front panel and technical specifications. 5.2.1 Version Description The functional version of the SL1A board is N1. 5.2.2 Function and Feature The SL1A is used to transmit and receive STM-1 optical signals, to perform O/E conversion for the STM-1 optical signals, to extract or insert overhead bytes, and to generate alarm signals. 5.2.3 Working Principle and Signal Flow The SL1A board consists of the O/E conversion module, data clock recovery unit, SDH overhead processing module, logic control module and power supply module. 5.2.4 Front Panel On the front panel of the SL1A board, there are indicators, interfaces, barcode and laser safety class label. 5.2.5 Valid Slots The SL1A board can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, and any of slots 1113 in the OptiX OSN 1500B subrack. 5.2.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SL1A indicates the optical interface type. 5.2.7 Board Configuration Reference You can set parameters for the SL1A board on the T2000. 5.2.8 Technical Specifications The technical specifications of the SL1A board cover the optical interface specifications, board dimensions, weight and power consumption.
Table 5-6 Functions and features of the SL1A board Function and Feature Basic function Specification of the optical interface Description Transmits and receives 1 x STM-1 optical signals. Supports standard optical interfaces of the I-1, S-1.1, L-1.1, L-1.2 and Ve-1.2 types. The optical interfaces of the I-1, S-1.1, L-1.1 and L-1.2 types comply with ITU-T G.957 Recommendations in features. The optical interface of the Ve-1.2 type complies with the standards defined by Huawei. Supports detection and query of the information on the optical module. Supports the usage and detection of the pluggable optical module SFP for easy maintenance. The optical interface supports the function of setting the on/off state of the laser and the ALS function. Service processing Overhead processing Supports processing the VC-12, VC-3 or VC-4 service. Supports processing the SOH bytes of the STM-1 signals. Supports the transparent transmission and termination of the POH bytes. Supports setting and querying the J0, J1 or C2 byte. Alarm and performance event Protection scheme Provides abundant alarms and performance events to easily manage and maintain the equipment. Supports the two-fiber unidirectional MSP protection ring, four-fiber MSP protection ring, linear MSP protection ring, sub-network connection protection (SNCP), sub-network connection tunnel protection (SNCTP), and sub-network connection multi-protection (SNCMP). Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports querying the manufacturing information of the board. Supports loading the FPGA in-service. Supports upgrading the board software without affecting services.
Maintenance feature
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Figure 5-4 Block diagram for the working principle of the SL1A
155 MHz
Reference clock
Cross-connect unit
155Mbit/s 155Mbit/s
O/E O/E
S P I
155Mbit/s
CDR
155Mbit/s
K1 and K2 insertion/extration
155Mbit/s
K1 and K2
Cross-connect unit
....
155Mbit/s 155Mbit/s
....
155Mbit/s
Cross-connect unit A
RST
155Mbit/s 155Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
Auxiliary Unit
The auxiliary unit consists of the logic control unit and the power supply module.
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Logic Control Module The logic control module traces the clock signals, which are received from the active or standby cross-connect board, and the frame header signals. This module controls the laser and passes through the orderwire and ECC bytes between the two optical interface boards that form the ADM. This module also selects the clock frame headers from the active or standby cross-connect board.
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The power supply module provides the DC voltages required by the modules of the board.
OUT
IN
SL1A
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the SL1A board, there is one pair of optical interfaces. Table 5-7 lists the type and usage of these optical interfaces.
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Table 5-7 Optical interfaces of the SL1A Interface IN OUT Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
J0 J1 C2
MLM 1260-1360
MLM 1261-1360
SLM 1480-1580
SLM 1480-1580
15-8
15-8
5-0
5-0
3-0
23
28
34
34
34
10
10
10
8.2
8.2
10
10
10
Note: MLM stands for multi-longitudinal mode and SLM for single-longitudinal mode.
Mechanical Specifications
The mechanical specifications of the SL1A board are as follows:
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Power Consumption
At normal ambient temperature (25), the maximum power consumption of the SL1A is 17 W.
5.3 SLQ1
This section describes the SLQ1, a 4 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and parameters. 5.3.1 Version Description The SLQ1 board has three versions, R1, N1 and N2. The difference among the three versions lies in the support for the TCM function and AU-3 service. The R1SLQ1 is a 4 x STM-1 optical interface board, which is housed in a divided slot in a subrack. 5.3.2 Function and Feature The SLQ1 is used to transmit and receive STM-1 optical signals, to perform O/E conversion for the STM-1 optical signals, to extract or insert overhead bytes, and to generate alarm signals. 5.3.3 Working Principle and Signal Flow The SLQ1 board consists of the O/E conversion module, CDR module, SDH overhead processing module, RST and so on. 5.3.4 Front Panel On the front panel of the N1SLQ1/N2SLQ1, there are indicators, interfaces, barcode and laser safety class label.On the front panel of the R1SLQ1, there are indicators, interfaces and barcode. 5.3.5 Valid Slots The slots valid for the SLQ1 vary with the version of the board. 5.3.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SLQ1 indicates the optical interface type. 5.3.7 Board Configuration Reference You can use the T2000 to set parameters for the SLQ1. 5.3.8 Technical Specifications The technical specifications of the SLQ1 cover the optical interface specifications, board dimensions, weight and power consumption.
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Table 5-10 Version Description of the SLQ1 Item Functional version Difference Description The SLQ1 has three versions, R1, N1 and N2. The N2SLQ1 supports the TCM function and AU-3 service. The N1SLQ1 and R1SLQ1 do not support the TCM function and AU-3 service. The R1SLQ1 is housed in a divided slot. Replaceability The versions cannot be replaced by each other.
NOTE
The N2SLQ1 board supports the TCM function and AU-3 service, which are not supported by the N1SLQ1 or R1SLQ1 board. For this reason, when configuring MSP and SNCP, you cannot configure the N1SLQ1 or R1SLQ1 board as the protection board if the working board is N2SLQ1 configured with the TCM service or AU-3 service. Otherwise, the service may be interrupted due to the switching operation.
Function and Feature Alarm and performance event Protection scheme Maintenance feature
SLQ1 Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports the two-fiber unidirectional MSP protection ring, four-fiber MSP protection ring, linear MSP, SNCP, SNCTP and SNCMP. Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
Reference clock
Cross-connect unit
155Mbit/s 155Mbit/s
O/E O/E
S P I
155Mbit/s
CDR
155Mbit/s
K1 and K2 insertion/extration
155Mbit/s
K1 and K2
Cross-connect unit
....
155Mbit/s 155Mbit/s
....
155Mbit/s
Cross-connect unit A
RST
155Mbit/s 155Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
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In the receive direction, the module converts the received optical signals into electrical signals. In the transmit direction, the module converts the electrical signals into SDH optical signals, and then sends optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides function to shut down the laser.
CDR Module
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RST
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In the receive direction, MST performs BIP-24 errored block count, multiplex sectionremote error indication (MS_REI) recovery, multiplex section-remote defect indication (MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. MST provides extraction or insertion of K1 byte and K2 byte. In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In the transmit direction, MST it performs administration unit group (AUG) assembly, AU-4 pointer generation, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
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MST
MSA
HPT
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Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Controls the laser. Realizes the pass-through of orderwire and embedded control channel (ECC) bytes between the paired slots constituting the add/ drop multiplexer (ADM) when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
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DC/DC Converter
It provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SLQ1
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Figure 5-8 shows the appearance of the front panel of the R1SLQ1. Figure 5-8 Front panel of the R1SLQ1
SLQ1
STAT ACT PROG SRV
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the SLQ1. Table 5-12 lists the type and usage of the optical interfaces. Table 5-12 Optical interfaces of the SLQ1 Interfaces IN1-IN4 OUT1-OUT4 Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
The R1SLQ1 can be housed in any of slots 23, 69 and 1213 in the OptiX OSN 1500A subrack. The N1SLQ1 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The N2SLQ1 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The R1SLQ1 can be housed in any of slots 13, 69 and 1113 in the OptiX OSN 1500B subrack. The N1SLQ1 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. The N2SLQ1 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack.
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l l
J0 J1 C2
SLM 14801580
3 to 0
23
28
34
34
34
31
10
10
10
14
8.2
8.2
10
10
10
10
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Mechanical Specifications
The mechanical specifications of the N1SLQ1/N2SLQ1 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1SLQ1/ N2SLQ1 is 15 W. In the normal temperature (25), the maximum power consumption of the R1SLQ1 is 12 W.
5.4 SLQ1A
This section describes the SLQ1A, a 4 x STM-1 optical interface board, in terms of version, function, principle, front panel and technical specifications. 5.4.1 Version Description The functional version of the SLQ1A board is N1. 5.4.2 Function and Feature The SLQ1A is used to transmit and receive STM-1 optical signals, to perform O/E conversion for the STM-1 optical signals, to extract or insert overhead bytes, and to generate alarm signals. 5.4.3 Working Principle and Signal Flow The SLQ1A board consists of the O/E conversion module, data clock recovery unit, SDH overhead processing module, logic control module, and power supply module. 5.4.4 Front Panel On the front panel of the SLQ1A board, there are indicators, interfaces, barcode and laser safety class label. 5.4.5 Valid Slots The SLQ1A board can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, and any of slots 1113 in the OptiX OSN 1500B subrack. 5.4.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SLQ1A indicates the optical interface type. 5.4.7 Board Configuration Reference You can set parameters for the SLQ1A board on the T2000. 5.4.8 Technical Specifications The technical specifications of the SLQ1A board cover the optical interface specifications, board dimensions, weight and power consumption.
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Description Supports inloop and outloop for optical interfaces. Supports inloop and outloop at a path level. Supports warm reset and cold reset. The warm reset does not affect services. Supports querying the manufacturing information of the board. Supports loading the FPGA in-service. Supports upgrading the board software without affecting services.
Reference clock
Cross-connect unit
155Mbit/s 155Mbit/s
O/E O/E
S P I
155Mbit/s
CDR
155Mbit/s
K1 and K2 insertion/extration
155Mbit/s
K1 and K2
Cross-connect unit
....
155Mbit/s 155Mbit/s
....
155Mbit/s
Cross-connect unit A
RST
155Mbit/s 155Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
The overhead processing module also extracts overhead bytes from the received STM-1 signals and transmits the signals to the cross-connect unit through the backplane bus.
Auxiliary Unit
The auxiliary unit consists of the logic control unit and the power supply module.
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Logic Control Module The logic control module traces the clock signals, which are received from the active or standby cross-connect board, and the frame header signals. This module controls the laser and passes through the orderwire and ECC bytes between the two optical interface boards that form the ADM. This module also selects the clock frame headers from the active or standby cross-connect board.
Power Supply Module The power supply module provides the DC voltages required by the modules of the board.
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SLQ1A
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the SLQ1A board, there are four pairs of optical interfaces. Table 5-16 lists the type and usage of the optical interfaces. Table 5-16 Optical interfaces of the SLQ1A board Interface IN1-IN4 OUT1OUT4 Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
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J0 J1 C2
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Table 5-18 Specifications of the optical interfaces of the SLQ1A board Item Nominal bit rate Line code Optical interface type Optical source type Working wavelength (nm) Launched optical power (dBm) Receiver sensitivity (dBm) Overload optical power (dBm) Minimum extinction ratio (dB) Specification 155520kbit/s NRZ I-1 S-1.1 L-1.1 L-1.2 Ve-1.2 Ie-1
SLM 1480-1580
3-0
23
28
34
34
34
31
10
10
10
14
8.2
8.2
10
10
10
10
Note: MLM stands for multi-longitudinal mode and SLM for single-longitudinal mode.
Mechanical Specifications
The mechanical specifications of the SLQ1A board are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
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Power Consumption
At normal ambient temperature (25), the maximum power consumption of the SLQ1A board is 17 W.
5.5 SLO1
This section describes the SLO1, an 8 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and parameters. 5.5.1 Version Description The functional version of the SLO1 board is N1. 5.5.2 Function and Feature The SLO1 is used to access 8 x STM-1 optical signals, to perform the O/E conversion to the signals, to insert or extract the overhead bytes, and to generate alarm signals. 5.5.3 Working Principle and Signal Flow The SLO1 board consists of the O/E conversion module, CDR module, SDH overhead processing module, RST and so on. 5.5.4 Front Panel On the front panel of the SLO1, there are indicators, interfaces, barcode and laser safety class label. 5.5.5 Valid Slots If the SLO1 is housed in any of slots 1213 of the OptiX OSN 1500A subrack, one to eight optical interfaces can be configured. If the SLO1 is housed in any of slots 1113 of the OptiX OSN 1500B subrack, one to eight optical interfaces can be configured. 5.5.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SLO1 indicates the optical interface type. 5.5.7 Board Configuration Reference You can use the T2000 to set parameters for the SLO1. 5.5.8 Technical Specifications The technical specifications of the SLO1 cover the optical interface specifications, board dimensions, weight and power consumption.
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Table 5-19 Functions and features of the SLO1 board Function and Feature Basic function Specification of the optical interface SLO1 Receives and transmits 8 x STM-1 optical signals. Supports standard optical interfaces of the I-1.1, S-1.1, L-1.1, L-1.2 and Ve-1.2 types. The optical interfaces of the I-1, S-1.1, L-1.1 and L-1.2 types comply with ITU-T G.957 in features. The optical interface of the Ve-1.2 type complies with the standards defined by Huawei. The optical module is pluggable. When optical modules of other types are inserted, an alarm indicating the mismatch of the optical module is reported. Supports detection and query of the information on the optical module. Supports the default off state of the laser. The laser is turned off before the software finishes the initialization when the board is powered on. Supports the usage and detection of the pluggable optical module SFP. Supports the setting and query of the on/off state of the laser. An alarm is generated when the laser is turned off. Performance events are reported to indicate the performance of the optical module. Service processing Supports the processing of the VC-12, VC-3 and VC-4 services. Supports AU-3 services. Overhead processing Supports the processing of the SOH bytes of the STM-1 signals. Supports the transparent transmission and termination of the POH bytes. If the two SCC boards are not in service, the SLO1 does not transmit overhead bytes (long 0s) to the two SCC boards. Supports one to eight channels of ECC communication. Alarm and performance event Protection scheme Maintenance feature Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports the two-fiber unidirectional MSP protection ring, four-fiber MSP protection ring, linear MSP, SNCP, SNCTP and SNCMP. Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
Figure 5-11 shows the block diagram for the working principle of the SLO1. Figure 5-11 Block diagram for the working principle of the SLO1
155 MHz
Reference clock
Cross-connect unit
155Mbit/s 155Mbit/s
O/E O/E
S P I
155Mbit/s
CDR
155Mbit/s
K1 and K2 insertion/extration
155Mbit/s
K1 and K2
Cross-connect unit
....
155Mbit/s 155Mbit/s
....
155Mbit/s
Cross-connect unit A
RST
155Mbit/s 155Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
MST: multiplex section termination MSA: multiplex section adaptation CDR: clock and data recovery
In the receive direction, the module converts the received optical signals into electrical signals. In the transmit direction, the module converts the electrical signals into SDH optical signals, and then sends optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides function to shut down the laser.
CDR Module
l
RST
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
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In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In the receive direction, MST performs BIP-24 errored block count, multiplex sectionremote error indication (MS_REI) recovery, multiplex section-remote defect indication (MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. MST provides extraction or insertion of K1 byte and K2 byte. In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In the transmit direction, MST it performs administration unit group (AUG) assembly, AU-4 pointer generation, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
MST
MSA
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Controls the laser. Realizes the pass-through of orderwire and embedded control channel (ECC) bytes between the paired slots constituting the add/ drop multiplexer (ADM) when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
l l
DC/DC Converter
It provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SLO1
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight pairs of optical interfaces on the front panel of the SLO1. Table 5-20 lists the type and usage of the optical interfaces. Table 5-20 Optical interfaces of the SLO1 Interfaces IN1IN8 OUT1OUT8 Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
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The optical interfaces of the SLO1 are level optical interfaces and indented by 20 mm. The SLO1 board can use the pluggable optical modules for easy maintenance.
WARNING
The optical interfaces of the SLO1 board are level optical interfaces. Thus, use the optical attenuator only at the ODF side.
J0 J1 C2
Mechanical Specifications
The mechanical specifications of the SLO1 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
Power Consumption
In the normal temperature (25), the maximum power consumption of the SLO1 is 26W.
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5.6 SLT1
This section describes the SLT1, a 12 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.6.1 Version Description The functional version of the SLT1 board is N1. 5.6.2 Function and Feature The SLT1 is used to transmit and receive STM-1 optical signals, to perform O/E conversion for STM-1 optical signals, to extract or insert overhead bytes, and to generate alarm signals. 5.6.3 Working Principle and Signal Flow The SLT1 board consists of the O/E conversion module, CDR module, SDH overhead processing module, RST and so on. The external services are accessed by the external interface boards EU08 and OU08 . The EU08 is an electrical interface board, and the OU08 is an optical interface board. 5.6.4 Front Panel On the front panel of the SLT1, there are indicators, interfaces, barcode and laser safety class label. 5.6.5 Valid Slots The SLT1, housed in any of slots 1213 of the OptiX OSN 1500A subrack, one to twelve optical interfaces can be configured. For the SLT1, housed in any of slots 1113 of the OptiX OSN 1500B subrack, one to twelve optical interfaces can be configured. 5.6.6 Board Configuration Reference You can use the T2000 to set parameters for the SLT1. 5.6.7 Technical Specifications The technical specifications of the SLT1 cover the optical interface specifications, board dimensions, weight and power consumption.
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Function and Feature Specification of the optical interface Specification of the optical module
SLT1 Supports S-1.1 standard optical interfaces compliant with ITU-T G.957 in features. Supports detection and query of the information on the optical module. The optical interface supports the function of setting the on/off state of the laser and the ALS function. Supports the usage and detection of the pluggable optical module SFP for easy maintenance.
Supports the processing of the VC-12, VC-3 and VC-4 services. Supports the processing of the SOH bytes of the STM-1 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes. The port one to port eight support one to eight channels of ECC communication(D1 D12), The port nine to port twelve support one to four channels of ECC communication(D1 D3) .
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports the two-fiber unidirectional MSP protection ring, four-fiber MSP protection ring, linear MSP protection ring, SNCP, SNCTP, and SNCMP. Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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Figure 5-13 Block diagram for the working principle of the SLT1
155 MHz
Reference clock
Cross-connect unit
155Mbit/s 155Mbit/s
O/E O/E
S P I
155Mbit/s
CDR
155Mbit/s
K1 and K2 insertion/extration
155Mbit/s
K1 and K2
Cross-connect unit
....
155Mbit/s 155Mbit/s
....
155Mbit/s
Cross-connect unit A
RST
155Mbit/s 155Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
MST: multiplex section termination MSA: multiplex section adaptation CDR: clock and data recovery
In the receive direction, the module converts the received optical signals into electrical signals. In the transmit direction, the module converts the electrical signals into SDH optical signals, and then sends optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides function to shut down the laser.
CDR Module
l
RST
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion.
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MST
In the receive direction, MST performs BIP-24 errored block count, multiplex sectionremote error indication (MS_REI) recovery, multiplex section-remote defect indication (MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. MST provides extraction or insertion of K1 byte and K2 byte. In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In the transmit direction, MST it performs administration unit group (AUG) assembly, AU-4 pointer generation, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
MSA
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Controls the laser. Realizes the pass-through of orderwire and embedded control channel (ECC) bytes between the paired slots constituting the add/ drop multiplexer (ADM) when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
l l
DC/DC Converter
It provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8 OUT9 IN9 OUT10 IN10 OUT11 IN11 OUT12 IN12
SLT1
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are 12 pairs of optical interfaces on the front panel of the SLT1. Table 5-24 lists the type and usage of the optical interfaces. Table 5-24 Optical interfaces of the SLT1 Interface IN1-IN12 OUT1-OUT12 Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
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WARNING
The optical interfaces of the SLT1 board are level optical interfaces. Thus, use the optical attenuator only at the ODF side.
J0 J1 C2
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Mechanical Specifications
The mechanical specifications of the SLT1 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.2
Power Consumption
In the normal temperature (25), the maximum power consumption of the SLT1 is 15 W.
5.7 SEP1
This section describes the SEP1 board, in terms of the version, function, working principle, front panel, and specifications. 5.7.1 Version Description The functional version of the SEP1 board is N1. 5.7.2 Function and Feature The SEP1 board processes STM-1 electrical signals. 5.7.3 Working Principle and Signal Flow The SEP1 board consists of the line interface module and CDR module, SDH overhead processing module, RST and so on. The external services are accessed by the external interface boards EU08 and OU08. The EU08 is an electrical interface board, and the OU08 is an optical interface board. 5.7.4 Front Panel On the front panel of the SEP1, there are indicators, interfaces and barcode. 5.7.5 Valid Slots When the SEP1 board is housed in any of slots 1213 of the OptiX OSN 1500A subrack, it cannot be used with the interface board. In the OptiX OSN 1500B subrack, when interfaces are available on the front panel of the SEP1 board, it can be housed in any of slots 1113. When the SEP1 board is used with the interface board, it is defined as SEP. In this case, it can be housed in any of slots 1213. 5.7.6 TPS Protection for the Board The TPS protection is equipment-level protection. When the working board fails, the accessed services are switched to the protection board. 5.7.7 Board Configuration Reference You can use the T2000 to set parameters for the SEP1. 5.7.8 Technical Specifications The technical specifications of the SEP1 cover the board dimensions, weight and power consumption.
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SEP1 Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
When the SEP1 is used with different interface boards and electrical interface switching boards, the access capabilities for the STM-1 signals are different. See Table 5-27. Table 5-27 Access capabilities for the SEP1 Interface Board None EU08 OU08 EU08+OU08 EU08+TSB8 SEP1 Accesses and processes 2 x STM-1 electrical signals, and does not support the TPS protection. Accesses and processes 8 x STM-1 electrical signals. Accesses and processes 8 x STM-1 optical signals. The hybrid usage is not supported. Accesses and processes 8 x STM-1 electrical signals, and supports the TPS protection for the SEP1 board.
CAUTION
When the SEP1 is used with the interface board, the two interfaces on the front panel are invalid. The hybrid usage of the EU08 and OU08 is not supported.
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Figure 5-15 Block diagram for the working principle of the SEP1
155 MHz PLL
Reference clock Cross-connect unit
K1 and K2 insertion/extration
K1 and K2
Cross-connect unit
high speed bus 155 Mbit/s Port 1 155 Mbit/s 155 Mbit/s Port 2 155 Mbit/s CMI
Transfo rmer
CMI
NRZ
CDR
RST
MST
MSA
HPT
NRZ
Transfor mer
CDR
SCC unit
LOS
Frame header
Communication
+1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
Figure 5-16 shows the block diagram for the working principle of the SEP used with the EU08. Figure 5-16 Block diagram for the working principle of the SEP used with the EU08
155 MHz PLL
EU08 155 Mbit/s Port 1 155 Mbit/s SPI CMI 155 Mbit/s 155 Mbit/s Reference clock Cross-connect unit
Transfo rmer
CDR
K1 and K2 insertion/extration
K1 and K2
Cross-connect unit
Port 8
Transfo rmer
CMI
CDR
155 Mbit/s 155 Mbit/s high speed bus Cross-connect unit A Cross-connect unit B
155 Mbit/s Port 1 155 Mbit/s Port 2 155 Mbit/s 155 Mbit/s
CMI
Transfo rmer
CMI
CDR
RST
MST
MSA
HPT
Transfor mer
NRZ
CDR
SCC unit
LOS
+1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
Figure 5-17 shows the block diagram for the working principle of the SEP used with the OU08.
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Figure 5-17 Block diagram for the working principle of the SEP used with the OU08
OU08 155 Mbit/s Port 1 155 Mbit/s
Reference clock
Cross-connect unit
NRZ
CDR
K1 and K2 insertion/extration
K1 and K2
Cross-connect unit
NRZ
CDR
Port 1
Transfo rmer
CMI
NRZ
CDR
RST
MST
MSA
HPT
Cross-connect unit B
Port 2
CMI
NRZ
CDR
mer
DC/DC converter
DC/DC converter
Fuse
Fuse
In the receive direction, the received electrical signals (CMI code) are isolated through the converter and then transmitted to the decoding unit. The CDR module then recovers the data and clock signals after decoding. In the transmit direction, the SDH signals, which are processed by the overhead processing unit, are transmitted to the encoding unit. After isolation by converter, 155 Mbit/s electrical signals (CMI code) are output. The encoding and decoding unit monitors R_LOS alarms.
RST
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In the receive direction, MST performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte.
MST
MSA
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In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In the transmit direction, MSA performs AUG assembly, AU-4 pointer generation, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect unit. Controls the laser. Realizes the pass-through of orderwire and ECC bytes between the paired slots constituting the ADM when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
l l
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SEP1
STAT ACT PROG SRV
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two pairs of optical interfaces on the front panel of the SEP1. Table 5-28 lists the type and usage of the optical interfaces.
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Table 5-28 Electrical interfaces of the SEP1 Interface IN1-IN2 OUT1-OUT2 Interface Type 75-ohm SMB 75-ohm SMB Usage Receives the STM-1 signals. Transmits the STM-1 signals.
Note: The SEP1 board can also be used with interface boards EU08 and OU08. In this case, the SEP1 is defined as the SEP. When the SEP1 is used with the interface board, the two interfaces on the front panel are invalid.
Protection Principle
Figure 5-19 shows the principle of the TPS protection for the SEP1 board. Figure 5-19 Principle of the TPS protection for the SEP1
8 STM-1(e) Switch control signal
TSB8
EU08
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Normal state: When the working boards are running normally, the control switch of the EU08 is in position 1 and the EU08 directly accesses the service signals to the SEP1 board. Switching state: When a failure is detected on the working board, the working board housed in each slot can be protected in the following ways.
When the working board housed in slot 13 fails, the control switch of the corresponding EU08 shifts from position 1 to position 2. At the same time, the control switch of the TSB8 shifts from position 1 to position 2, and thus the working board housed in slot 13 is protected by the protection board housed in slot 12.
Hardware Configuration
Figure 5-20 shows the slot configuration for the 1:1 TPS protection for the SEP1. Figure 5-20 Slot configuration for the 1:1 TPS protection for the SEP1
Slot 14 Slot 15 Slot 16 Slot 17 Slot 11 Slot 20 FAN Slot 12 Slot 13 Slot 4 Slot 5 Protection Working CXL16/4/1 CXL16/4/1 EU08 TSB8 Slot 18 PIU
PIU
EOW AUX
As shown in Figure 5-20, the protection board housed in slot 12 protects the board housed in slot 13. Table 5-29 lists the slots for the SEP1, EU08 and TSB8. Table 5-29 Slots for the SEP1, EU08 and TSB8 Board SEP1 (working board) TSB8 SEP1 (working board) EU08 Protection Group Slot 12 Slot 14 Slot 13 Slot 16
J0 J1 C2
Mechanical Specifications
The mechanical specifications of the SEP1 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the SEP1 is 17 W.
5.8 SL4
This section describes the SL4, a 1 x STM-4 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.8.1 Version Description The SL4 board has three versions, R1, N1 and N2. The difference among the three versions lies in the support for the TCM function. The R1SL4 is an STM-1 optical interface board, which is housed in a divided slot in a subrack. 5.8.2 Function and Feature The SL4 board is used to receive and transmit 1 x STM-4 optical signals, to process the overhead bytes, and to perform the MSP protection. 5.8.3 Working Principle and Signal Flow The SL4 board consists of the O/E conversion module, CDR module, SDH overhead processing module, RST and so on. 5.8.4 Front Panel
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On the front panel of the N1SL4/N2SL4, there are indicators, interfaces, barcode and laser safety class label.On the front panel of the R1SL4, there are indicators, interfaces and barcode. 5.8.5 Valid Slots The slots valid for the SL4 vary with the version of the board. 5.8.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SL4 indicates the optical interface type. 5.8.7 Board Configuration Reference You can use the T2000 to set parameters for the SL4. 5.8.8 Technical Specifications The technical specifications of the SL4 cover the optical interface specifications, board dimensions, weight and power consumption.
NOTE
The N2SL4 board supports the TCM function and AU-3 services, which are not supported by the N1SL4 or R1SL4 board. For this reason, when configuring MSP and SNCP, you cannot configure the N1SL4 or R1SL4 board as the protection board if the working board is N2SL4 configured with the TCM service . Otherwise, the service may be interrupted due to the switching operation.
Table 5-32 Functions and features of the SL4 Function and Feature Basic function Specification of the optical interface Specification of the optical module SL4 Receives and transmits 1 x STM-4 optical signals, and processes 1 x STM-4 standard or concatenation services. Supports standard optical interfaces of the I-4, S-4.1, L-4.1, L-4.2 and Ve-4.2 types. The optical interfaces of the I-4, S-4.1, L-4.1 and L-4.2 types comply with ITU-T G.957 in features. The optical interface of the Ve-4.2 type complies with the standards defined by Huawei. Supports detection and query of the information on the optical module. The optical interface supports the function of setting the on/off state of the laser and the ALS function. Supports the usage and monitoring of the pluggable optical module SFP. Service processing Overhead processing Supports VC-12, VC-3, and VC-4 services and VC4-4c concatenation services. Supports the processing of the SOH bytes of the STM-4 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes. Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports the two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP, SNCP, SNCTP, and SNCMP. Supports the optical-path-shared MSP and SNCP protection. Maintenance feature Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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Figure 5-21 Block diagram for the working principle of the SL4
155 MHz
Reference clock
Cross-connect unit
622Mbit/s 622Mbit/s
O/E O/E
S P I
622Mbit/s
CDR
622Mbit/s
K1 and K2 insertion/extration
622Mbit/s
K1 and K2
Cross-connect unit
....
622Mbit/s 622Mbit/s
....
622Mbit/s
Cross-connect unit A
RST
622Mbit/s 622Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
MST: multiplex section termination MSA: multiplex section adaptation CDR: clock and data recovery
In the receive direction, the module converts the received optical signals into electrical signals. In the transmit direction, the module converts the electrical signals into SDH optical signals, and then sends optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides function to shut down the laser.
CDR Module
l
RST
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion.
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MST
In the receive direction, MST performs BIP-24 errored block count, multiplex sectionremote error indication (MS_REI) recovery, multiplex section-remote defect indication (MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. MST provides extraction or insertion of K1 byte and K2 byte. In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In the transmit direction, MST it performs administration unit group (AUG) assembly, AU-4 pointer generation, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
MSA
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Controls the laser. Realizes the pass-through of orderwire and embedded control channel (ECC) bytes between the paired slots constituting the add/ drop multiplexer (ADM) when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
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DC/DC Converter
It provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
OUT
IN
SL4
Figure 5-23 shows the appearance of the front panel of the R1SL4. Figure 5-23 Front panel of the R1SL4
SL4
STAT ACT PROG SRV
OUT IN
SL4
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SL4. Table 5-33 lists the type and usage of the optical interfaces. Table 5-33 Optical interfaces of the SL4 Interface IN OUT Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
The SL4 board can use the pluggable optical modules for easy maintenance.
The R1SL4 can be housed in any of slots 23, 69 and 1213 in the OptiX OSN 1500A subrack. The N1SL4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The N2SL4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The R1SL4 can be housed in any of slots 13, 69 and 1113 in the OptiX OSN 1500B subrack. The N1SL4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. The N2SL4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack.
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Feature Code 10
Feature Code 11 12 13 14
J0 J1 C2
Specification 622080 kbit/s NRZ I-4 MLM 12611360 15 to 8 23 S-4.1 MLM 12741356 15 to 8 28 L-4.1 SLM 12801335 3 to +2 28 L-4.2 SLM 14801580 3 to +2 28 Ve-4.2 SLM 14801580 3 to +2 34
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Mechanical Specifications
The mechanical specifications of the N1SL4/N2SL4 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.5
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1SL4/N2SL4 is 15 W. In the normal temperature (25), the maximum power consumption of the R1SL4 is 10 W.
5.9 SL4A
This section describes the SL4A, a 1 x STM-4 optical interface board, in terms of version, function, principle, front panel and technical specifications. 5.9.1 Version Description The functional version of the SL4A board is N1. 5.9.2 Function and Feature The SL4A board is used to receive and transmit 1 x STM-4 optical signals, to process the overhead bytes, and to perform the MSP protection. 5.9.3 Working Principle and Signal Flow The SL4A board consists of the O/E conversion module, data clock recovery unit, SDH overhead processing module, logic control module and power supply module. 5.9.4 Front Panel On the front panel of the SL4A board, there are indicators, interfaces, barcode and laser safety class label. 5.9.5 Valid Slots
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The SL4A board can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The SL4A board can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 5.9.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SL4A indicates the optical interface type. 5.9.7 Board Configuration Reference You can set parameters for the SL4A board on the T2000. 5.9.8 Technical Specifications The technical specifications of the SL4A board cover the optical interface specifications, board dimensions, weight and power consumption.
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Description Provides abundant alarms and performance events to easily manage and maintain the equipment. Supports the two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP, sub-network connection protection (SNCP), subnetwork connection tunnel protection (SNCTP) and sub-network connection multi-protection (SNCMP). Supports the optical-path-shared MSP and SNCP protection.
Maintenance feature
Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports querying the manufacturing information of the board. Supports loading the FPGA in-service. Supports upgrading the board software without affecting services.
Reference clock
Cross-connect unit
622Mbit/s 622Mbit/s
O/E O/E
S P I
622Mbit/s
CDR
622Mbit/s
K1 and K2 insertion/extration
622Mbit/s
K1 and K2
Cross-connect unit
....
622Mbit/s 622Mbit/s
....
622Mbit/s
Cross-connect unit A
RST
622Mbit/s 622Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
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Auxiliary Unit
The auxiliary unit consists of the logic control unit and the power supply module.
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Logic Control Module The logic control module traces the clock signals, which are received from the active or standby cross-connect board, and the frame header signals. This module controls the laser and passes through the orderwire and ECC bytes between the two optical interface boards that form the ADM. This module also selects the clock frame headers from the active or standby cross-connect board.
Power Supply Module The power supply module provides the DC voltages required by the modules of the board.
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OUT
IN
SL4A
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the SL4A board, there is one pair of optical interfaces. Table 5-37 lists the type and usage of the optical interfaces. Table 5-37 Optical interfaces of the SL4A Interface IN OUT Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
The SL4A board can use the pluggable optical modules for easy maintenance.
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Table 5-39 Specifications of the optical interfaces of the SL4A board Item Nominal bit rate Line code Optical interface type Optical source type Working wavelength (nm) Launched optical power (dBm) Receiver sensitivity (dBm) Overload optical power (dBm) Minimum extinction ratio (dB) Specification 622080 kbit/s NRZ I-4 MLM 1261-1360 15-8 23 8 8.2 S-4.1 MLM 1274-1356 15-8 28 8 8.2 L-4.1 SLM 1280-1335 3-2 28 8 10 L-4.2 SLM 1480-1580 3-2 28 8 10 Ve-4.2 SLM 1480-1580 3-2 34 13 10.5
Note: MLM stands for multi-longitudinal mode and SLM for single-longitudinal mode.
Mechanical Specifications
The mechanical specifications of the SL4A board are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
At normal ambient temperature (25), the maximum power consumption of the SL4A board is 17 W.
5.10 SLD4
This section describes the SLD4, a 2 x STM-4 optical interface board, in terms of the version, function, working principle, front panel and specifications.
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5.10.1 Version Description The SLD4 board has three versions, R1, N1 and N2. The difference among the three versions lies in the support for the TCM function. The R1SLD4 is a 2 x STM-1 optical interface board, which is housed in a divided slot in a subrack. 5.10.2 Function and Feature The SLD4 is used to transmit and receive STM-4 optical signals, to perform O/E conversion for STM-4 signals, to extract or insert overhead bytes, and to generate alarm signals on the line. 5.10.3 Working Principle and Signal Flow The SLD4 board consists of the O/E conversion module, CDR module, SDH overhead processing module so on. 5.10.4 Front Panel On the front panel of the N1SLD4/N2SLD4, there are indicators, interfaces, barcode and laser safety class label.On the front panel of the R1SLD4, there are indicators, interfaces and barcode. 5.10.5 Valid Slots The slots valid for the SLD4 vary with the cross-connect capacity of the subrack. 5.10.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SLD4 indicates the optical interface type. 5.10.7 Board Configuration Reference You can use the T2000 to set parameters for the SLD4. 5.10.8 Technical Specifications The technical specifications of the SLD4 cover the optical interface specifications, board dimensions, weight and power consumption.
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The N2SLD4 board supports the TCM function and AU-3 services, which are not supported by the N1SLD4 or R1SLD4 board. For this reason, when configuring MSP and SNCP, you cannot configure the N1SLD4 or R1SLD4 board as the protection board if the working board is N2SLD4 configured with the TCM service .Otherwise, the service may be interrupted due to the switching operation.
Reference clock
Cross-connect unit
622Mbit/s 622Mbit/s
O/E O/E
S P I
622Mbit/s
CDR
622Mbit/s
K1 and K2 insertion/extration
622Mbit/s
K1 and K2
Cross-connect unit
....
622Mbit/s 622Mbit/s
....
622Mbit/s
Cross-connect unit A
RST
622Mbit/s 622Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
MST: multiplex section termination MSA: multiplex section adaptation CDR: clock and data recovery
In the receive direction, the module converts the received optical signals into electrical signals. In the transmit direction, the module converts the electrical signals into SDH optical signals, and then sends optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides function to shut down the laser.
CDR Module
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RST
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In the receive direction, MST performs BIP-24 errored block count, multiplex sectionremote error indication (MS_REI) recovery, multiplex section-remote defect indication (MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. MST provides extraction or insertion of K1 byte and K2 byte. In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In the transmit direction, MST it performs administration unit group (AUG) assembly, AU-4 pointer generation, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
MST
MSA
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Controls the laser. Realizes the pass-through of orderwire and embedded control channel (ECC) bytes between the paired slots constituting the add/ drop multiplexer (ADM) when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
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DC/DC Converter
It provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
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SLD4
Figure 5-28 shows the appearance of the front panel of the R1SLD4.
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SLD4
STAT ACT PROG SRV
SLD4
OUT IN OUT IN
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two pairs of optical interfaces on the front panel of the SLD4. Table 5-42 lists the type and usage of the optical interfaces. Table 5-42 Optical interfaces of the SLD4 Interface IN1-IN2 OUT1-OUT2 Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
The SLD4 board can use the pluggable optical modules for easy maintenance.
The R1SLD4 can be housed in any of slots 23, 69 and 1213 in the OptiX OSN 1500A subrack. The N1SLD4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The N2SLD4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The R1SLD4 can be housed in any of slots 13, 69 and 1113 in the OptiX OSN 1500B subrack. For the board housed in any of slots 13 and 1113, two optical interfaces can be configured. For the board housed in any of slots 69, one optical interface can be configured. The N1SLD4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. The N2SLD4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack.
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J0 J1 C2
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15 to 8
15 to 8
3 to +2
3 to +2
3 to +2
23
28
28
28
34
13
8.2
8.2
10
10
10.5
Mechanical Specifications
The mechanical specifications of the N1SLD4/N2SLD4 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
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Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.5
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1SLD4/N2SLD4 is 15 W. In the normal temperature (25), the maximum power consumption of the R1SLD4 is 11 W.
5.11 SLD4A
This section describes the SLD4A, a 2 x STM-4 optical interface board, in terms of version, function, principle, front panel and technical specifications. 5.11.1 Version Description The functional version of the SLD4A board is N1. 5.11.2 Function and Feature The SLD4A board is used to transmit and receive STM-4 optical signals, to perform O/E conversion for STM-4 signals, to extract or insert overhead bytes, and to generate alarm signals. 5.11.3 Working Principle and Signal Flow The SLD4A board consists of the O/E conversion module, SDH overhead processing module, logic control module and power supply module. 5.11.4 Front Panel On the front panel of the SLD4A board, there are indicators, interfaces, barcode and laser safety class label. 5.11.5 Valid Slots The SLD4A can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The SL4A board can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 5.11.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SLD4A indicates the optical interface type. 5.11.7 Board Configuration Reference You can set parameters for the SLD4A board on the T2000. 5.11.8 Technical Specifications The technical specifications of the SLD4A board cover the optical interface specifications, board dimensions, weight and power consumption.
Table 5-45 lists the functions and features of the SLD4A board. Table 5-45 Functions and features of the SLD4A board Function and Feature Basic function Specification of the optical interface Description Receives and transmits 2 x STM-4 optical signals, and processes 2 x STM-4 standard or concatenation services. Supports standard optical interfaces of the I-4, S-4.1, L-4.1, L-4.2 and Ve-4.2 types. The optical interfaces of the I-4, S-4.1, L-4.1 and L-4.2 types comply with ITU-T G.957 Recommendations in features. The optical interface of the Ve-4.2 type complies with the standards defined by Huawei. Supports detection and query of the information on the optical module. The optical interface supports the function of setting the on/off state of the laser and the ALS function. Supports using and monitoring the SFP pluggable optical module. Service processing Overhead processing Supports VC-12, VC-3, VC-4 services and VC4-4c concatenation services. Supports processing the SOH bytes of the STM-4 signals. Supports the transparent transmission and termination of the POH bytes. Supports setting and querying the J0, J1 or C2 byte. Supports one to two channels of ECC communication. Alarm and performance event Protection scheme Provides abundant alarms and performance events to easily manage and maintain the equipment. Supports the two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP, sub-network connection protection (SNCP), subnetwork connection tunnel protection (SNCTP) and sub-network connection multi-protection (SNCMP). Supports the optical-path-shared MSP and SNCP protection. Maintenance feature Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports querying the manufacturing information of the board. Supports loading the FPGA in-service. Supports upgrading the board software without affecting services.
Figure 5-29 Block diagram for the working principle of the SL4A board
Slot 1 Slot 20 FAN Slot 12 Slot 13 Slot 4 Slot 5 CXL CXL Slot 11 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 EOW AUX
Auxiliary Unit
The auxiliary unit consists of the logic control unit and the power supply module.
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Logic Control Module The logic control module traces the clock signals, which are received from the active or standby cross-connect board, and the frame header signals. This module controls the laser and passes through the orderwire and ECC bytes between the two optical interface boards that form the ADM. This module also selects the clock frame headers from the active or standby cross-connect board.
Power Supply Module The power supply module provides the DC voltages required by the modules of the board.
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SLD4A
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the SLD4A board, there are two pairs of optical interfaces. Table 5-46 lists the type and usage of the optical interfaces. Table 5-46 Optical interfaces of the SLD4A board Interface IN1IN2 OUT1OUT2 Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
The SLD4A board can use the pluggable optical modules for easy maintenance.
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Table 5-48 Specifications of the optical interfaces of the SLD4A board Item Nominal bit rate Line code Optical interface type Optical source interface Working wavelength (nm) Launched optical power (dBm) Receiver sensitivity (dBm) Overload optical power (dBm) Minimum extinction ratio (dB) Specification 622080 kbit/s NRZ I-4 MLM 1261-1360 S-4.1 MLM 1274-1356 L-4.1 SLM 1280-1335 L-4.2 SLM 1480-1580 Ve-4.2 SLM 1480-1580
15-8
15-8
3-2
3-2
3-2
23
28
28
28
34
13
8.2
8.2
10
10
10.5
Note: MLM stands for multi-longitudinal mode and SLM for single-longitudinal mode.
Mechanical Specifications
The mechanical specifications of the SLD4A board are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
At normal ambient temperature (25), the maximum power consumption of the SLD4A is 17 W.
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5.12 SLQ4
This section describes the SLQ4, a 4 x STM-4 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.12.1 Version Description The SLQ4 board has two versions, N1 and N2. The difference between the two versions lies in the support for the TCM function. 5.12.2 Function and Feature The SLQ4 is used to transmit and receive STM-4 optical signals, to perform O/E conversion for STM-4 signals, to extract or insert overhead bytes, and to generate alarm signals on the line. 5.12.3 Working Principle and Signal Flow The SLQ4 board consists of the O/E conversion module, CDR module, SDH overhead processing module, RST and so on. 5.12.4 Front Panel On the front panel of the SLQ4, there are indicators, interfaces, barcode and laser safety class label. 5.12.5 Valid Slots The SLQ4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The SLQ4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 5.12.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SLQ4 indicates the optical interface type. 5.12.7 Board Configuration Reference You can use the T2000 to set parameters for the SLQ4. 5.12.8 Technical Specifications The technical specifications of the SLQ4 cover the optical interface specifications, board dimensions, weight and power consumption.
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Item Replaceability
NOTE
The N2SLQ4 board supports the TCM function and AU-3 services, which are not supported by the N1SLQ4 board. For this reason, when configuring MSP and SNCP, you cannot configure the N1SLQ4 board as the protection board if the working board is N2SLQ4 configured with the TCM service or AU-3 services. Otherwise, the service may be interrupted due to the switching operation.
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SLQ4 Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
Reference clock
Cross-connect unit
622Mbit/s 622Mbit/s
O/E O/E
S P I
622Mbit/s
CDR
622Mbit/s
K1 and K2 insertion/extration
622Mbit/s
K1 and K2
Cross-connect unit
....
622Mbit/s 622Mbit/s
....
622Mbit/s
Cross-connect unit A
RST
622Mbit/s 622Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
MST: multiplex section termination MSA: multiplex section adaptation CDR: clock and data recovery
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In the receive direction, the module converts the received optical signals into electrical signals. In the transmit direction, the module converts the electrical signals into SDH optical signals, and then sends optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides function to shut down the laser.
CDR Module
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RST
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In the receive direction, MST performs BIP-24 errored block count, multiplex sectionremote error indication (MS_REI) recovery, multiplex section-remote defect indication (MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. MST provides extraction or insertion of K1 byte and K2 byte. In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In the transmit direction, MST it performs administration unit group (AUG) assembly, AU-4 pointer generation, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
MST
MSA
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units.
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Controls the laser. Realizes the pass-through of orderwire and embedded control channel (ECC) bytes between the paired slots constituting the add/ drop multiplexer (ADM) when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
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DC/DC Converter
It provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SLQ4
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit.
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Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the SLQ4. Table 5-51 lists the type and usage of the optical interfaces. Table 5-51 Optical interfaces of the SLQ4 Interface IN1-IN4 OUT1-OUT4 Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
The SLQ4 board can use the pluggable optical modules for easy maintenance.
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15 to 8
15 to 8
3 to +2
3 to +2
3 to +2
23
28
28
28
34
8 8.2
8 8.2
8 10
8 10
13 10.5
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Mechanical Specifications
The mechanical specifications of the SLQ4 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the SLQ4 is 16 W.
5.13 SLQ4A
This section describes the SLQ4A, a 4 x STM-4 optical interface board, in terms of version, function, principle, front panel and technical specifications. 5.13.1 Version Description The functional version of the SLQ4A board is N1. 5.13.2 Function and Feature The SLQ4A board is used to transmit and receive STM-4 optical signals, to perform O/E conversion on STM-4 signals, to extract or insert overhead bytes, and to generate alarm signals. 5.13.3 Working Principle and Signal Flow The SLQ4A board consists of the O/E conversion module, SDH overhead processing module, logic control module and power supply module. 5.13.4 Front Panel On the front panel of the SLQ4A board, there are indicators, interfaces, barcode and laser safety class label. 5.13.5 Valid Slots The SLQ4A can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The SLQ4A board can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 5.13.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SLQ4A indicates the optical interface type. 5.13.7 Board Configuration Reference You can set parameters for the SLQ4A board on the T2000. 5.13.8 Technical Specifications The technical specifications of the SLQ4A board cover the optical interface specifications, board dimensions, weight and power consumption.
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Reference clock
Cross-connect unit
622Mbit/s 622Mbit/s
O/E O/E
S P I
622Mbit/s
CDR
622Mbit/s
K1 and K2 insertion/extration
622Mbit/s
K1 and K2
Cross-connect unit
....
622Mbit/s 622Mbit/s
....
622Mbit/s
Cross-connect unit A
RST
622Mbit/s 622Mbit/s
MST
MSA
HPT
High speed bus Cross-connect unit B
O/E O/E
S P I
CDR
SCC unit
+5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
Auxiliary Unit
The auxiliary unit consists of the logic control unit and the power supply module.
l
Logic Control Module The logic control module traces the clock signals, which are received from the active or standby cross-connect board, and the frame header signals. This module controls the laser
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and passes through the orderwire and ECC bytes between the two optical interface boards that form the ADM. This module also selects the clock frame headers from the active or standby cross-connect board.
l
Power Supply Module The power supply module provides the DC voltages required by the modules of the board.
SLQ4A
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the SLQ4A board, there are four pairs of optical interfaces. Table 5-55 lists the type and usage of the optical interfaces. Table 5-55 Optical interfaces of the SLQ4A board Interface IN1-IN4 OUT1OUT4 Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
The SLQ4A board can use the pluggable optical modules for easy maintenance.
J0 J1 C2
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15-8
15-8
3-2
3-2
3-2
23
28
28
28
34
8 8.2
8 8.2
8 10
8 10
13 10.5
Note: MLM stands for multi-longitudinal mode and SLM for single-longitudinal mode.
Mechanical Specifications
The mechanical specifications of the SLQ4A board are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
At normal ambient temperature (25), the maximum power consumption of the SLQ4A board is 17 W.
5.14 SL16
This section describes the SL16, a 1 x STM-16 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.14.1 Version Description The SL16 board has three versions, N1, N2 and N3. The difference among the three versions lies in the support for the TCM function and AU-3 services. 5.14.2 Function and Feature The SL16 board is used to receive and transmit 1 x STM-16 optical signals and to process the overhead. 5.14.3 Working Principle and Signal Flow The SL16 board consists of the O/E conversion module, MUX/DEMUX module, SDH overhead processing module, RST and so on. 5.14.4 Front Panel On the front panel of the SL16, there are indicators, interfaces, barcode, laser safety class label, and APD alarm label. 5.14.5 Valid Slots The SL16 board can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, and any of slots 1113 in the OptiX OSN 1500B subrack. 5.14.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SL16 indicates the optical interface type. 5.14.7 Board Configuration Reference You can use the T2000 to set parameters for the SL16. 5.14.8 Technical Specifications The technical specifications of the SL16 cover the optical interface specifications, board dimensions, weight and power consumption.
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Table 5-58 Version Description of the SL16 Item Functional version Difference Description The SL16 has three versions, N1, N2 and N3. The N1SL16 does not support the TCM function and AU-3 services. The N2SL16 supports the TCM function, and it can be configured with AU-3 services. The TCM function and AU-3 services cannot be configured on the N3SL16 at the same time. The N3SL16 supports the board version replacement function. Replaceability The N1SL16 and N2SL16 cannot be replaced by each other. When the TCM function and AU-3 services are not required, the N3SL16 can fully replace the N2SL16 and N1SL16. The N3SL16 supports the board version replacement function and can replace the N1SL16. After the N1SL16 is replaced, the N3SL16 is consistent with the N1SL16 in configuration and service status.
NOTE
The N3SL16 and N2SL16 board supports the TCM and AU3 services, which are not supported by the N1SL16 board. For this reason, when configuring MSP and SNCP, you cannot configure the N1SL16 board as the protection board if the working board is N3SL16 or N2SL16 configured with the TCM or AU3 service. Otherwise, the service may be interrupted due to the switching operation.
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SL16 Supports detection and query of the information on the optical module. The optical interface supports the function of setting the on/off state of the laser and the ALS function. Supports VC-12, VC-3, and VC-4 services and VC4-4c, VC4-8c, and VC4-16c concatenation services. Supports AU-3 services.
Overhead processing
Supports the processing of the SOH of the STM-16 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
N2SL16/N3SL16 Supports the setting and query of the REG working mode. Supports the two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, SNCP, SNCTP and SNCMP. Supports the optical-path-shared MSP and SNCP protection. Processes two sets of K bytes. One SL16 board supports a maximum of two MSP protection rings.
Maintenance feature
Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. Supports the PRBS function.
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Figure 5-35 Block diagram for the working principle of the SL16
155 MHz
Reference clock
Cross-connect unit
2.488 Gbit/s
2.488 Gbit/s
16 x 155 Mbit/s
K1 and K2 insertion/extration
K1 and K2
Cross-connect unit
O/E S P I O/E
DEMUX
high speed bus 2.488 Gbit/s 16 x 155 Mbit/s Cross-connect unit A
2.488 Gbit/s
RST
MST
MSA
HPT
high speed bus Cross-connect unit B SCC unit
MUX
5V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
In the receive direction, it converts the received optical signals into electrical signals. In the transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the function to shut down the laser.
MUX/DEMUX Module
l
In the receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In the transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In the receiving direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, and BIP-8 errored block count. In the transmitting direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In the receiving direction, MST performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection.
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MST
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In the transmitting direction, MST performs calculation and insertion of BIP-24, insertion of MS_REI MS_RDI and MS_AIS. Provides extraction or insertion of K1 byte and K2 byte. In the receiving direction, MSA performs AU4 pointer interpretation, LOP and AIS detection, pointer justification. In the transmitting direction, MSA performs AUG assembly, AU-4 pointer generation, and AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
MSA
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Tracing the clock signal from the active and the standby cross-connect units. Implements laser controlling function. Realizes the pass-through of orderwire and ECC bytes between the paired slots constituting the ADM when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
l l
This module provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. This module also provides protection for the board +3.3V power supply.
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APD
Receiver MAX:-9dBm
OUT
IN
SL16
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SL16. Table 5-60 lists the type and usage of the optical interfaces. Table 5-60 Optical interfaces of the SL16 Interface IN OUT
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Interface Type LC LC
J0 J1 C2
Table 5-62 Specifications of the optical interfaces of the SL16 Item Nominal bit rate Optical Interface Type Optical source type Working wavelengt h (nm) Launched optical power (dBm) Receiver sensitivity (dBm) Overload optical power (dBm) Min. extinction ratio (dB) Specification 2488320 kbit/s L-16.2 L-16.2Je V-16.2Je (BA) U-16.2Je (BA+PA)
SLM 15001580
SLM 15301560
SLM 15301565
SLM 1550.12
2 to +3
5 to 7
2 to +3 (without BA) 28
13 to 15 (with BA)
2 to +3 (without BA and PA) 28 (without PA and BA) 9 (without PA and BA) 8.2
15 to 18 (with BA)
28
28
32 (with PA)
10 (with PA)
8.2
8.2
8.2
Note: The optical interface of the Le-16.2 type is the same as the optical interface of the L-16.2Je type. The launched optical power of the optical interface of the V-16.2Je type is measured when the booster amplifer (BA) is added. The launched optical power of the optical interfaces of the V-16.2Je and U-16.2Je types ranges from 2 dBm to 3 dBm when no BA is added.
Table 5-63 Specifications of the ITU-T G.692-compliant optical interfaces that output standard wavelengths Item Nominal bit rate Dispersion limit (km) Mean launched optical power (dBm) Receiver sensitivity (dBm)
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Item Min. overload (dBm) Max. allowed dispersion (ps/nm) Min. extinction ratio (dB)
Mechanical Specifications
The mechanical specifications of the SL16 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1SL16 is 20 W. In the normal temperature (25), the maximum power consumption of the N2SL16 is 20 W. In the normal temperature (25), the maximum power consumption of the N3SL16 is 22 W.
5.15 SL16A
This section describes the SL16A, a 1 x STM-16 optical interface board, in terms of the version, function, working principle, front panel and specifications. 5.15.1 Version Description The SL16A board has three versions, N1, N2 and N3. The difference among the three versions lies in the support for the TCM function. 5.15.2 Function and Feature The SL16A board is used to receive and transmit 1 x STM-16 optical signals, to process the overhead bytes, and to perform the MSP protection. 5.15.3 Working Principle and Signal Flow The SL16A board consists of the O/E conversion module, MUX/DEMUX module, SDH overhead processing module, RST and so on. 5.15.4 Front Panel On the front panel of the SL16A, there are indicators, interfaces, barcode, laser safety class label, and APD alarm label. 5.15.5 Valid Slots The SL16A can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The SL16A can be housed in any of slots 1113 in the OptiX OSN 1500B subrack.
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5.15.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the SL16A indicates the optical interface type. 5.15.7 Board Configuration Reference You can use the T2000 to set the J0 parameter for the SL16A. 5.15.8 Technical Specifications The technical specifications of the SL16A cover the optical interface specifications, board dimensions, weight and power consumption.
NOTE
The N3SL16A and N2SL16A board supports the TCM and AU3 services, which are not supported by the N1SL16A board. For this reason, when configuring MSP and SNCP, you cannot configure the N1SL16A board as the protection board if the working board is N3SL16A or N2SL16A configured with the TCM or AU3 service. Otherwise, the service may be interrupted due to the switching operation.
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Table 5-65 Functions and features of the SL16A Function and Feature Basic function Specification of the optical interface Specification of the optical module SL16A Transmit and receive 1 x STM-16 optical signals. Supports optical interfaces of the I-16, S-16.1, L-16.1, and L-16.2 types. The optical interfaces comply with ITU-T G.957 and ITU-T G.692 in features. Supports detection and query of the information on the optical module. The optical interface supports the function of setting the on/off state of the laser and the ALS function. Supports the usage and monitoring of the SFP pluggable optical module. Service processing Overhead processing Supports VC-12, VC-3, and VC-4 services and VC4-4c, VC4-8c, and VC4-16c concatenation services. Supports the processing of the SOH bytes of the STM-16 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0 bytes. Alarm and performance event Specifications of the REG Protection scheme Provides rich alarms and performance events. The N2SL16A and N3SL16A support the setting and query of the REG working mode. Supports the two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, SNCP, SNCTP and SNCMP. Processes two sets of the K bytes.Supports the optical-path-shared MSP and SNCP protection. Maintenance feature Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. Supports AU-3 services.
Figure 5-37 Block diagram for the working principle of the N1SL16A and N2SL16A
155 MHz
Reference clock
Cross-connect unit
2.488 Gbit/s
2.488 Gbit/s
16 x 155 Mbit/s
K1 and K2
K1 and K2 insertion/extration
Cross-connect unit
O/E S P I O/E
DEMUX
high speed bus 2.488 Gbit/s 16 x 155 Mbit/s Cross-connect unit A
2.488 Gbit/s
RST
MST
MSA
HPT
high speed bus Cross-connect unit B SCC unit
MUX
5V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
Figure 5-38 shows the block diagram for the working principle of the N3SL16A. Figure 5-38 Block diagram for the working principle of the N3SL16A
155 MHz
Reference clock
Cross-connect unit
2.488 Gbit/s
2.488 Gbit/s
16 x 155 Mbit/s
K1 and K2
K1 and K2 insertion/extration
Cross-connect unit
O/E S P I O/E
DEMUX
high speed bus 2.488 Gbit/s 16 x 155 Mbit/s Cross-connect unit A
2.488 Gbit/s
RST
MST
MSA
HPT
high speed bus Cross-connect unit B SCC unit
MUX
5V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Fuse
+3.3 V
In the receive direction, it converts the received optical signals into electrical signals. In the transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission.
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The SPI detects the R_LOS alarm and provides the function to shut down the laser.
MUX/DEMUX Module
l
In the receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In the transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In the receiving direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, and BIP-8 errored block count. In the transmitting direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In the receiving direction, MST performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In the transmitting direction, MST performs calculation and insertion of BIP-24, insertion of MS_REI MS_RDI and MS_AIS. Provides extraction or insertion of K1 byte and K2 byte. In the receiving direction, MSA performs AU4 pointer interpretation, LOP and AIS detection, pointer justification. In the transmitting direction, MSA performs AUG assembly, AU-4 pointer generation, and AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
MST
MSA
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Tracing the clock signal from the active and the standby cross-connect units. Implements laser controlling function. Realizes the pass-through of orderwire and ECC bytes between the paired slots constituting the ADM when the CXL is not online.
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Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
This module provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. This module also provides protection for the board +3.3V power supply.
SL16A
STAT ACT PROG SRV
APD
Receiver MAX:-9dBm
OUT
IN
SL16A
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Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SL16A. Table 5-66 lists the type and usage of the optical interfaces. Table 5-66 Optical interfaces of the SL16A Interface IN OUT Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
Feature Code 01
02
S-16.1
03
L-16.1
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Feature Code 04
MLM 12661360
SLM 12601360
SLM 12801335
SLM 15001580
10 to 3
5 to 0
2 to +3
2 to +3
18
18
27
28
5-111
Mechanical Specifications
The mechanical specifications of the SL16A are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg):
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1SL16A and N2SL16A are 20 W. In the normal temperature (25), the maximum power consumption of the N3SL16A is 17 W.
5.16 SF16
This section describes the SF16, a 1 x STM-16 optical interface board with the out-band FEC function, in terms of the version, function, working principle, front panel and specifications. 5.16.1 Version Description The functional version of the SF16 board is N1. 5.16.2 Function and Feature The SF16 board is used to receive and transmit one-channel OTU1 (2.666 Gbit/s, FEC) optical signals and to process the overhead. 5.16.3 Working Principle and Signal Flow The SF16 consists of the O/E conversion module, MUX/DEMUX module, FEC module, SDH overhead processing module and so on. 5.16.4 Front Panel On the front panel of the SF16, there are indicators, interfaces, barcode and laser safety class label. 5.16.5 Valid Slots The SF16 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The SF16 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 5.16.6 Board Configuration Reference
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You can use the T2000 to set parameters for the SF16. 5.16.7 Technical Specifications The technical specifications of the SF16 cover the optical interface specifications, board dimensions, weight and power consumption.
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SF16 Not supports. Supports the two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, SNCP, SNCTP and SNCMP. Supports the optical-path-shared MSP and SNCP protection. Processes two sets of K bytes. One SF16 board supports a maximum of two MSP protection rings.
Maintenance feature
Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
Reference clock
Cross-connect unit
2.666 Gbit/s
O/E S P I O/E
2.666 Gbit/s
DEMUX
16x166 Mbit/s
16x155 Mbit/s
K1 and K2 insertion/extration
K1 and K2
Cross-connect unit
FEC
2.666 Gbit/s 16x166 Mbit/s 16x155 Mbit/s
Cross-connect unit
2.666 Gbit/s
RST
MST
MSA
HPT
high speed bus DCC Cross-connect unit
MUX
SDH overhead processing module
SCC unit
5V +1.8 V
DC/DC converter
DC/DC converter
Fuse Fuse
In the receive direction, the module converts the received 2.666 Gbit/s FEC optical signals into electrical signals. In the transmit direction, the module converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides function to shut down the laser.
MUX/DEMUX Module
l
In the receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovers the clock signal at the same time. In the transmit direction, the MUX part multiplexes the parallel electrical signals received from the FEC module into high rate electrical signals.
FEC Module
l
In the downstream direction, the FEC encoding and decoding module receives 2.488 Gbit/ s SDH signals, which are sent by the SDH overhead processing chip. After frame search, FEC encoding, data packets encapsulation and scrambling, the 2.488 Gbit/s SDH signals are converted to 2.666 Gbit/s signals and then transmitted to the MUX module. In the upstream direction, signals take the reverse process. The FEC encoding and decoding module receives the 2.666 Gbit/s signals from the DEMUX module. After frame search, FEC encoding, data packets encapsulation and scrambling in the FEC module, the 2.488 Gbit/s signals are recovered and then transmitted to SDH overhead processing chip. The frame format of the 2.666 Gbit/s signals complies with ITU G.709. The FEC processing module connects to the communication and control unit through a CPU bus. The CPU controls working modes of the FEC module by configuring the internal register. The working mode can be regenerator mode, that is, REG mode. The CPU can monitor the performance through the internal register.
RST
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0), mismatch detection, BIP-8 errored block count. In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In the receive direction, MST performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification.
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MST
MSA
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In the transmit direction, MSA performs AUG assembly, AU-4 pointer generation, and AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring) UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
HPT
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect unit. Controls the laser. Realizes the pass-through of orderwire and ECC bytes between the paired slots constituting the ADM when the CXL is not online. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
l l
DC/DC Converter
It provides the board with required DC voltages. It converts the 48 V/60 V power supply to the following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3V power supply.
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SF 16
STAT ACT PROG SRV
OUT
IN
SF16
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SF16. Table 5-70 lists the type and usage of the optical interfaces.
NOTE
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Table 5-70 Optical interfaces of the SF16 Interface IN OUT Interface Type LC LC Usage Receives optical signals. Transmits optical signals.
J0 J1 C2
Item Wavelength (nm) Launched optical power (dBm)b Launched optical power (dBm)c Receiver sensitivity (dBm)b Receiver sensitivity (dBm)d Overload optical power (dBm)d Min. extinction ratio (dB)b
a: The numbers in the brackets indicate the specifications. For example, BA (14) indicates that the optical power amplified by the BA is 14 dBm. "FEC+BA+PA+RA" indicates that the optical interface is used with the FEC, PA, Raman amplifier and BA. b: The specifications are for the optical module itself rather than for the amplifier. c: The specifications are for the BA. d: The specifications are for the PA.
Table 5-72 Specifications of the ITU-T G.692-compliant optical interfaces that output standard wavelengths Item Nominal bit rate Dispersion limit (km) Mean launched optical power (dBm) Receiver sensitivity (dBm) Min. overload (dBm) Max. allowed dispersion (ps/nm) Min. extinction ratio (dB) Specification 2666057.143 kbit/s 640 5 to 1 28 9 10880 8.2
Mechanical Specifications
The mechanical specifications of the SF16 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
Power Consumption
In the normal temperature (25), the maximum power consumption of the SF16 is 26 W.
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About This Chapter
This chapter describes the PDH processing boards for the E1/T1, E3/T3, E4/STM-1, and DDN signals. 6.1 PL1 This section describes the PL1, a 16 x E1 processing board, in terms of the version, function, working principle, front panel and specifications. 6.2 PD1 This section describes the PD1, a 32 x E1 processing board, in terms of the version, function, working principle, front panel and specifications. 6.3 PQ1 This section describes the PQ1, a 63 x E1 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.4 PQM This section describes the PQM, a 63 x E1/T1 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.5 PL3 This section describes the PL3, a 3 x E3/T3 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.6 PL3A This section describes the PL3A, a 3 x E3/T3 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.7 PD3 This section describes the PD3, a 6 x E3/T3 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.8 PQ3 This section describes the PQ3, a 12 x E3/T3 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.9 DX1
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This section describes the DX1, a DDN interface convergence board, in terms of the version, function, principle, front panel, configuration and specifications. 6.10 DXA This section describes the DXA, a DDN convergence board, in terms of the version, function, principle, front panel, configuration and specifications. 6.11 SPQ4 This section describes the SPQ4, a 4 x E1/STM-1 processing board, in terms of the version, function, working principle, front panel and specifications.
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6.1 PL1
This section describes the PL1, a 16 x E1 processing board, in terms of the version, function, working principle, front panel and specifications. 6.1.1 Version Description The functional version of the PL1 is R1. 6.1.2 Function and Feature The PL1 is used to directly access and process E1 electrical signals, to process the overhead, to report alarms and performance events and to provide the maintenance features. 6.1.3 Working Principle and Signal Flow The PL1 consists of the PPI, E1 mapping/demapping, interface conversion module, communication and control module and so on. 6.1.4 Front Panel On the front panel of the PL1, there are indicators and interfaces. 6.1.5 Valid Slots The PL1 can be housed in any of slots 69 of the OptiX OSN 1500A subrack or the OptiX OSN 1500B subrack. 6.1.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the PL1 indicates the interface impedance type. 6.1.7 Board Configuration Reference You can use the T2000 to set parameters for the PL1. 6.1.8 Technical Specifications The technical specifications of the PL1 cover the optical interface specifications, board dimensions, weight and power consumption.
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Function and Feature Overhead processing Alarm and performance event Maintenance feature
PL1 Supports the transparent transmission and termination of POH bytes at the VC-12 level, such as the J2 byte. Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports inloop and outloop for electrical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. Supports the PRBS function.
E1
LIU P P I LIU
6 x 2 Mbit/s
155 Mbit/s
E1
E1 mapping/ demapping
6 x 2 Mbit/s
155 Mbit/s
Cross-connect unit A
Cross-connect unit B
+2.5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
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Figure 6-2 shows the block diagram of the E1 mapping/demapping. Figure 6-2 Block diagram of the E1 mapping/demapping
E1 mapping/demapping E1 STM-1
LPA
LPT
HPA
HPT
TU-AIS/TU-LOP Detector
E1
STM-1
LPA
LPT
HPA
HPT
PPI
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module:
l l l
Encodes and decodes signals. Recovers data and clock. Processes the PDH LOS signals.
E1 mapping/demapping
l l
LPA The 2 Mbit/s plesiochronous stream is inserted in a VC-12 container to be adapted so as to be transported into the synchronous network for check of the PDH AIS. LPT The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the VC-12 container and POH. The latter contains nine octets equally distributed within the frame bytes for VC-12: V5, J2, N2, and K4. HPA HPA generates and processes channel level TU-PTR. In the receive direction, the signals are split into VC-12s, which are located and isolated in TU-12. TU-PTR is processed. TUAIS and TU-LOP alarms are monitored. In the transmit direction, VC-12s are located precisely and added with TU-PTR. 63 TUG-3s are multiplexed into a VC-4 by bytes interleaving. The sequence is: TUG2->TUG3->VC-4. HPT
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l l
l l
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The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the C4 container and POH. MST and RST These two functions are necessary to create a proprietary STM1 signal in order to interface the E1 mapping/demapping block with the multiplex unit.
l l
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Selects the clock and frame header from the active or the standby cross-connect units. Control the indicator on the board.
DC/DC converter
It provides the board with required DC voltages. It converts the 48 V/60 V power supply to the following voltages: + 2.5 V, + 3.3 V, + 1.8 V. In addition, protection for +3.3 V power are provided to the board.
PL1
STAT ACT PROG SRV
1-16
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Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are 16 2mmHM interfaces on the front panel of the PL1. Table 6-2 lists the type and usage of the interfaces. Table 6-2 Interfaces on the front panel of the PL1 Interface 18 916 Interface Type 2mmHM 2mmHM Usage Receives the first eight channels (18) of E1 signals. Receives the last eight channels (916) of E1 signals.
2048 kbit/s
HDB3
Mechanical Specifications
The mechanical specifications of the PL1 are as follows:
l l
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.5
Power Consumption
In the normal temperature (25), the maximum power consumption of the PL1 is 7 W.
6.2 PD1
This section describes the PD1, a 32 x E1 processing board, in terms of the version, function, working principle, front panel and specifications. 6.2.1 Version Description The PD1 has two versions, R1 and R2. The two versions have different functions. 6.2.2 Function and Feature The PD1 is used to process E1 signals and the overhead, to report alarms and performance events, and to provide the maintenance features and TPS protection. 6.2.3 Working Principle and Signal Flow
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The PD1 consists of the PPI, E1 mapping/demapping, interface conversion module, communication and control module and so on. 6.2.4 Front Panel On the front panel of the PD1, there are indicators. 6.2.5 Valid Slots The PD1 must be used with the L75S or L12S. 6.2.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the PD1 indicates the interface impedance type. 6.2.7 TPS Protection for the Board The PD1 supports the 1:N TPS protection. 6.2.8 Board Configuration Reference You can use the T2000 to set parameters for the PD1. 6.2.9 Technical Specifications The technical specifications of the PD1 cover the electrical interface specifications, board dimensions, weight and power consumption.
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Table 6-6 Functions and features of the PD1 Function and Feature Basic function Service processing PD1 R1PD1 Processes 32 x E1 signals. Accesses and processes 32 x E1 electrical signals when used with the interface board. R2PD1 Processes 32 x E1 signals. Accesses and processes 32 x E1 electrical signals when used with the interface board. Supports the E13 function, which is used to converge E1 services into E3 services.
Supports the transparent transmission and termination of the POH bytes at the VC-12 level, such as the J2 byte. Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports inloop and outloop for the electrical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. Supports the PRBS function.
Protection scheme
Supports the TPS protection when used with the electrical interface switching board.
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E1
LIU P P I LIU
6 x 2 Mbit/s
155 Mbit/s
E1
E1 mapping/ demapping
6 x 2 Mbit/s
155 Mbit/s
Cross-connect unit A
Cross-connect unit B
+2.5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Figure 6-5 shows the block diagram of the E1mapping/ demapping. Figure 6-5 Block diagram of the E1 mapping/ demapping
E1 mapping/demapping E1 STM-1
LPA
LPT
HPA
HPT
TU-AIS/TU-LOP Detector
E1
STM-1
LPA
LPT
HPA
HPT
PPI
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module:
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Encodes and decodes signals. Recovers data and clock. Processes the PDH LOS signals.
E1 mapping/demapping
l l
LPA The 2 Mbit/s plesiochronous stream is inserted in a VC-12 container to be adapted so as to be transported into the synchronous network for check of the PDH AIS. LPT The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the VC-12 container and POH. The latter contains nine octets equally distributed within the frame bytes for VC-12: V5, J2, N2, and K4. HPA HPA generates and processes channel level TU-PTR. In the receive direction, the signals are split into VC-12s, which are located and isolated in TU-12. TU-PTR is processed. TUAIS and TU-LOP alarms are monitored. In the transmit direction, VC-12s are located precisely and added with TU-PTR. 63 TUG-3s are multiplexed into a VC-4 by bytes interleaving. The sequence is: TUG2->TUG3->VC-4. HPT The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the C4 container and POH. MST and RST These two functions are necessary to create a proprietary STM1 signal in order to interface the E1 mapping/demapping block with the multiplex unit.
l l
l l
l l
l l
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Selects the clock and frame header from the active or the standby cross-connect units. Control the indicator on the board.
DC/DC converter
It provides the board with required DC voltages. It converts the 48 V/60 V power supply to the following voltages: + 2.5 V, + 3.3 V, + 1.8 V. In addition, protection for +3.3 V power are provided to the board.
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PD1
STAT ACT PROG SRV
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PD1. In the OptiX OSN 1500A subrack, the PD1 is used with the L75S or L12S, which provides 75ohm or 120-ohm E1 interfaces. For details, see the sections that describe the L75S and L12S. In the OptiX OSN 1500B subrack, the PD1 is used with the D75S or D12S, which provides 75ohm or 120-ohm E1 interfaces. For details, see the sections that describe the D75S and D12S.
Table 6-7 Valid slots for the PD1 and corresponding slots for the L75S and L12S in the OptiX OSN 1500A subrack Valid Slot for the PD1 Slot 12 Corresponding Slot for the L75S and L12S Slot 7 (116 channels services) Slot 6 (1732 channels services)
NOTE
Slot 2 can house a protection board of the TPS protection. The board housed in slot 2 protects the board housed in slot 12.
In the OptiX OSN 1500B subrack, the PD1 can be housed in any of slots 13, 68 and 1113. Table 6-8 lists the valid slots for the PD1 and the corresponding slots for the D75S and D12S. Table 6-8 Valid slots for the PD1 and corresponding slots for the D75S and D12S in the OptiX OSN 1500B subrack Valid Slot for the PD1 Slot 2 Slot 3 Slots 7 and 12 Slots 8 and 13 Corresponding Slot for the D75S and D12S Slot 14 Slot 16 Slot 15 Slot 17
NOTE
Boards housed in slots 7 and 12 share the interface board housed in slot 15. The boards housed in slots 7 and 12 cannot be used with the interface board housed in slot 15 to add or drop services at the same time. Boards housed in slots 8 and 13 share the interface board housed in slot 17. The boards housed in slots 8 and 13 cannot be used with the interface board housed in slot 17 to add or drop services at the same time. Slot 1 can house a protection board of the TPS protection. The board housed in slot 1 protects the boards housed in slots 2 and 3. Slot 11 can house a protection board of the TPS protection. The board housed in slot 11 protects the boards housed in slots 12 and 13. Slot 6 can house a protection board of the TPS protection. The board housed in slot 6 protects the boards housed in slots 7 and 8.
l l l
Table 6-9 Relation between the board feature code and the interface impedance type Board SSR1PD1A01, SSR2PD1A01 SSR1PD1B01, SSR2PD1B01 Feature Code A01 B01 Interface Impedance Type 75 ohms 120 ohms
Protection Principle
In the OptiX OSN 1500A subrack, used with the L75S or L12S, two PD1 boards can get 1:1 TPS protection. Figure 6-7 shows the principle for the TPS protection of the PD1. Figure 6-7 Principle of the TPS protection for the PD1 in the OptiX OSN 1500A subrack
E1protection bus
S L O T 6
S L O T 7
L75S
S L O T 2
S L O T 12
Fail
L75S
E1 service bus
PD1
In the OptiX OSN 1500B subrack, used with the D75S or D12S, the PD1 boards can get 1:N (12) TPS protection. Figure 6-8 shows the principle of the TPS protection for the PD1.
Protection
PD1
Working
TPS switching control bus
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Figure 6-8 Principle of the TPS protection for the PD1 in the OptiX OSN 1500B subrack
E1 protection bus
D75S D75S
Working
PD1
Working
PD1
When detecting a failure in the working PD1 board, the cross-connect board issues a command to switch the services from the faulty PD1 to the protection PD1. In this way, services are protected.
Hardware Configuration
In the OptiX OSN 1500A subrack, PD1 boards can be housed in the half-width slots to realize the 1:1 TPS protection. Figure 6-9 shows the slot configuration for the 1:1 TPS protection for the PD1. Figure 6-9 Slot configuration for the 1:1 TPS protection for the PD1 in the OptiX OSN 1500A subrack
Slot 1 Slot 20 FAN PD1(P) Slot 2 Slot 3 Slot 4 Slot 5 Slot 11 Slot 12 PD1(W) Slot 13 CXL16/4/1 CXL16/4/1 Slot 6 L75S(17~32) Slot 7 L75S(1~16) Slot 8 Slot 9 Slot 10 EOW AUX
Table 6-10 shows the slot configuration for the 1:2 TPS protection for the PD1 in the OptiX OSN 1500B subrack.
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Table 6-10 Slot configuration for the 1:2 TPS protection for the PD1 in the OptiX OSN 1500B subrack Board PD1 (protection) PD1 (working) D75S/D12S Protection Group Before the Slot Division Slot 6 Slots 7 and 8 Slots 15 and 17 Protection Group After the Slot Division Slot 1 Slots 2 and 3 Slots 14 and 16 Slot 11 Slots 12 and 13 Slots 15 and 17 Slot 6 Slots 7 and 8 Slots 15 and 17
The two protection groups that contain slots 6 and 11 share the protection bus and thus cannot coexist. Before the slots are divided, the OptiX OSN 1500B supports one group of TPS protection for E1 services. After the slots are divided, when Q2CXL and Q3CXL are uesd, the OptiX OSN 1500B supports a maximum of two TPS protection groups for E1 services. when R1CXL is uesd, the OptiX OSN 1500B supports a maximum of one TPS protection group for E1 services.
Mechanical Specifications
The mechanical specifications of the PD1 are as follows:
l l
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg)
0.5 (R1PD1)
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0.56 (R2PD1)
Power Consumption
In the normal temperature (25), the maximum power consumption of the R1PD1 is 15 W. In the normal temperature (25), the maximum power consumption of the R2PD1 is 10.4 W.
6.3 PQ1
This section describes the PQ1, a 63 x E1 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.3.1 Version Description The PQ1 has two versions, R1 and R2. The two versions have different functions. 6.3.2 Function and Feature The PQ1 can be used to process E1 signals and the overhead, to report alarms and performance events, to provide the maintenance feature and the TPS protection. 6.3.3 Working Principle and Signal Flow The PQ1 consists of the PPI, E1/T1 mapping/demapping, interface conversion module and so on. 6.3.4 Front Panel On the front panel of the PQ1, there are indicators. 6.3.5 Valid Slots The PQ1 must be used with the D75S, D12S or D12B. 6.3.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the PQ1 indicates the interface impedance type. 6.3.7 TPS Protection for the Board The PQ1 supports the 1:N TPS protection. 6.3.8 Board Configuration Reference You can use the T2000 to set parameters for the PQ1. 6.3.9 Technical Specifications The technical specifications of the PQ1 cover the electrical interface specifications, board dimensions, weight and power consumption.
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Table 6-11 Version Description of the PQ1 Item Functional version Difference Description The PQ1 has two versions, N1 and N2. The N2PQ1 supports the E13 function and the board version replacement function. The N2PQ1 does not perform the tributary timing function. Replaceability When the tributary timing function is not required, the N1PQ1A can be replaced by the N2PQ1A. When the tributary timing function is not required, the N1PQ1B can be replaced by the N2PQ1B. NOTE: When the impedance of interfaces is ignored, the PQ1A (75 ohms) and PQ1B (100 ohms/120 ohms) are called PQ1 hereinafter.
Supports the transparent transmission and termination of the POH bytes at the VC-12, such as the J2 byte. Provides rich alarms and performance events for easy management and maintenance of the equipment.
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Supports inloop and outloop for electrical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. Supports the PRBS function.
Protection scheme
Supports the TPS protection when used with the interface board. When the working board is the PQ1, the protection board can be the PQM. In this way, the hybrid protection is provided.
E1/T1
LIU P P I LIU
155 Mbit/s
E1/T1
155 Mbit/s
Cross-connect unit A
Cross-connect unit B
+2.5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Figure 6-11 shows the block diagram of the E1/T1 mapping/ demapping.
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LPA
LPT
HPA
HPT
TU-AIS/TU-LOP Detector
E1/T1
STM-1
LPA
LPT
HPA
HPT
PPI
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module:
l l l
Encodes and decodes signals. Recovers data and clock. Processes the PDH LOS signals.
E1/T1 mapping/demapping
l l
LPA The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be adapted so as to be transported into the synchronous network for check of the PDH AIS. LPT The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the VC-12 container and POH. The latter contains nine octets equally distributed within the frame bytes for VC-12: V5, J2, N2, and K4. HPA HPA generates and processes channel level TU-PTR. In the receive direction, the signals are split into VC-12s, which are located and isolated in TU-12. TU-PTR is processed. TUAIS and TU-LOP alarms are monitored. In the transmit direction, VC-12s are located precisely and added with TU-PTR. 63 TUG-3s are multiplexed into a VC-4 by bytes interleaving. The sequence is: TUG2->TUG3->VC-4. HPT
l l
l l
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The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the C4 container and POH. MST and RST These two functions are necessary to create a proprietary STM1 signal in order to interface the E1/T1 mapping/demapping block with the multiplex unit.
l l
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Selects the clock and frame header from the active or the standby cross-connect units. Control the indicator on the board.
DC/DC converter
It provides the board with required DC voltages. It converts the 48 V/60 V power supply to the following voltages: + 2.5 V, + 3.3 V, + 1.8 V. In addition, protection for +3.3 V power are provided to the board.
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PQ1
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PQ1. The D75S, D12S or D12B provides 75-ohm or 120-ohm E1/T1 interfaces for the PQ1. For details, see the sections that describe the D75S, D12S and D12B.
In the OptiX OSN 1500B subrack, the PQ1 can be housed in any of slots 1113, and must be used with the D75S, D12S or D12B. Table 6-13 lists the valid slots for the PQ1 and corresponding slots for the D75S, D12S or D12B. Table 6-13 Valid slots for the PQ1 and corresponding slots for the D75S, D12S or D12B in the OptiX OSN 1500B subrack Valid Slot for the PQ1 Slot 12 Corresponding Slot for the D75S, D12S and D12B Slot 14 (132 channels of services) Slot 15 (3363 channels of services) Slot 13 Slot 16 (132 channels of services) Slot 17 (3363 channels of services)
NOTE
l l
Slot 11 can house a protection board of the TPS protection. The board housed in slot 11 protects the boards housed in slots 12 and 13. If the interface board for the boards housed in slot 12 and 13 is the D12B, the boards housed in slot 12 and 13 cannot get the TPS protection.
Protection Principle
In the OptiX OSN 1500B subrack, used with the D75S or D12S, the PQ1 can get the 1:N (2) TPS protection. Figure 6-13 shows the principle of the TPS protection for the PQ1.
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Figure 6-13 Principle of the TPS protection for the PQ1 in the OptiX OSN 1500B subrack
E1 protection bus
S S L L O O T T 14 15
S L O T 16
S L O T 17
D75S D75S
D75S D75S
E1 service bus
SLOT 11
SLOT 12
SLOT 13
Fail
When detecting a failure in the working PD1 board, the cross-connect board issues a command to switch the services from the faulty PQ1 to the protection PQ1. In this way, services are protected.
Hardware Configuration
Table 6-15 lists the slot configuration for the 1:2 TPS protection for the PQ1 in the OptiX OSN 1500B subrack. Table 6-15 Slot configuration for the 1:2 TPS protection for the PQ1 in the OptiX OSN 1500B subrack Working Board PQ1A (75 ohms) PQ1B (120 ohms) Protection Board PQ1A (75 ohms) PQ1B (120 ohms) or PQM Slot Slot 11 can house the protection board. The board in slot 11 protects the boards in slots 12 and 13. Figure 6-14 shows the slot configuration for the 1:2 TPS protection for the PQ1.
Protection
Working
Working
TPS switching control bus
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Figure 6-14 Slot configuration for 1:2 TPS protection of the PQ1
Slot 14 Slot 15 Slot 16 Slot 17 Slot 11 Slot 20 Slot 12 Slot 13 Slot 4 Slot 5 D75S D75S D75S D75S Slot 19 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 EOW AUX PIU Slot 18 PIU
FAN
Mechanical Specifications
The mechanical specifications of the PQ1 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1PQ1 is 19 W. In the normal temperature (25), the maximum power consumption of the N2PQ1 is 13 W.
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6.4 PQM
This section describes the PQM, a 63 x E1/T1 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.4.1 Version Description The functional version of the PQM board is N1. 6.4.2 Function and Feature The PQM is used to process E1/T1 signals and the overhead, to report alarms and performance events, and to provide the maintenance features and TPS protection. 6.4.3 Working Principle and Signal Flow The PQM consists the PPI, E1/T1 mapping/demapping, interface conversion module, communication and control module and so on. 6.4.4 Front Panel On the front panel of the PQM, there are indicators. 6.4.5 Valid Slots The OptiX OSN 1500A does not support the PQM board. 6.4.6 TPS Protection for the Board The PQM supports the 1:N TPS protection. 6.4.7 Board Configuration Reference You can use the T2000 to set parameters for the PQM. 6.4.8 Technical Specifications The technical specifications of the PQM cover the electrical interface specifications, board dimensions, weight and power consumption.
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Function and Feature Overhead processing Alarm and performance event Maintenance feature
PQM Supports the transparent transmission and termination of the POH bytes at the VC-12 level, such as the J2 byte. Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports inloop and outloop for electrical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. Supports the PRBS function.
Protection scheme
When used with the interface board, the PQM supports the TPS protection. When the working board is the PQ1, the protection board can be the PQM. In this way, the hybrid protection is provided.
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E1/T1
LIU P P I LIU
155 Mbit/s
E1/T1
155 Mbit/s
Cross-connect unit A
Cross-connect unit B
+2.5 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Figure 6-16 shows the block diagram of the E1/T1 mapping/ demapping. Figure 6-16 Block diagram of the E1/T1 mapping/ demapping
E1/T1 mapping/demapping E1/T1 STM-1
LPA
LPT
HPA
HPT
TU-AIS/TU-LOP Detector
E1/T1
STM-1
LPA
LPT
HPA
HPT
PPI
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module:
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Encodes and decodes signals. Recovers data and clock. Processes the PDH LOS signals.
E1/T1 mapping/demapping
l l
LPA The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be adapted so as to be transported into the synchronous network for check of the PDH AIS. LPT The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the VC-12 container and POH. The latter contains nine octets equally distributed within the frame bytes for VC-12: V5, J2, N2, and K4. HPA HPA generates and processes channel level TU-PTR. In the receive direction, the signals are split into VC-12s, which are located and isolated in TU-12. TU-PTR is processed. TUAIS and TU-LOP alarms are monitored. In the transmit direction, VC-12s are located precisely and added with TU-PTR. 63 TUG-3s are multiplexed into a VC-4 by bytes interleaving. The sequence is: TUG2->TUG3->VC-4. HPT The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the C4 container and POH. MST and RST These two functions are necessary to create a proprietary STM1 signal in order to interface the E1/T1 mapping/demapping block with the multiplex unit.
l l
l l
l l
l l
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Selects the clock and frame header from the active or the standby cross-connect units. Control the indicator on the board.
DC/DC converter
It provides the board with required DC voltages. It converts the 48 V/60 V power supply to the following voltages: + 2.5 V, + 3.3 V, + 1.8 V. In addition, protection for +3.3 V power are provided to the board.
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PQM
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PQM.
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The D12S or D12B provides 100-ohm T1/E1 interfaces for the PQM. For details, see the sections that describe the D12S and D12B.
NOTE
l l
Slot 11 can house a protection board of the TPS protection. The board housed in slot 11 protects the boards housed in slots 12 and 13. If the interface board for the boards housed in slots 12 and 13 is the D12B, the boards housed in slots 12 and 13 cannot get the TPS protection.
Protection Principle
In the OptiX OSN 1500B, used with the D12S, the PQM can be configured into one 1:N (N 2) TPS protection group. Figure 6-18 shows the principle of the TPS protection for the PQM.
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Figure 6-18 Principle of the TPS protection for the PQM in the OptiX OSN 1500B subrack
S S L L O O T T 14 15
S L O T 16
S L O T 17
D12S
D12S
D12S
D12S
SLOT 11
SLOT 12
SLOT 13
Fail
When detecting a fault in the working PQM board, the cross-connect board issues a command to switch the services from the faulty PQM to the protection PQM. In this way, services are protected.
Hardware Configuration
Table 6-18 lists the slot configuration for the 1:2 TPS protection for the PQM in the OptiX OSN 1500B subrack. Table 6-18 Slot configuration for the 1:2 TPS protection for the PQM in the OptiX OSN 1500B subrack Working Board PQM (E1) PQM (T1) Protection Board PQM (E1) PQM (T1) Slot Slot 11 can house the protection board. The board in slot 11 protects the boards in slots 12 and 13. Figure 6-19 shows the slot configuration for the 1:2 TPS protection for the PQM.
Protection
Working
Working
TPS switching control bus
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Figure 6-19 Slot configuration for the 1:2 TPS protection for the PQM in the OptiX OSN 1500B subrack
Slot 14 Slot 15 Slot 16 Slot 17 Slot 11 Slot 20 Slot 12 Slot 13 Slot 4 Slot 5 D12S D12S D12S D12S Slot 19 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 EOW AUX PIU Slot 18 PIU
FAN
J2 byte V5 byte Tributary loopback Service loading indication Path service type
Mechanical Specifications
The mechanical specifications of the PQM are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the PQM is 22 W.
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6.5 PL3
This section describes the PL3, a 3 x E3/T3 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.5.1 Version Description The PL3 has two versions, N1 and N2. The two versions have different functions. 6.5.2 Function and Feature The PL3 can be used to process E3/T3 signals and the overhead, to report alarms and performance events, to provide the maintenance feature and the TPS protection. 6.5.3 Working Principle and Signal Flow The PL3 consists the PPI, E3/T3 mapping/demapping, interface conversion module, communication and control module and so on. 6.5.4 Front Panel On the front panel of the PL3, there are indicators. 6.5.5 Valid Slots The OptiX OSN 1500A does not support the PL3 board. 6.5.6 TPS Protection for the Board The PL3 supports the 1:N TPS protection. 6.5.7 Board Configuration Reference You can use the T2000 to set parameters for the PL3. 6.5.8 Technical Specifications The technical specifications of the PL3 cover the electrical interface specifications, board dimensions, weight and power consumption.
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E3/T3
LIU P P I LIU
6 x 34 Mbit/s/ 6 x 45 Mbit/s
2 x 155 Mbit/s
E3/T3
6 x 34 Mbit/s/ 6 x 45 Mbit/s
2 x 155 Mbit/s
Cross-connect unit A
Cross-connect unit B
+1.8 V
DC/DC converter
DC/DC converter
Fuse
OSC: Oscillator
Figure 6-21 shows the block diagram of the E3/T3 mapping/demapping. Figure 6-21 Block diagram of the E3/T3 mapping/demapping
E3/T3 mapping/demapping
E3/T3
LPA
LPT
HPA
HPT
STM-1
E3/T3
STM-1
LPA
LPT
HPA
HPT
LPA: Low order Path Adaptation HPA: High order Path Adaptation
LPT: Low order Path Termination HPT: High order Path Termination
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PPI
l
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module: Encodes and decodes signals. Recovers data and clock. Processes the A_LOS alarm.
l l l
E3/T3 mapping/demapping
l l
LPA The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted so as to be transported into the synchronous network. LPT The virtual container (VC-3) is formatted by lower order path termination (LPT). The VC-3 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the VC-3 container and POH. The latter contains nine octets equally distributed within the frame bytes for VC-3: J1, B3, C2, G1, F2, H4, F3, K3, and N1. HPA HPA generates and processes channel level TU-PTR. In the receive direction, the signals are split into VC-3s, which are located and isolated in TU-3. TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The sequence is: TU-3->TUG3->VC-4. HPT The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the C4 container and POH. MST and RST The functions are necessary to create a proprietary STM1 signal in order to connect the interface conversion module.
l l l
l l
l l
l l
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
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PL3
STAT ACT PROG SRV
PL3
Indicators
The following indicators are present on the front panel of the board:
l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit.
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Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PL3. The C34S, an electrical interface switching board, provides the E3/T3 interfaces for the PL3. For details, see the section that describes the D34S.
Protection Principle
In the OptiX OSN 1500B, used with the C34S and TSB8, the PL3 can be configured into one 1:1 TPS protection group. Figure 6-23 shows the principle of the TPS protection for the PL3.
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Figure 6-23 Principle of the TPS protection for the PL3 in the OptiX OSN 1500B subrack
3 xE3/T3
TSB8
C34S
SLOT 4/5
Protection PL3
Working PL3
Fail
SLOT12
SLOT13
Normal state When the working boards are running normally, the control switch of the C34S is in position 1 and services are directly accessed to the PL3 board.
Switching state When the working board detects a fault and requires a switching, the control switch of the C34S is shifted to position 2 and the control switch of the TSB8 is shifted to a corresponding position. In this way, the protection board protects the faulty working board.
Hardware Configuration
Table 6-22 lists the slot configuration for the 1:1 TPS protection for the PL3 in the OptiX OSN 1500B subrack. Table 6-22 Slot configuration for the 1:1 TPS protection for the PL3 in the OptiX OSN 1500B subrack Working Board PL3 (E3) PL3 (T3) Protection Board PL3 (E3)/PD3 (E3) PL3 (T3)/PD3 (T3) Slot If the working board is the PL3, the PD3 can be the protection board. Figure 6-24 shows the slot configuration for the 1:1 TPS protection for the PL3.
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Figure 6-24 Slot configuration for the 1:1 TPS protection for the PL3 in the OptiX OSN 1500B subrack
Slot 14 Slot 15 Slot 16 Slot 17 Slot 11 Slot 20 FAN Slot 12 Slot 13 Slot 4 Slot 5 Protection Working CXL16/4/1 CXL16/4/1 C34S TSB8 Slot 18 PIU
PIU
EOW AUX
As shown in Figure 6-24, the protection board housed in slot 12 protects the board housed in slot 13. Table 6-23 lists the slots for the PL3, C34S and TSB8. Table 6-23 Slots for the PL3, C34S and TSB8 in the OptiX OSN 1500B subrack Board PL3 (working) PL3/PD3 (protection) TSB8 C34S Protection Group Slot 13 Slot 12 Slot 14 Slot 16
J1 byte C2 byte Tributary loopback Service loading indication Path service type
Mechanical Specifications
The mechanical specifications of the PL3 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1PL3 is 15 W. In the normal temperature (25), the maximum power consumption of the N2PL3 is 12 W.
6.6 PL3A
This section describes the PL3A, a 3 x E3/T3 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.6.1 Version Description The PL3A board has two functional versions, N1 and N2. The difference between the two versions lies in the support for the E13/M13 function. 6.6.2 Function and Feature The PL3A can be used to process E3/T3 signals and the overhead, to report alarms and performance events, to provide the maintenance feature and the TPS protection. 6.6.3 Working Principle and Signal Flow The PL3A consists of the PPI, E3/T3 mapping/demapping, interface conversion module, communication and control module and so on. 6.6.4 Front Panel On the front panel of the PL3A, there are indicators and interfaces. 6.6.5 Valid Slots The PL3A can be housed in different slots in the OptiX OSN 1500A and OptiX OSN 1500B subracks 6.6.6 Board Configuration Reference You can use the T2000 to set parameters for the PL3A. 6.6.7 Technical Specifications The technical specifications of the PL3A cover the electrical interface specifications, board dimensions, weight and power consumption.
Table 6-24 Version description of the PL3A Item Functional version Difference Description The PL3A has two versions, N1 and N2. The N1PL3A does not support the E13/M13 function. The N2PL3A supports the E13/M13 function. The N2PL3A supports the board version replacement function and can replace the N1PL3A. After the N1PD3A is replaced, the N2PD3A is consistent with the N1PD3A in configuration and service status. Replaceability The N2PD3A can fully replace the N1PD3A.
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PL3A Supports inloop and outloop for electrical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. Supports the PRBS function.
E3/T3
LIU P P I LIU
6 x 34 Mbit/s/ 6 x 45 Mbit/s
2 x 155 Mbit/s
E3/T3
6 x 34 Mbit/s/ 6 x 45 Mbit/s
2 x 155 Mbit/s
Cross-connect unit A
Cross-connect unit B
+1.8 V
DC/DC converter
DC/DC converter
Fuse
OSC: Oscillator
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E3/T3
LPA
LPT
HPA
HPT
STM-1
E3/T3
STM-1
LPA
LPT
HPA
HPT
LPA: Low order Path Adaptation HPA: High order Path Adaptation
LPT: Low order Path Termination HPT: High order Path Termination
PPI
l
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module: Encodes and decodes signals. Recovers data and clock. Processes the A_LOS alarm.
l l l
E3/T3 mapping/demapping
l l
LPA The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted so as to be transported into the synchronous network. LPT The virtual container (VC-3) is formatted by lower order path termination (LPT). The VC-3 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the VC-3 container and POH. The latter contains nine octets equally distributed within the frame bytes for VC-3: J1, B3, C2, G1, F2, H4, F3, K3, and N1. HPA HPA generates and processes channel level TU-PTR. In the receive direction, the signals are split into VC-3s, which are located and isolated in TU-3. TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The sequence is: TU-3->TUG3->VC-4. HPT The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the C4 container and POH.
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l l l
l l
l l
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MST and RST The functions are necessary to create a proprietary STM1 signal in order to connect the interface conversion module.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
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PL3A
STAT ACT PROG SRV
PL3A
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are three pairs of 75-ohm unbalanced interfaces, which are of the SMB type.
The PL3A can be housed in any of slots 1113 in the OptiX OSN 1500B subrack.
J1 byte C2 byte Tributary loopback Service loading indication Path service type
HDB3 B3ZS
Mechanical Specifications
The mechanical specifications of the PL3A are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1PL3A is 15 W. In the normal temperature (25), the maximum power consumption of the N2PL3A is 12 W.
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6.7 PD3
This section describes the PD3, a 6 x E3/T3 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.7.1 Version Description The PD3 board has two functional versions, N1 and N2. The difference between the two versions lies in the support for the E13/M13 function. 6.7.2 Function and Feature The PD3 can be used to process E3/T3 signals and the overhead, to report alarms and performance events, to provide the maintenance feature and the TPS protection. 6.7.3 Working Principle and Signal Flow The PD3 consists of the PPI, E3/T3 mapping/demapping, interface conversion module, communication and control module and so on. 6.7.4 Front Panel On the front panel of the PD3, there are indicators. 6.7.5 Valid Slots The OptiX OSN 1500A does not support the PD3 board. 6.7.6 TPS Protection for the Board The PD3 supports the 1:N TPS protection. 6.7.7 Board Configuration Reference You can use the T2000 to set parameters for the PD3. 6.7.8 Technical Specifications The technical specifications of the PD3 cover the electrical interface specifications, board dimensions, weight and power consumption.
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E3/T3
LIU P P I LIU
6 x 34 Mbit/s/ 6 x 45 Mbit/s
2 x 155 Mbit/s
E3/T3
6 x 34 Mbit/s/ 6 x 45 Mbit/s
2 x 155 Mbit/s
Cross-connect unit A
Cross-connect unit B
+1.8 V
DC/DC converter
DC/DC converter
Fuse
OSC: Oscillator
Figure 6-29 shows the block diagram of the E3/T3 mapping/demapping. Figure 6-29 Block diagram of the E3/T3 mapping/demapping
E3/T3 mapping/demapping
E3/T3
LPA
LPT
HPA
HPT
STM-1
E3/T3
STM-1
LPA
LPT
HPA
HPT
LPA: Low order Path Adaptation HPA: High order Path Adaptation
LPT: Low order Path Termination HPT: High order Path Termination
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PPI
l
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module: Encodes and decodes signals. Recovers data and clock. Processes the A_LOS alarm.
l l l
E3/T3 mapping/demapping
l l
LPA The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted so as to be transported into the synchronous network. LPT The virtual container (VC-3) is formatted by lower order path termination (LPT). The VC-3 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the VC-3 container and POH. The latter contains nine octets equally distributed within the frame bytes for VC-3: J1, B3, C2, G1, F2, H4, F3, K3, and N1. HPA HPA generates and processes channel level TU-PTR. In the receive direction, the signals are split into VC-3s, which are located and isolated in TU-3. TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The sequence is: TU-3->TUG3->VC-4. HPT The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the C4 container and POH. MST and RST The functions are necessary to create a proprietary STM1 signal in order to connect the interface conversion module.
l l l
l l
l l
l l
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
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PD3
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
No interfaces are present on the front panel of the PD3. The D34S, an electrical interface switching board, provides the E3/T3 interfaces for the PD3. For details, see the section that describes the D34S.
Protection Principle
For the OptiX OSN 1500B, when used with the D34S and TSB8, the PD3 can be configured into one 1:1 TPS protection group. Figure 6-31 shows the principle of the TPS protection for the PD3. Figure 6-31 Principle of the TPS protection for the PD3 in the OptiX OSN 1500B subrack
6 xE3/T3
TSB8
D34S
SLOT 4/5
Protection
Working
PD3
Fail
PD3
SLOT12
SLOT13
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Normal state When the working boards are running normally, the control switch of the D34S is in position 1 and services are directly accessed to the PD3 board.
Switching state When the working board detects a fault and requires a switching, the control switch of the D34S is shifted to position 2 and the control switch of the TSB8 is shifted to a corresponding position. In this way, the protection board protects the faulty working board.
Hardware Configuration
Table 6-30 lists the slot configuration for the TPS protection for the PD3 in the OptiX OSN 1500B subrack. Table 6-30 Slot configuration for the 1:1 TPS protection for the PD3 in the OptiX OSN 1500B subrack Working Board PD3 (E3) PD3 (T3) Protection Board PD3 (E3) PD3 (T3) Slot Figure 6-32 shows the slot configuration for the 1:1TPS protection for the PD3
Figure 6-32 Slot configuration for the 1:1 TPS protection for the PD3 in the OptiX OSN 1500B subrack
Slot 14 Slot 15 Slot 16 Slot 17 Slot 11 Slot 20 FAN Slot 12 Slot 13 Slot 4 Slot 5 Protection Working CXL16/4/1 CXL16/4/1 D34S TSB8 Slot 18 PIU
PIU
EOW AUX
As shown in Figure 6-32, the protection board housed in slot 12 protects the board housed in slot 13. Table 6-31 lists the slots for the PD3, D34S and TSB8. Table 6-31 Slots for the PD3, D34S and TSB8 in the OptiX OSN 1500B subrack Board PD3 (working) PD3 (protection) TSB8
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Board D34S
J1 byte C2 byte Tributary loopback Service loading indication Path service type
Mechanical Specifications
The mechanical specifications of the PD3 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
Power Consumption
In the normal temperature (25), the maximum power consumption of the N1PD3 is 19 W. In the normal temperature (25), the maximum power consumption of the N2PD3 is 12 W.
6.8 PQ3
This section describes the PQ3, a 12 x E3/T3 processing board, in terms of the version, function, principle, front panel, configuration and specifications. 6.8.1 Version Description The functional version of the PQ3 board is N2. 6.8.2 Function and Feature
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The PQ3 can be used to process E3/T3 signals and the overhead, to report alarms and performance events, to provide the maintenance feature and the TPS protection. 6.8.3 Working Principle and Signal Flow The PQ3 consists the PPI, E3/T3 mapping/demapping, interface conversion module, communication and control module and so on. 6.8.4 Front Panel On the front panel of the PQ3, there are indicators. 6.8.5 Valid Slots The OptiX OSN 1500A does not support the PQ3 board. 6.8.6 TPS Protection for the Board The PQ3 supports the 1:N TPS protection. 6.8.7 Board Configuration Reference You can use the T2000 to set parameters for the PQ3. 6.8.8 Technical Specifications The technical specifications of the PQ3 cover the electrical interface specifications, board dimensions, weight and power consumption.
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PQ3 Supports inloop and outloop for electrical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. Supports the PRBS function.
Protection scheme
Supports the TPS protection when used with the interface board and the switching board.
E3/T3
LIU P P I LIU
6 x 34 Mbit/s/ 6 x 45 Mbit/s
2 x 155 Mbit/s
E3/T3
6 x 34 Mbit/s/ 6 x 45 Mbit/s
2 x 155 Mbit/s
Cross-connect unit A
Cross-connect unit B
+1.8 V
DC/DC converter
DC/DC converter
Fuse
OSC: Oscillator
E3/T3
LPA
LPT
HPA
HPT
STM-1
E3/T3
STM-1
LPA
LPT
HPA
HPT
LPA: Low order Path Adaptation HPA: High order Path Adaptation
LPT: Low order Path Termination HPT: High order Path Termination
PPI
l
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module: Encodes and decodes signals. Recovers data and clock. Processes the A_LOS alarm.
l l l
E3/T3 mapping/demapping
l l
LPA The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted so as to be transported into the synchronous network. LPT The virtual container (VC-3) is formatted by lower order path termination (LPT). The VC-3 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the VC-3 container and POH. The latter contains nine octets equally distributed within the frame bytes for VC-3: J1, B3, C2, G1, F2, H4, F3, K3, and N1. HPA HPA generates and processes channel level TU-PTR. In the receive direction, the signals are split into VC-3s, which are located and isolated in TU-3. TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The sequence is: TU-3->TUG3->VC-4. HPT The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the C4 container and POH.
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l l l
l l
l l
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MST and RST The functions are necessary to create a proprietary STM1 signal in order to connect the interface conversion module.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board.
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PQ3
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PQ3. The D34S, an electrical interface switching board, provides the E3/T3 interfaces for the PQ3. For details, see the section that describes the D34S.
Table 6-33 Valid slots for the PQ3 and corresponding slots for the D34S in the OptiX OSN 1500B subrack Valid Slot for the PQ1 Slot 12 Slot 13 Corresponding Slot for the D34S Slots 14 and 15 Slots 16 and 17
Protection Principle
In the OptiX OSN 1500B, used with the D34S and TSB8, the PQ3 can be configured into one 1:1 TPS protection group. Figure 6-36 shows the principle of the TPS protection for the PQ3. Figure 6-36 Principle of the TPS protection for the PQ3 in the OptiX OSN 1500B subrack
6 xE3/T3 6 xE3/T3
TSB8
TSB8
D34S
D34S
Protection
Working PQ3
Fail
SLOT 4/5
PQ3
SLOT12
SLOT13
Normal state When the working boards are running normally, the control switch of the D34S is in position 1 and services are directly accessed to the PQ3 board.
Switching state When the working board detects a fault and requires a switching, the control switch of the D34S is shifted to position 2 and the control switch of the TSB8 is shifted to a corresponding position. In this way, the protection board protects the faulty working board.
Hardware Configuration
NOTE
Two TSB8 boards are required to configure the TPS protection for the N2PQ3.
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Table 6-34 lists the slot configuration for the TPS protection for the PQ3 in the OptiX OSN 1500B subrack. Table 6-34 Slot configuration for the 1:1 TPS protection for the PQ3 in the OptiX OSN 1500B subrack Working Board PQ3 (E3) PQ3 (T3) Protection Board PQ3 (E3) PQ3 (T3) Slot Figure 6-37 shows the slot configuration for the 1:3 TPS protection for the PQ3.
Figure 6-37 Slot configuration for the 1:1 TPS protection for the PQ3 in the OptiX OSN 1500B subrack
Slot 14 Slot 15 Slot 16 Slot 17 Slot 11 Slot 20 FAN Slot 12 Slot 13 Slot 4 Slot 5 Protection Working CXL16/4/1 CXL16/4/1 TSB8 TSB8 D34S D34S Slot 18 PIU
PIU
EOW AUX
As shown in Figure 6-37, the protection board housed in slot 12 protects the board housed in slot 13. Table 6-35 lists the slots for the PQ3, D34S and TSB8. Table 6-35 Slots for the PQ3, D34S and TSB8 in the OptiX OSN 1500B subrack Board PQ3 (working) PQ3 (protection) TSB8 D34S Protection Group Slot 13 Slot 12 Slots 1415 Slots 1617
J1 byte
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Mechanical Specifications
The mechanical specifications of the PL1 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
Power Consumption
In the normal temperature (25), the maximum power consumption of the PQ3 is 13 W.
6.9 DX1
This section describes the DX1, a DDN interface convergence board, in terms of the version, function, principle, front panel, configuration and specifications. 6.9.1 Version Description The functional version of the DX1 board is N1. 6.9.2 Function and Feature The DX1, a DDN interface convergence board, cross-connects 48 x E1 signals at the 64k level at the system side. 6.9.3 Working Principle and Signal Flow The DX1 consists of the interface and frame processing module, encoding/decoding module, timeslot cross-connect module, framing/deframing module and so on. 6.9.4 Front Panel On the front panel of the DX1, there are indicators. 6.9.5 Valid Slots The OptiX OSN 1500A does not support the DX1 board. 6.9.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the DX1 indicates the interface impedance type.
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6.9.7 TPS Protection for the Board The DX1 supports the 1:N TPS protection. 6.9.8 Board Configuration Reference You can use the T2000 to set parameters for the DX1. 6.9.9 Technical Specifications The technical specifications of the DX1 cover the electrical interface specifications, board dimensions, weight and power consumption.
Processes eight channels of N x 64 kbit/s services and 8 x framed E1 services. Cross-connects 48 channels of N x 64 kbit/s signals at the system side. Accesses eight channels of N x 64 kbit/s and 8 x framed E1 services and realizes the 1:N TPS protection when used with the DM12. One DX1 board should be used with two DM12 boards. Provides rich alarms and performance events for easy management and maintenance of the equipment. The connectors of the DB28 and DB44 are present on the front panel of the DM12. The DB28 is for the N x 64 kbit/s signals, and the DB44 is for the framed E1 signals. Supports inloop and outloop. Supported.
8X Frame E1
8X Nx64 kbit/s
Crossconnect unit
8X Nx64 kbit/s
SCC unit
DC/DC converter
DC/DC converter
Fuse
Fuse
DX1
STAT ACT PROG SRV
DX1
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
There are no interfaces on the front panel of the DX1. When used with the DM12, the DX1 can input and output the framed E1 and N x 64 kbit/s signals. For details, see the section that describes the DM12.
NOTE
l l
Slot 11 can house a protection board of the TPS protection. The board housed in slot 11 protects the boards housed in slots 12 and 13. One DX1 should be used with two DM12 to access eight channels of N x 64 kbit/s signals. The DM12 board housed in the slot with a smaller slot number is used to access 8 x framed E1 and four channels of N x 64 kbit/s signals. The DM12 board housed in the slot with a larger slot number is used to access four channels of N x 64 kbit/s signals.
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Protection Principle
In the OptiX OSN 1500B, used with the DM12, the DX1 can be configured into one 1:N (N 2) TPS protection group. Figure 6-40 shows the principle of the TPS protection for the DX1. Figure 6-40 Principle of the TPS protection for the DX1 in the OptiX OSN 1500B subrack
S S L L protection bus O O T T 14 15
S L O T 16
S L O T 17
DM12 DM12
DM12 DM12
S L O T 12
service bus
S L O T 11 S L O T 13
Fail
When detecting a fault in the working DX1 board, the cross-connect board issues a command to switch the services from the faulty DX1 to the protection DX1. In this way, services are protected.
Hardware Configuration
Figure 6-41 shows the slot configuration for the 1:2 TPS protection for the DX1 in the OptiX OSN 1500B subrack.
Protection
Working
Working
TPS switching control bus
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Figure 6-41 Slot configuration for the 1:2 TPS protection for the DX1 in the OptiX OSN 1500B subrack
Slot 14 Slot 15 Slot 16 Slot 17 Slot 11 Slot 20 FAN Slot 12 Slot 13 Slot Slot 4 5 DM12 DM12 DM12 DM12 Slot 18 Slot 19 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 EOW AUX PIU PIU
As shown in Figure 6-41, the protection board housed in slot 11 protects the boards housed in slots 1213. Table 6-39 lists the slots for the DX1 and DM12 in the OptiX OSN 1500B subrack. Table 6-39 Slots for the DX1 and DM12 in the OptiX OSN 1500B subrack Board DX1 (working) DX1 (protection) DM12 Protection Group Slots 12 and 13 Slot 11 Slots 1417
J2 byte Tributary loopback Service loading indication Protocol mode of serial ports DDN clock source management
Mechanical Specifications
The mechanical specifications of the DX1 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the DX1 is 15 W.
NOTE
After the TPS protection is performed, the power consumption of the DX1 is 31 W.
6.10 DXA
This section describes the DXA, a DDN convergence board, in terms of the version, function, principle, front panel, configuration and specifications. 6.10.1 Version Description The functional version of the DXA board is N1. 6.10.2 Function and Feature The DXA, a DDN interface convergence board, cross-connects 63 x E1 signals at the 64k level at the system side. 6.10.3 Working Principle and Signal Flow The DXA consists of the timeslot cross-connect module, framing/deframing module, mapping/ demapping module, control and communication module and power supply module. 6.10.4 Front Panel On the front panel of the DXA, there are indicators. 6.10.5 Valid Slots The DXA can be housed in different slots in the OptiX OSN 1500A and OptiX OSN 1500B subracks. 6.10.6 Board Configuration Reference You can use the T2000 to set parameters for the DXA. 6.10.7 Technical Specifications The technical specifications of the DXA cover the optical interface specifications, board dimensions, weight and power consumption.
Crossconnect unit
Crossconnect unit
DC/DC converter
Fuse
signals and transmits the signals to the timeslot cross-connect module. The timeslot crossconnect module cross-connects and grooms the signals in the 64 kbit/s granularities.
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DXA
STAT ACT PROG SRV
DXA
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the DXA.
The DXA can be housed in any of slots 1113 in the OptiX OSN 1500B subrack.
J2 byte Tributary loopback Service loading indication Protocol mode of serial ports DDN clock source management
Mechanical Specifications
The mechanical specifications of the DXA are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.8
Power Consumption
In the normal temperature (25), the maximum power consumption of the DXA is 10 W.
6.11 SPQ4
This section describes the SPQ4, a 4 x E1/STM-1 processing board, in terms of the version, function, working principle, front panel and specifications. 6.11.1 Version Description The SPQ4 has two versions, N1 and N2. The two versions have different functions. 6.11.2 Function and Feature The SPQ4 is used to process 4 x E4/STM-1 electrical signals and the overhead, to report alarms and performance events, and to provide the maintenance features and protection. 6.11.3 Working Principle and Signal Flow The SPQ4 consists of the interface module, encoding/decoding module, frame synchronization and scramble processing module, mapping/demapping module, SDH overhead processing module, logic control module, and power supply module. 6.11.4 Front Panel On the front panel of the SPQ4, there are indicators. 6.11.5 Valid Slots
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The OptiX OSN 1500A does not support the SPQ4 board. 6.11.6 TPS Protection for the Board The SPQ4 supports the 1:N TPS protection. 6.11.7 Board Configuration Reference You can use the T2000 to set parameters for the SPQ4. 6.11.8 Technical Specifications The technical specifications of the SPQ4 cover the electrical interface specifications, board dimensions, weight and power consumption.
Replaceability
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SPQ4 Supports the processing of SOH bytes for the STM-1 signals, such as B1, B2, K1, K2, M1, F1, and D1D12. Supports the transparent transmission and termination of POH bytes, including J1, B3, C2, G1, and H4. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports the TPS protection when used with the interface board and the switching board. Supports the two-fiber unidirectional MSP protection ring, linear MSP protection, and SNCP.
Maintenance feature
Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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140M mapping/demapping
4x155 Mbit/s
LIU
LIU
P P I/ S P I
Cross-connect unit A
4x155 Mbit/s
DCC K1 and K2
5V +1.8V +2.5V
DC/DC converter
DC/DC converter
Fuse
Fuse
LPA
HPT
PG
MST
RST
E4 AIS insertion
J1/C2/B3
E4 AIS insertion
139Mbit/s
155Mbit/s
SIPO
LPA
HPT
MST
RST
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K1 and K2 insertion/extration
Crossconnect unit
RST
155 Mbit/s
MST
MSA
HPT
155 Mbit/s
DCC
SCC unit
The principle of the E4/ STM-1 electrical interface units is described below.
PPI/SPI
l
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module: Encodes and decodes signals. Recovers data and clock. Processes the PDH LOS signals. The SPI module mainly consists of line interface units (LIUs). It provides inloop and outloop function. This module: Encodes and decodes signals. Recovers data and clock. Processes the R_LOS signals.
l l l l
l l l
SDH Overhead Processing Module and 140M Mapping/Demapping Module SDH Overhead Processing Module (155Mbit/s SDH Signals)
The functions required to manage 155 Mbit/s SDH signals are implemented by the SDH overhead processing module.
RST
l
In the receive direction, RST performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In the transmit direction, RST performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion.
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MST
l
In the receive direction, MST performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte.
MSA
l
In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In the transmit direction, MSA performs AUG assembly, AU-4 pointer generation, AU_AIS generation.
HPT
l l l l l l
OH termination J1 path trace message recover REI information recovering HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
LPA
The 140 Mbit/s plesiochronous stream is inserted in a C4 container to be adapted so as to be transported into the synchronous network. PDH AIS is monitored and E4 AIS in inserted.
HPT
The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed within a 125 us interval (for example, one STM1 period), and consists of the C4 container and POH. The latter contains nine octets equally distributing within the frame. These overhead bytes can be extracted: J1, B3. C2, G1, F2, H4, F3, K3 and N1.E4 AIS can be inserted in downstream direction. PG (Pointer generator) A fixed pointer value is inserted in the SOH to structure the AU4 signal.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface. Traces the clock signal from the active and the standby cross-connect units. Realizes the pass-through of orderwire and ECC bytes between the two service processing boards constituting the ADM when the GSCC is not online. Selects the clock and frame header from the active or the standby cross-connect units. Control the indicator on the board.
l l
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SPQ4
STAT ACT PROG SRV
SPQ4
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the SPQ4. When used with the MU04, the SPQ4 can input or output the E4/STM-1 signals. For details, see the section that describes the MU04.
Table 6-43 lists the valid slots for the SPQ4 and corresponding slots for the MU04. Table 6-43 Valid slots for the SPQ4 and corresponding slots for the MU04 in the OptiX OSN 1500B subrack Valid Slot for the SPQ4 Slot 12 Slot 13 Corresponding Slot for the DMU04 Slot 14 Slot 16
Protection Principle
In the OptiX OSN 1500B, used with the MU04 and TSB8, the SPQ4 can be configured into one 1:1 TPS protection group. Figure 6-48 shows the principle of the TPS protection for the SPQ4. Figure 6-48 Principle of the TPS protection for the SPQ4 in the OptiX OSN 1500B subrack
4 E4/STM-1
Switch control signal
TSB8
MU04
1 2
SLOT 4/5
Protection
SPQ4
Working SPQ4
Fail
SLOT12
SLOT13
Normal state When the working boards are running normally, the control switch of the MU04 is in position 1 and the MU04 directly accesses the service signals to the SLH1.
Switching state When the working board detects a fault and requires a switching, the control switch of the MU04 is shifted to position 2 and the control switch of the TSB8 is shifted to a corresponding position. In this way, the protection board protects the faulty working board.
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Hardware Configuration
Figure 6-49 shows the slot configuration for the 1:2 TPS protection for the SPQ4 in the OptiX OSN 1500B subrack. Figure 6-49 Slot configuration for the 1:1 TPS protection for the SPQ4
Slot 14 Slot 15 Slot 16 Slot 17 Slot 11 Slot 20 FAN Slot 12 Slot 13 Slot 4 Slot 5 Protection Working CXL16/4/1 CXL16/4/1 MU04 TSB8 Slot 18 PIU
PIU
EOW AUX
As shown in Figure 6-49, the protection board housed in slot 12 protects the board housed in slot 13. Table 6-44 lists the slots for the SPQ4, MU04 and TSB8. Table 6-44 Slots for the SPQ4, MU04 and TSB8 in the OptiX OSN 1500B subrack Board SPQ4 (working) SPQ4 (protection) MU04 TSB8 Protection Group Slot 13 Slot 12 Slot 16 Slot 14
J1 byte C2 byte
Mechanical Specifications
The mechanical specifications of the SPQ4 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.9
Power Consumption
In the normal temperature (25), the maximum power consumption of the SPQ4 is 24 W.
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7
About This Chapter
This chapter describes the data processing boards for the FE, GE, ATM, and SAN signals. 7.1 EFT4 This section describes the EFT4, a 4 x FE Ethernet transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications. 7.2 EFT8 This section describes the EFT8, an 8/16 x FE Ethernet transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications. 7.3 EFT8A This section describes the EFT8A, an 8 x FE Ethernet transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications. 7.4 EGT2 This section describes the EGT2, a 2 x GE Ethernet transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications. 7.5 EFS0 This section describes the EFS0, an 8 x FE Ethernet processing board with Lanswitch, in terms of the version, function, principle, front panel, configuration and specifications. 7.6 EFS4 This section describes the EFS4, a 4 x FE Ethernet processing board with Lanswitch, in terms of the version, function, principle, front panel, configuration and specifications. 7.7 EGS2 This section describes the EGS2, a 2 x GE Ethernet processing board with Lanswitch, in terms of the version, function, principle, front panel, configuration and specifications. 7.8 EMS4 This section describes the EMS4, a 4 x GE and 16 x FE Ethernet transparent transmission and convergence board, in terms of the version, function, principle, front panel, configuration and specifications. 7.9 EGS4
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This section describes the EGS4, a 4 x GE Ethernet convergence board, in terms of the version, function, principle, front panel, configuration and specifications. 7.10 EGS4A This section describes the EGS4A, a 4 x GE Ethernet convergence board, in terms of the version, function, principle, front panel, configuration and specifications. 7.11 EGR2 This section describes the EGR2, a 2 x GE Ethernet processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.12 EMR0 This section describes the EMR0, a 12 x FE and 1 x GE Ethernet ring processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.13 ADL4 This section describes the ADL4, a 1 x STM-4 ATM processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.14 ADQ1 This section describes the ADQ1, a 4 x STM-1 ATM processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.15 IDL4 This section describes the IDL4, a 1 x STM-4 ATM processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.16 IDQ1 This section describes the IDQ1, a 4 x STM-1 ATM processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.17 MST4 This section describes the MST4, a 4-channel multi-service transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications.
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7.1 EFT4
This section describes the EFT4, a 4 x FE Ethernet transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications. 7.1.1 Version Description The functional version of the EFT4 board is R1. 7.1.2 Function and Feature The EFT4 supports transparent transmission of Ethernet services, LCAS, and test frames. 7.1.3 Working Principle and Signal Flow The EFT4 consists of the ethernet access module, mapping module, interface converting module, Communication and control module and so on. 7.1.4 Front Panel On the front panel of the EFT4, there are indicators, interfaces and barcode. 7.1.5 Valid Slots The EFT4 can be housed in any of slots 2, 3, 69 and 1213 in the OptiX OSN 1500A subrack. The EFT4 can be housed in any of slots 13, 69 and 1113 in the OptiX OSN 1500B subrack. 7.1.6 Board Configuration Reference You can use the T2000 to set parameters for the EFT4. 7.1.7 Technical Specifications The specifications of the EFT4 cover the mechanical specifications and power consumption.
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Function and Feature Max. uplink bandwidth Number of VCTRUNKs Encapsulation format Mapping granularity Ethernet service type MTU
EFT4 622 Mbit/s. 4. HDLC, LAPS, GFP-F. Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X3). Supports EPL. Supports setting of the packet length, which ranges from 1518 bytes to 1535 bytes. After the setting becomes valid, the length of the packets that enter or exit the IP ports is limited. Not supported. Supports VLAN transparent transmission. Supports the LPT in the GFP-carrying mode. Not supported. Supports the IEEE 802.3x flow control based on FE port. Dynamically increases or decreases the bandwidth, and realizes the protection function, compliant with ITU-T G.7042. Not supported. Receives and transmits Ethernet test frames. Supports Ethernet performance monitoring at the port level.
MPLS VLAN LPT CAR Flow control function LCAS ETH-OAM Test frame Ethernet performance monitoring Alarm and performance event
Provides rich alarms and performance events for easy management and maintenance of the equipment.
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ENCP
FE
Cross-connect unit
Laser shutdown
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V
Clock module
DC/DC converter
Fuse
Fuse
- 48 V/-60V - 48 V/-60V
DC/DC converter
+3.3 V
The function modules of ethernet switching boards are described below: ENCP: data encapsulation module VCP: virtual concatenation processing module DENCP: decapsulation module
Mapping module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format. The concatenation is processed. Ethernet signals are then converted into SDH signals. In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
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Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
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EFT4
STAT ACT PROG SRV
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four FE interfaces on the front panel of the EFT4. Table 7-2 lists the type and usage of the interfaces. Table 7-2 Optical interfaces of the EFT4 Interface FE1 FE2 FE3 FE4 Interface Type RJ-45 RJ-45 RJ-45 RJ-45 Usage Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals.
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Table 7-3 lists the pins of the RJ-45 interface. Table 7-3 Pins of the RJ-45 of the EFT4 Pin 1 2 3 4 5 6 7 8 Description Transmitting positive Transmitting negative Receiving positive Grounding Grounding Receiving negative Grounding Grounding
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Mechanical Specifications
The mechanical specifications of the EFT4 are as follows:
l l
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.5
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Power Consumption
In the normal temperature (25), the maximum power consumption of the EFT4 is 14 W.
7.2 EFT8
This section describes the EFT8, an 8/16 x FE Ethernet transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications. 7.2.1 Version Description The functional version of the EFT8 board is N1. 7.2.2 Function and Feature The EFT8 supports transparent transmission of Ethernet services, LCAS, and test frames. 7.2.3 Working Principle and Signal Flow The EFT8 consists of the ethernet access module, mapping module, interface converting module, communication and control module and so on. 7.2.4 Front Panel On the front panel of the EFT8, there are indicators, interfaces and barcode. 7.2.5 Valid Slots The EFT8 can be used with the ETF8 and EFF8. 7.2.6 Board Configuration Reference You can use the T2000 to set parameters for the EFT8. 7.2.7 Technical Specifications The specifications of the EFT8 cover the mechanical specifications and power consumption.
Function and Feature Specification of the optical interface Format of service frames Max. uplink bandwidth Number of VCTRUNKs Encapsulation format Mapping granularity Ethernet service type MPLS VLAN LPT CAR ETH-OAM Flow control function LCAS ETH-OAM Test frame Ethernet performance monitoring Alarms and performance events
EFT8 Supports the 10Base-T/100Base-TX signals when used with the ETF8. Supports the 100Base-FX/100Base-TX signals when used with the EFF8. The optical interfaces comply with IEEE 802.3u. Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG. Supports frames with a length ranging from 64 bytes to 9600 bytes. Supports Jumbo frames with a length less than 9600 bytes. 1.25 Gbit/s. 16. Supports HDLC, LAPS, and GFP-F. Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X3). Supports EPL. Not supported. Supports the VLAN transparent transmission. Supports the LPT in the GFP-carrying mode. Not supported. Supports ETH-OAM in compliance with 802.1ag. The EFT8 supports CC for the multicast. Supports the IEEE 802.3x flow control based on FE port. Dynamically increases or decreases the bandwidth, and realizes the protection function, compliant with ITU-T G.7042. Not supported. Receives and transmits GFP test frames. Supports Ethernet performance monitoring at the port level.
Provides rich alarms and performance events for easy management and maintenance of the equipment.
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ENCP
FE
Cross-connect unit
Laser shutdown
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V
Clock module
DC/DC converter
Fuse
Fuse
- 48 V/-60V - 48 V/-60V
DC/DC converter
+3.3 V
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format. The concatenation is processed. Ethernet signals are then converted into SDH signals.
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In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EFT8
STAT ACT PROG SRV
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
EFT8
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight interfaces on the front panel of the EFT8. Table 7-5 lists the type and usage of the interfaces.
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Table 7-5 Optical interfaces of the EFT8 Interface FE1 FE2 FE3 FE4 FE5 FE6 FE7 FE8 Interface Type RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 Usage Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals.
Table 7-6 lists the pins of the RJ-45 interface. Table 7-6 Pins of the RJ-45 of the EFT8 Pin 1 2 3 4 5 6 7 8 Description Transmitting positive Transmitting negative Receiving positive Grounding Grounding Receiving negative Grounding Grounding
Table 7-7 and Table 7-8 list the valid slots for the EFT8 and corresponding slots for the ETF8 and EFF8. Table 7-7 Valid slots for the EFT8 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500A Valid Slot for the EFT8 Slot 12 Slot 13 Corresponding Slot for the ETF8 and EFF8 Without the interface board Without the interface board
Table 7-8 Valid slots for the EFT8 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500B Valid Slot for the EFT8 Slot 11 Slot 12 Slot 13 Corresponding Slot for the ETF8 and EFF8 Without the interface board Slot 14 Slot 16
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Mechanical Specifications
The mechanical specifications of the EFT8 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the EFT8 is 26 W.
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7.3 EFT8A
This section describes the EFT8A, an 8 x FE Ethernet transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications. 7.3.1 Version Description The functional version of the EFT8A board is N1. 7.3.2 Function and Feature The EFT8A supports transparent transmission of Ethernet services, LCAS, and test frames. 7.3.3 Working Principle and Signal Flow The EFT8A consists of the ethernet access module, mapping module, interface converting module, communication and control module and so on. 7.3.4 Front Panel On the front panel of the EFT8A, there are indicators, interfaces and barcode. 7.3.5 Valid Slots The EFT8A can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The EFT8A can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.3.6 Board Configuration Reference You can use the T2000 to set parameters for the EFT8A. 7.3.7 Technical Specifications The specifications of the EFT8A cover the mechanical specifications and power consumption.
EFT8A Transparently transmits 8 x FE services. Supports 10Base-T/100Base-TX signals. The optical interfaces comply with IEEE 802.3u. Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG. Supports frames with a length ranging from 64 bytes to 9600 bytes. Supports Jumbo frames with a length less than 9600 bytes. 622 Mbit/s.
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Function and Feature Number of VCTRUNKs Encapsulation format Mapping granularity Ethernet service type MPLS VLAN LPT CAR ETH-OAM Flow control function LCAS ETH-OAM Test frame Ethernet performance monitoring Alarm and performance event
EFT8A 8. Supports HDLC, LAPS, and GFP-F. Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X3). Supports EPL. Not supported. Supports VLAN transparent transmission. Supports the LPT in the GFP-carrying mode. Not supported. Supports the ETH-OAM in compliance with 802.1ag. The EFT8 supports CC for the multicast. Supports the IEEE 802.3x flow control based on FE port. Dynamically increases or decreases the bandwidth, and realizes the protection function, compliant with ITU-T G.7042. Not supported. Receives and transmits GFP test frames. Supports Ethernet performance monitoring at the port level.
Provides rich alarms and performance events for easy management and maintenance of the equipment.
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ENCP
FE
Cross-connect unit
Laser shutdown
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V
Clock module
DC/DC converter
Fuse
Fuse
- 48 V/-60V - 48 V/-60V
DC/DC converter
+3.3 V
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format. The concatenation is processed. Ethernet signals are then converted into SDH signals. In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
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Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
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EFT8A
STAT ACT PROG SRV
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
EFT8A
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight FE interfaces on the front panel of the EFT8A. Table 7-10 lists the type and usage of the interfaces.
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Table 7-10 Optical interfaces of the EFT8A Interface FE1 FE2 FE3 FE4 FE5 FE6 FE7 FE8 Interface Type RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 Usage Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals.
Table 7-11 lists the pins of the RJ-45 interface. Table 7-11 Pins of the RJ-45 of the EFT8A Pin 1 2 3 4 5 6 7 8 Description Transmitting positive Transmitting negative Receiving positive Grounding Grounding Receiving negative Grounding Grounding
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Mechanical Specifications
The mechanical specifications of the EFT8A are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the EFT8A is 26 W.
7.4 EGT2
This section describes the EGT2, a 2 x GE Ethernet transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications. 7.4.1 Version Description The functional version of the EGT2 board is N1. 7.4.2 Function and Feature The EGT2 supports transparent transmission of Ethernet services, LCAS, and test frames. 7.4.3 Working Principle and Signal Flow The EGT2 consists of the ethernet access module, mapping module, interface converting module, interface converting module, Communication and Control Module and so on. 7.4.4 Front Panel On the front panel of the EGT2, there are indicators, interfaces and barcode. 7.4.5 Valid Slots The EGT2 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The EGT2 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.4.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the EGT2 indicates the optical interface type.
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7.4.7 Board Configuration Reference You can use the T2000 to set parameters for the EGT2. 7.4.8 Technical Specifications The specifications of the EGT2 cover the optical interface specifications, mechanical specifications and power consumption.
Format of service frames Max. uplink bandwidth Number of VCTRUNKs Encapsulation format Mapping granularity Ethernet service type MPLS VLAN LPT
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Function and Feature CAR Flow control function LCAS ETH-OAM Test frame Ethernet performance monitoring Alarm and performance event
EGT2 Not supported. Supports the IEEE 802.3x flow control based on GE port. Dynamically increases or decreases the bandwidth and realizes the protection function, compliant with ITU-T G.7042. Not supported. Receives and transmits Ethernet test frames. Supports Ethernet performance monitoring at the port level.
Provides rich alarms and performance events for easy management and maintenance of the equipment.
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ENCP
GE
Cross-connect unit
Laser shutdown
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V
Clock module
DC/DC converter
Fuse
Fuse
- 48 V/-60V - 48 V/-60V
DC/DC converter
+3.3 V
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format. The concatenation is processed. Ethernet signals are then converted into SDH signals. In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
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Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
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EGT2
STAT ACT PROG SRV LINK1 ACT1 LINK2 ACT2
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two GE interfaces on the front panel of the EGT2. Table 7-13 lists the type and usage of the interfaces.
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Table 7-13 Optical interfaces of the EGT2 Interface IN1/OUT1 IN2/OUT2 Interface Type LC (pluggable) LC (pluggable) Usage Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals.
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
1480 to 1580
1270 to 1355
1270 to 1355
770 to 860
22
23
19
17
Mechanical Specifications
The mechanical specifications of the EGT2 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.9
Power Consumption
In the normal temperature (25), the maximum power consumption of the EGT2 is 29 W.
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7.5 EFS0
This section describes the EFS0, an 8 x FE Ethernet processing board with Lanswitch, in terms of the version, function, principle, front panel, configuration and specifications. 7.5.1 Version Description The EFS0 has three functional versions, N1, N2 and N4. The production of the N1 version is stopped. 7.5.2 Function and Feature The EFS0 supports Layer 2 switching, MPLS and broadcast. 7.5.3 Working Principle and Signal Flow The EFS0 consists of the ethernet access module, network processor module, mapping module, interface converting module and so on. 7.5.4 Front Panel On the front panel of the EFS0, there are indicators, interfaces and barcode. 7.5.5 Valid Slots The EFS0 can be housed in any of slots 1213 in the OptiX OSN 1500B subrack. 7.5.6 TPS Protection The EFS0 supports the 1:N TPS protection. 7.5.7 Board Configuration Reference You can use the T2000 to set parameters for the EFS0. 7.5.8 Technical Specifications The specifications of the EFS0 cover the mechanical specifications and power consumption.
Item Replaceability
Description The N2EFS0 supports the board version replacement function and can replace the N1EFS0. The N4EFS0 supports the board version replacement function and can replace the N1EFS0 and N2EFS0.
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EFS0 Supports EVPL services based on port+VLAN that use the frame encapsulation formats of MartinioE and stack VLAN. Supports the Layer 2 convergence and point to multipoint convergence. Supports the Layer 2 forwarding function. Supports switching at the client and SDH sides. Supports the function of self-learning the source MAC address. The length of the MAC address table is 16k. The aging time of the MAC address can be set and queried. Supports the configuration of static MAC route. The N1EFS0 and N2EFS0 support the dynamic query of the MAC address. The N4EFS0 does not support the dynamic query of the MAC address. Supports the creation, deletion and query of the VB. The maximum number of the VBs is 16. The maximum number of logical ports for each VB is 30.
EVPLAN
Supports data isolation based on VB+VLAN. Supports the query of the number of the learned MAC addresses according to VB+VLAN or VB+LP.
MTU
The packet length can be set from 1518 bytes to 9600 bytes. After the packet length setting takes effect, the maximum length of the packets entering or going out from the IP port are limited by the MTU setting. Supported. Compliant with IEEE 802.1q/p. Supported (4k VLAN). Supports broadcast packet suppression and RSTP, compliant with IEEE 802.1w. Supported. The N4EFS0 supports CC for the multicast, LB test for the unicast, Link Trance test(LT), loop detection (LD), auto-negotiation, fault diagnosis, and link performance detection. Supported. The granularity is 64 kbit/s.
CAR
The N1EFS0 supports the port service, port+VLAN ID service, and port+VLAN PRI service. The N2EFS0 and N4EFS0 support the port flow, port+VLAN ID flow, and port+VLAN PRI flow.
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Function and Feature LCAS LPT Link Aggreation Flow control function Test frame Loopback function Ethernet performance monitoring Alarm and performance event
EFS0 Dynamically increases or decreases the bandwidth and realizes the protection function, compliant with ITU-T G.7042. Supports the LPT function, which can be enabled or disabled. Supported. Supports the IEEE 802.3x flow control based on port. Receives and transmits Ethernet test frames. Supports inloop at the Ethernet port (PHY layer or MAC layer). Supports inloop and outloop at the VC-3 level. Supports Ethernet performance monitoring at the port level.
Provides rich alarms and performance events for easy management and maintenance of the equipment.
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Control FE
Network processor
D E N C P
V C P
Mapping module
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V +1.5 V
Clock module
+1.8 V +2.5 V
DC/DC converter
DC/DC converter
Fuse
Fuse
7-34
In the receive direction, services are mapped and forwarded by adding Tunnel and VC double labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per the level (P or PE) of the equipment. Services are then routed or forwarded. The network processor module:
l l l l l
Supports flow sense and flow classification Supports uni-cast, multi-cast and broadcast of the flow Provides data priority setting Provides weighted fair queuing (WFQ) Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP-F format. The concatenation is processed. The LCAS function is supported. Ethernet signals are then converted into SDH signals. In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
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Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EFS0
STAT ACT PROG SRV
EFS0
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Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the EFS0. The interfaces are present on the ETF8, EFF8 or ETS8.
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Figure 7-11 Slot configuration for the 1:1 TPS protection for the EFS0 in the OptiX OSN 1500B subrack
Slot 14 Slot 15 Slot 16 Slot 17 Slot 11 Slot 20 FAN Slot 12 Slot 13 Slot 4 Slot 5 EFS0 Protection EFS0 Working CXL16/4/1 CXL16/4/1 ETS8 TSB8 Slot 18 PIU
PIU
EOW AUX
As shown in Figure 7-11, the protection board housed in slot 12 protects the board housed in slot 13. The ETS8, housed in slot 16, is used with the working ETS0. The TSB8, housed in slot 14, is used with the protection EFS0.
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Mechanical Specifications
The mechanical specifications of the EFS0 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the EFS0 is 35 W.
7.6 EFS4
This section describes the EFS4, a 4 x FE Ethernet processing board with Lanswitch, in terms of the version, function, principle, front panel, configuration and specifications.
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7.6.1 Version Description The EFS4 has two functional versions, N1 and N2. The two versions have different maximum uplink bandwidth. 7.6.2 Function and Feature The EFS4 supports Layer 2 switching, MPLS and broadcast. 7.6.3 Working Principle and Signal Flow The EFS4 consists of the interface module, service processing module, encapsulation and mapping module, interface converting module, control and communication Module and the power supply module 7.6.4 Front Panel On the front panel of the EFS4, there are indicators, interfaces and barcode. 7.6.5 Valid Slots The EFS4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The EFS4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.6.6 Board Configuration Reference You can use the T2000 to set parameters for the EFS4. 7.6.7 Technical Specifications The specifications of the EFS4 cover the mechanical specifications and power consumption.
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Table 7-20 Functions and features of the EFS4 Function and Feature Basic function Specification of the optical interfaces Format of service frames Max. uplink bandwidth Number of VCTRUNKs Mapping granularity Encapsulation format EPL EVPL EPLAN EFS4 Processes 4 x FE services. Supports 10Base-T/100Base-TX signals. The optical interfaces comply with IEEE 802.3u. Supports Ethernet II, IEEE 802.3, and IEEE 802.1 q/p. Supports frames with a length ranging from 64 bytes to 9600 bytes. Supports Jumbo frames with a length less than 9600 bytes. The maximum uplink bandwidth of the N1EFS4 is 622 Mbit/s. The maximum uplink bandwidth of the N2EFS4 is 1.25 Gbit/s. The number of the VCTRUNKs of the N1EFS4 is 12. The number of the VCTRUNKs of the N2EFS4 is 24. Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X12). GFP-F. Supports transparent transmission based on port. Supports EVPL services based on port+VLAN that use the frame encapsulation formats of MartinioE and stack VLAN. Supports the Layer 2 convergence and point to multipoint convergence. Supports the Layer 2 forwarding function and switching at the client and SDH sides. Supports the function of self-learning the source MAC address. The length of the MAC address table is 16k. The aging time of the MAC address can be set and queried. Supports the configuration of static MAC route. The N1EFS4 supports the dynamic query of the MAC address. The N2EFS4 does not support the dynamic query of the MAC address. Supports the creation, deletion and query of the VB. The maximum number of the VBs is 16 (a maximum of two VBs for the N2EGS2). The maximum number of logical ports for each VB is 30. EVPLAN Supports data isolation based on VB+VLAN. Supports the query of the number of the learned MAC addresses according to VB+VLAN or VB+LP. MTU The packet length can be set from 1518 bytes to 9600 bytes. After the packet length setting takes effect, the maximum length of the packets entering or going out from the IP port are limited by the MTU setting. Supported.
MPLS
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Function and Feature VLAN VLAN convergence RSTP Multicast (IGMP Snooping) ETH-OAM
EFS4 Compliant with IEEE 802.1q/p. Supported (4k VLAN). Supports broadcast packet suppression and RSTP, compliant with IEEE 802.1w. Supported. The N2EFS4 supports CC for the multicast, LB test for the unicast, Link Trance test(LT), loop detection (LD), auto-negotiation, fault diagnosis, and link performance detection. Supported. The granularity is 64 kbit/s.
CAR
Service based QoS flow classification LCAS LPT Link Aggreation Flow control function Test frame Loopback function Ethernet performance monitoring Alarm and performance event
The N1EFS4 supports the port service, port+VLAN ID service, and port +VLAN PRI service. The N2EFS4 supports the port flow, port+VLAN ID flow, and port +VLAN PRI flow. Dynamically increases or decreases the bandwidth, and realizes the protection function, compliant with ITU-T G.7042. Supports the LPT function, which can be enabled or disabled. Supported. Supports the IEEE 802.3x flow control based on port. Receives and transmits Ethernet test frames. Supports inloop at the Ethernet port (PHY layer or MAC layer). Supports inloop and outloop at the VC-3 level. Supports Ethernet performance monitoring at the port level.
Provides rich alarms and performance events for easy management and maintenance of the equipment.
Figure 7-12 shows the block diagram for the functions of the EFS4. Figure 7-12 Block diagram for the functions of the EFS4
E N C P Switch fabric
Data Cross-connect unit
Control FE
Network processor
D E N C P
V C P
Mapping module
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V +1.5 V
Clock module
+1.8 V +2.5 V
DC/DC converter
DC/DC converter
Fuse
Fuse
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Ethernet/ VLAN
In the receive direction, services are mapped and forwarded by adding Tunnel and VC double labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per the level (P or PE) of the equipment. Services are then routed or forwarded. The network processor module:
l l l l l
Supports flow sense and flow classification Supports uni-cast, multi-cast and broadcast of the flow Provides data priority setting Provides weighted fair queuing (WFQ) Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP-F format. The concatenation is processed. The LCAS function is supported. Ethernet signals are then converted into SDH signals. In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
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Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EFS4
STAT ACT PROG SRV
FE1
FE2
FE3
FE4
EFS4
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Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four FE interfaces on the front panel of the EFS4. Table 7-21 lists the type and usage of the interfaces. Table 7-21 Optical interfaces of the EFS4 Interface FE1 FE2 FE3 FE4 Interface Type RJ-45 RJ-45 RJ-45 RJ-45 Usage Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals.
Table 7-22 lists the pins of the RJ-45 interface. Table 7-22 Pins of the RJ-45 of the EFS4 Pin 1 2 3 4 5 6
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Description Transmitting positive Transmitting negative Receiving positive Grounding Grounding Receiving negative
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Pin 7 8
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Mechanical Specifications
The mechanical specifications of the EFS4 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the EFS4 is 30 W.
7.7 EGS2
This section describes the EGS2, a 2 x GE Ethernet processing board with Lanswitch, in terms of the version, function, principle, front panel, configuration and specifications. 7.7.1 Version Description The EGS2 has two functional versions, N1 and N2. The two versions have different functions and features. 7.7.2 Function and Feature The EGS2 supports Layer 2 switching, MPLS and broadcast.
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7.7.3 Working Principle and Signal Flow The EGS2 consists of the ethernet access module, network processor module, mapping module, interface converting module, communication and control module and so on. 7.7.4 Front Panel On the front panel of the EGS2, there are indicators, interfaces and barcode. 7.7.5 Valid Slots The EGS2 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The EGS2 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.7.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the EGS2 indicates the optical interface type. 7.7.7 Board Configuration Reference You can use the T2000 to set parameters for the EGS2. 7.7.8 Technical Specifications The specifications of the EGS2 cover the optical interface specifications, mechanical specifications and power consumption.
Table 7-24 lists the functions and features of the EGS2. Table 7-24 Functions and features of the EGS2 Function and Feature Basic function Specification of the optical interface EGS2 Processes 2 x GE services. The optical interfaces are 1000Base-SX/LX/ZX Ethernet optical interfaces. The optical interfaces support the auto-negotiation, compliant with IEEE 802.3z. The optical interfaces use the hot-swappable optical module SFP. When multimode optical fiber is used, the maximum transmission distance is 550 m. When single-mode optical fiber is used, the maximum transmission distance is 10 km. The optical modules can be used for different requirements for the transmission distance, such as 40 km and 70 km. Format of service frames Max. uplink bandwidth Number of VCTRUNKs Mapping granularity Encapsulation format Supports Ethernet II, IEEE 802.3, and IEEE 802.1q/p. Supports frames with a length ranging from 64 bytes to 9600 bytes. Supports Jumbo frames with a length less than 9600 bytes. The maximum uplink bandwidth of the N1EGS2 is 1.25 Gbit/s. The maximum uplink bandwidth of the N2EGS2 is 2.5 Gbit/s. The number of the VCTRUNKs of the N1EGS2 is 24. The number of the VCTRUNKs of the N2EGS2 is 48. Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X12). The encapsulation formats for the N1EGS2 are GFP-F, LAPS, and HDLC. The encapsulation format for the N2EGS2 is GFP-F. EPL EVPL Supports transparent transmission based on port. Not supported by the N1EGS2. The N2EGS2 supports EVPL services based on port+VLAN that use the frame encapsulation formats of MartinioE and stack VLAN.
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EGS2 Supports the Layer 2 convergence and point to multipoint convergence. Supports the Layer 2 forwarding function and switching at the client and SDH sides. Supports the function of self-learning the source MAC address. The length of the MAC address table is 16k. The aging time of the MAC address can be set and queried. Supports the configuration of the static MAC route. Supports the creation, deletion and query of the VB. The maximum number of the VBs is 2. The maximum number of logical ports for each VB is 30.
EVPLAN MTU
Supports data isolation based on VB+VLAN. The packet length can be set from 1518 bytes to 9600 bytes. After the packet length setting takes effect, the maximum length of the packets entering or going out from the IP port are limited by the MTU setting. Not supported by the N1EGS2. Supported by the N2EGS2.
MPLS
Compliant with IEEE 802.1q/p. Supported (4k VLAN). Not supported by the N1EGS2. The N2EGS2 supports broadcast packet suppression and RSTP, compliant with IEEE 802.1w.
Not supported by the N1EGS2. Supported by the N2EGS2. Supported. The granularity is 64 kbit/s.
The N1EGS2 supports the port service, port+VLAN ID service, and port +VLAN PRI service. The N2EGS2 supports the port flow, port+VLAN ID flow, and port +VLAN PRI flow. Not supported by the N1EGS2. The N2EGS2 supports LCAS, compliant with ITU-T G.7042. Dynamically increases or decreases the bandwidth, and realizes the protection function.
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Function and Feature Flow control function Test frame Loopback function Ethernet performance monitoring Alarm and performance event
EGS2 Supports the IEEE 802.3x flow control based on port. Receives and transmits Ethernet test frames. Supports inloop at the Ethernet port (PHY layer or MAC layer). Supports inloop and outloop at the VC-3 level. Supports Ethernet performance monitoring at the port level.
Provides rich alarms and performance events for easy management and maintenance of the equipment.
Control GE
Network processor
D E N C P
V C P
Mapping module
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V +1.5 V
Clock module
+1.8 V +2.5 V
DC/DC converter
DC/DC converter
Fuse
Fuse
In the receive direction, services are mapped and forwarded by adding Tunnel and VC double labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per the level (P or PE) of the equipment. Services are then routed or forwarded. The network processor module:
l l l l l
Supports flow sense and flow classification Supports uni-cast, multi-cast and broadcast of the flow Provides data priority setting Provides weighted fair queuing (WFQ) Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format. The concatenation is processed. The LCAS function is supported. Ethernet signals are then converted into SDH signals. In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
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EGS2
STAT ACT PROG SRV LINK1 ACT1 LINK2 ACT2
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two GE interfaces on the front panel of the EGS2. Table 7-25 lists the type and usage of the interfaces.
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Table 7-25 Optical interfaces of the EGS2 Interface OUT1/IN1 OUT2/IN2 Interface Type LC (pluggable) LC (pluggable) Usage Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals.
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Mechanical Specifications
The mechanical specifications of the EGS2 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the EGS2 is 43 W.
7.8 EMS4
This section describes the EMS4, a 4 x GE and 16 x FE Ethernet transparent transmission and convergence board, in terms of the version, function, principle, front panel, configuration and specifications.
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7.8.1 Version Description The functional version of the EMS4 board is N1. 7.8.2 Function and Feature The EMS4 supports Layer 2 switching, link convergence, and multicast. 7.8.3 Working Principle and Signal Flow The EMS4 consists of the ethernet access module, mapping module, interface conversion module and so on. 7.8.4 Front Panel On the front panel of the EMS4, there are indicators, interfaces and barcode. 7.8.5 Valid Slots The EMS4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. Without the interface board, the EMS4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. With the interface board, the EMS4 can be housed in any of slots 1213 in the OptiX OSN 1500B subrack. 7.8.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the EMS4 indicates the optical interface type. 7.8.7 Board Protection The EMS4 supports the board protection switching (BPS) and port protection switching (PPS) protection. 7.8.8 Board Configuration Reference You can use the T2000 to set parameters for the EMS4. 7.8.9 Technical Specifications The specifications of the EMS4 cover the optical interface specifications, laser safety class, mechanical specifications and power consumption.
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EMS4 Accesses 16 x FE signals at the electrical interface when used with the ETF8. Accesses 16 x FE signals at the optical interface when used with the EFF8. Accesses 8 x FE signals at the electrical interface and 8 x FE signals at the optical interface when used with the ETF8 and EFF8.
The optical interfaces are 1000Base-SX/LX/ZX Ethernet optical interfaces. Supports the auto-negotiation, compliant with IEEE 802.3z. The optical interfaces use the hot-swappable optical module SFP. When multimode optical fiber is used, the maximum transmission distance is 550 m. When single-mode optical fiber is used, the maximum transmission distance is 10 km. The optical modules can be used for different requirements for the transmission distance, such as 40 km and 70 km. Supports 10Base-T/100Base-TX signals when used with the ETF8. Supports 100Base-FX signals when used with the EFF8. The optical interfaces are compliant with IEEE 802.3u.
Supports Ethernet II, IEEE 802.3, IEEE 802.1q TAG, and IEEE 802.1p TAG. Supports frames with a length ranging from 64 bytes to 9216 bytes. Supports Jumbo frames with a length less than 9216 bytes.
Max. uplink bandwidth Mapping granularity VCG Encapsulation format EPL EVPL
2.5 Gbit/s. Virtual concatenation: VC-12, VC-3, VC-4, VC12-Xv (X64), VC3-Xv (X24), and VC4-Xv (X8). A maximum of 64. Supports GFP-F, LAPS, and HDLG. Supports transparent transmission based on port. Supports 42 x bidirectional services. Supports EVPL services based on port+VLAN. Supports a maximum of 8000 links. Supports EVPL services based on QinQ. Supports service forwarding based on port.
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EMS4 Supports the Layer 2 forwarding function and switching at the client and SDH sides. Supports 1k MAC switching or 4K VLAN MAC switching. Supports the function of self-learning the source MAC address. The length of the MAC address table is 128k. The aging time of the MAC address can be set and queried. The configuration of static MAC routes is supported. Supports the creation, deletion and query of VB. The maximum number of VBs is two.
Supports data isolation based on VB+VLAN. Supports VLAN and QinQ, the addition, deletion and switching of VLAN labels, compliant with IEEE 802.1q/p. The packet length can be set from 1518 bytes to 9216 bytes. After the packet length setting takes effect, the maximum length of the packets entering or going out from the IP port are limited by the MTU setting. Not supports broadcast packet suppression Supports RSTP, compliant with IEEE 802.1w.
RSTP
Multicast(IGMPSnooping) ETH-OAM
Supported. Supports CC for the multicast and LB test for the unicast, loop detection (LD), auto-negotiation, fault diagnosis, and link performance detection.. Supported. Not supported. Supports manual link convergence and static link convergence. Supported (4096 VLAN) in QinQ service. Supported (4095 VLAN) in EVPL service.
Protection CAR
Supports the 1+1 hot backup for the board and the PPS protection. Supported. The granularity is 64 kbit/s.
Supports the PORT flow, PORT+VLAN ID flow and PORT +SVLAN ID flow. Dynamically increases or decreases the bandwidth, and realizes the protection function, compliant with ITU-T G.7042. Supported.
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Function and Feature Distributed link aggregation Flow control function Loopback function Ethernet performance monitoring Alarm and performance event
EMS4 Supports inter-board link aggregation. Supports the IEEE 802.3x flow control based on port. Supports inloop at the Ethernet port (PHY layer) and outloop at the SDH side. Supports Ethernet performance monitoring RMON at the port level and VCTRUNK. Provides rich alarms and performance events for easy management and maintenance of the equipment.
access module
Network processor
D E N C P
V C P
Mapping module
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V +1.5 V
Clock module
+1.8 V +2.5 V
DC/DC converter
DC/DC converter
Fuse
and mapping module. The encapsulation and mapping module then compensates for the time delay of the virtual concatenation services, aligns frames, demaps and decapsulates the frames, strips the data packets, and transmits the data packets to the service processing module. Finally, the service processing module converges the data and transmits the data through the ethernet physical interface.
Ethernet/ VLAN
Supports flow sense and flow classification Supports uni-cast, multi-cast and broadcast of the flow Provides data priority setting Provides weighted fair queuing (WFQ) Provides four classes of services (CoS)
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Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP-F or HDLC format. The concatenation is processed. The LCAS function is supported. Ethernet signals are then converted into SDH signals. In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EMS4
STAT ACT PROG SRV
EMS4
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the EMS4. Table 7-29 lists the type and usage of the optical interfaces. Table 7-29 Optical interfaces of the EMS4 Interface OUT1/IN1 OUT2/IN2 OUT3/IN3 OUT4/IN4 Interface Type LC (pluggable) LC (pluggable) LC (pluggable) LC (pluggable) Usage Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals.
Table 7-31 Valid slots for the EMS4 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500B subrack Valid Slot for the EMS4 Slot 11
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Corresponding Slot for the ETF8 and EFF8 Without the interface board
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Corresponding Slot for the ETF8 and EFF8 Slots 14 and 15 Slots 16 and 17
Protection Principle
When the BPS protection is performed to the EMS4, the GE and FE ports use the single-fed dual-selective scheme to get protected. The EMS4 has four four GE ports and 16 FE ports, which may be connected to many communication devices. Normally, the active board is working and services are transmitted in the two directions of the active link. On the backup link, the EMS4 disables the transmission of all ports. In this case, the ports of opposite board are in the Linkdown state. At the same time, the opposite board enables the transmission and does not transmit services. In this way, the receive ports of the backup EMS4 are not in the Linkdown state. The solid lines in Figure 7-18 show how the EMS4 normally works.
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No.1
A
Standby communication equipment
Active EMS4
No.2
No.3
XCS
B
No.1 No.2
Standby EMS4
No.3
BPS Protection
For the BPS protection, when the active board detects the Linkdown fault of any link or any board fault, the cross-connect board switches all services to the standby board. In this way, services are protected. As the solid lines shown in Figure 7-19. The services numbered 1, 2 and 3 are all switched to the standby EMS4 and corresponding communication equipment.
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No.1
Active EMS4
No.2
No.3
XCS
B
No.1 No.2
Standby EMS4
No.3
PPS Protection
For the PPS protection, when the active board detects the Linkdown fault of any link or any board fault, the cross-connect board switches all services to the standby board. In this way, services are protected. The solid lines in Figure 7-20 show how the PPS protection is performed. Only the service numbered 1 is switched to the standby EMS4 and the standby communication equipment.
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No.1
A
Standby communication equipment
Active EMS4
No.2
XCS
B
No.1 No.2 Standby communication equipment
Standby EMS4
No.3
The conditions that trigger the protection for the EMS4 are as follows:
l l
Fault at at the PHY layer of the MAC port, also Linkdown Fault in key board hardware units, such as the power supply module and the optical module
WARNING
When the board-level protection is performed, FE ports only support the 100M full duplex mode and GE ports support the auto-negotiation and 1000M full duplex mode.
Board Configuration
Two EMS4 boards should be configured for the protection. One EMS4 is the active board and the other is the standby board. For the configuration of the EMS4 board protection, it is required that the access capacity of the protection slot must be not less than the access capacity of the working slot.
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Mechanical Specifications
The mechanical specifications of the EMS4 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
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Power Consumption
In the normal temperature (25), the maximum power consumption of the EMS4 is 65 W if the EMS4 is not used with an interface board. In the normal temperature (25), the maximum power consumption of the EMS4 is 75 W if the EMS4 is used with an interface board.
7.9 EGS4
This section describes the EGS4, a 4 x GE Ethernet convergence board, in terms of the version, function, principle, front panel, configuration and specifications. 7.9.1 Version Description The EGS4 has two functional versions, N1 and N3. 7.9.2 Function and Feature The EGS4 supports Layer 2 switching, MPLS and broadcast. 7.9.3 Working Principle and Signal Flow The EGS4 consists of the interface module, service processing module, encapsulation and mapping module, interface converting module, control and communication module and the power supply module. 7.9.4 Front Panel On the front panel of the EGS4, there are indicators, interfaces and barcode. 7.9.5 Valid Slots The EGS4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The EGS4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.9.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the EGS4 indicates the optical interface type. 7.9.7 Board Protection The EGS4 supports the board protection switching (BPS) and port protection switching (PPS) protection. 7.9.8 Board Configuration Reference You can use the T2000 to set parameters for the EGS4. 7.9.9 Technical Specifications The specifications of the EGS4 cover the optical interface specifications, laser safety class, mechanical specifications and power consumption.
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Table 7-34 Version Description of the EGS4 Item Functional version Difference Description The EGS4 has two functional versions, N1 and N3. The N1EGS4 supports the binding to a maximum of 1008 VC12s. The N3EGS4 supports the binding to a maximum of 504 VC12s:
l
VC4/VC3:These VC4s/VC3s belong in the following two ranges: VC4-1 to VC4-8 and VC4-9 to VC4-16. The VC4s/VC3s of only one range can be bound at a time. VC12:These VC12s belong in the following two ranges: VC4-1 to VC4-4 and VC4-9 to VC4-12. The VC12s of only one range can be bound at a time.
Replaceability
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Function and Feature Mapping granularity VCG Encapsulation format EPL EVPL
EGS4 Virtual concatenation: VC-12, VC-3, VC-4, VC12-Xv (X64), VC3-Xv (X24), and VC4-Xv (X8). 64 to the maximum. Supports GFP-F, LAPS, and HDLG. Supports transparent transmission based on port. Supports EVPL services based on port+VLAN. Supports a maximum of 8000 links. Supports EVPL services based on QinQ. Supports service forwarding based on port.
EPLAN
Supports the Layer 2 forwarding function and switching at the client and SDH sides. Supports 1k MAC switching or 4k VLAN MAC switching. Supports the function of self-learning the source MAC address. The length of the MAC address table is 128k. The aging time of the MAC address can be set and queried. The configuration of static MAC routes is supported. Supports data isolation based on VB+VLAN. Supports the creation, deletion and query of VB. The maximum number of VBs is two.
VLAN MTU
Supports VLAN and QinQ, the addition, deletion and switching of VLAN labels, compliant with IEEE 802.1q/p. The packet length can be set from 1518 bytes to 9216 bytes. After the packet length setting takes effect, the maximum length of the packets entering or going out from the IP port are limited by the MTU setting. Not supports broadcast packet suppression Supports RSTP, compliant with IEEE 802.1w.
RST
Multicast(IGMPSnooping) ETH-OAM
Supported. Supports CC for the multicast and LB test for the unicast, loop detection (LD), auto-negotiation, fault diagnosis, and link performance detection... Supported. Not supported. Supports manual link convergence and static link convergence. Supported (4096 VLAN) in QinQ service. Supported (4095 VLAN) in EVPL service.
Protection
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Supports the 1+1 hot backup for the board and the PPS protection.
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EGS4 Supported. The granularity is 64 kbit/s. N1EGS4 Supports 512 rate, EGS4 Supports 60 rate.
Flow classification LCAS LPT Distributed link aggregation Flow control function Loopback function Ethernet performance monitoring Alarm and performance event
Supports the port flow and port+VLAN ID flow. Dynamically increases or decreases the bandwidth, and realizes the protection function, compliant with ITU-T G.7042. Supported. Supports inter-board link aggregation. Supports the IEEE 802.3x flow control based on port. Supports inloop at the Ethernet port (PHY layer). Supports Ethernet performance monitoring RMON at the port level and VCTRUNK. Provides rich alarms and performance events for easy management and maintenance of the equipment.
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Control GE
Network processor
D E N C P
V C P
Mapping module
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V +1.5 V
Clock module
+1.8 V +2.5 V
DC/DC converter
DC/DC converter
Fuse
conversion is unnecessary. At PHY layer, the electrical signals are decoded and the ETH_LOS alarms are tested. The electrical signals are converted from serial signals to parallel signals and then sent to network processor. In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer, signals are encoded and converted from electrical signals to optical signals.
Ethernet/ VLAN
Supports flow sense and flow classification Supports uni-cast, multi-cast and broadcast of the flow Provides data priority setting Provides weighted fair queuing (WFQ) Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP-F or HDLC format. The concatenation is processed. The LCAS function is supported. Ethernet signals are then converted into SDH signals. In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
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The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
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EGS4
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the EGS4. Table 7-36 lists the type and usage of the optical interfaces.
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Table 7-36 Optical interfaces of the EGS4 Interface OUT1/IN1 OUT2/IN2 OUT3/IN3 OUT4/IN4 Interface Type LC (pluggable) LC (pluggable) LC (pluggable) LC (pluggable) Usage Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals.
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Protection Principle
When the BPS protection is performed to the EGS4, the GE and FE ports use the single-fed dualselective scheme to get protected. The EGS4 has four four GE ports and 16 FE ports, which may be connected to many communication devices. Normally, the active board is working and services are transmitted in the two directions of the active link. On the standby link, the EGS4 disables the transmission of all ports. In this case, the ports of the opposite board are in the Linkdown state. At the same time, the opposite board enables the transmission and does not transmit services. In this way, the receive ports of the standby EGS4 are not in the Linkdown state. The solid lines in Figure 7-23 show how the EGS4 normally works. Figure 7-23 Normal working of the EGS4
Active communication equipment Standby communication equipment
No.1
Active EGS4
No.2
No.3
XCS
B
No.1 No.2
Standby EGS4
No.3
BPS Protection
For the BPS protection, when the active board detects the Linkdown fault of any link or any board fault, the cross-connect board switches all services to the standby board. In this way, services are protected. The lines in Figure 7-24 show how the BPS protection is performed. The services numbered 1, 2 and 3 are all switched to the standby EGS4 and corresponding communication equipment.
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No.1
Active EGS4
No.2
No.3
XCS
No.1 No.2
B
Standby communication equipment
Standby EGS4
No.3
PPS Protection
For the PPS protection, when the active board detects the Linkdown fault of any link or any board fault, the cross-connect board switches all services to the standby board. In this way, services are protected. The solid lines in Figure 7-25 show how the PPS protection is performed. Only the service numbered 1 is switched to the standby EGS4 and the standby communication equipment.
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No.1
A
Standby communication equipment
Active EGS4
No.2
XCS
No.1 No.2
B
Standby communication equipment
Standby EGS4
No.3
The conditions that trigger the protection for the EGS4 are as follows:
l l
Fault at at the PHY layer of the MAC port, also Linkdown Fault in key board hardware units, such as the power supply module and the optical module
WARNING
When the protection is performed, the GE ports support auto-negotiation and 1000M full duplex modes.
Board Configuration
Two EGS4 boards should be configured for the protection. One EGS4 is the active board and the other is the standby board. For the configuration of the EGS4 board protection, it is required that the access capacity of the protection slot must be not less than the access capacity of the working slot.
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Mechanical Specifications
The mechanical specifications of the EGS4 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
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Power Consumption
In the normal temperature (25), the maximum power consumption of the EGS4 is 70 W.
7.10 EGS4A
This section describes the EGS4A, a 4 x GE Ethernet convergence board, in terms of the version, function, principle, front panel, configuration and specifications. 7.10.1 Version Description The functional version of the EGS4A board is N2. 7.10.2 Function and Feature The EGS4A supports Layer 2 switching, MPLS and broadcast. 7.10.3 Working Principle and Signal Flow The EGS4A consists of the interface module, service processing module, encapsulation and mapping module, interface converting module, control and communication module and the power supply module. 7.10.4 Front Panel On the front panel of the EGS4A, there are indicators, interfaces and barcode. 7.10.5 Valid Slots The EGS4A can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The EGS4A can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.10.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the EGS4A indicates the optical interface type. 7.10.7 Board Protection The EGS4A supports the board protection switching (BPS). 7.10.8 Board Configuration Reference You can use the T2000 to set parameters for the EGS4A. 7.10.9 Technical Specifications The specifications of the EGS4A cover the optical interface specifications, laser safety class, mechanical specifications and power consumption.
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Table 7-39 Functions and features of the EGS4A Function and Feature Basic function Specification of the optical interface EGS4A Accesses and processes 4 x GE services. The optical interfaces are 1000Base-SX/LX/ZX Ethernet optical interfaces. The optical interfaces support the auto-negotiation, compliant with IEEE 802.3z. The optical interfaces use the hot-swappable optical module SFP. When multimode optical fiber is used, the maximum transmission distance is 550 m. When single-mode optical fiber is used, the maximum transmission distance is 10 km. The optical modules can be used for different requirements for the transmission distance, such as 40 km and 70 km. Format of service frames Supports Ethernet II, IEEE 802.3, IEEE 802.1q TAG, and IEEE 802.1p TAG. Supports frames with a length ranging from 64 bytes to 9216 bytes. Supports Jumbo frames with a length less than 9216 bytes. Max. uplink bandwidth Mapping granularity VCG Encapsulation format EPL EVPL 2.5 Gbit/s. VC4-4c, VC4-16c, VC3-Xv (X48), and VC4-Xv (X16). 32 Supports GFP-F, LAPS, and HDLG. Supports transparent transmission based on port. Support port+VLAN-based EVPL service and service forward. Support QinQ-based EVPL service and service forward. Support port-based service forward. EPLAN Support Layer 2 switching. Support self-learning of MAC address. Support setting and querying the MAC address aging time. The MAC address table has 64k entries. Support configuration of static MAC route. Support creating, deleting and querying a VB. The maximum number of VBs is 30 and that of logic ports is 64 for each VB. EVPLAN Support virtual bridge (VB) + VLAN based data isolation. Support creating, deleting and querying the VLAN broadcast table. VLAN Supports VLAN and QinQ, the addition, deletion and switching of VLAN labels, compliant with IEEE 802.1q/p.
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EGS4A The packet length can be set from 1518 bytes to 1535 bytes. After the packet length setting takes effect, the maximum length of the packets entering or going out from the IP port are limited by the MTU setting. Not support. Not support. Support Multicast CC, LB testing, fault detection in compliance with IEEE 802.1ag and 802.3ah. Supported. Not supported. Support manual link aggregation and static link aggregation. Supported (4096 VLAN). Supports the BPS protection. Support the settings of four parameters: CIR, CBS, PIR and PBS. Support the traffic classification based on PORT, PORT+VLAN, PORT+VLAN+PRI, PORT+S and PORT+S+C. Dynamically increases or decreases the bandwidth, and realizes the protection function, compliant with ITU-T G.7042. Not supported. Supports inter-board link aggregation. Supports the IEEE 802.3x flow control based on port. Supports inloop at the Ethernet port (PHY layer). Supports Ethernet performance monitoring RMON at the port level and VCTRUNK. Provides rich alarms and performance events for easy management and maintenance of the equipment.
RST Multicast(IGMPSnooping) ETH-OAM Test frame Service mirroring Link convergence VLAN convergence Protection CAR Flow classification LCAS LPT Distributed link aggregation Flow control function Loopback function Ethernet performance monitoring Alarm and performance event
Control GE
Network processor
D E N C P
V C P
Mapping module
LOS
Communication Reference clock and frame header SCC unit SCC unit
+3.3 V +1.5 V
Clock module
+1.8 V +2.5 V
DC/DC converter
DC/DC converter
Fuse
conversion is unnecessary. At PHY layer, the electrical signals are decoded and the ETH_LOS alarms are tested. The electrical signals are converted from serial signals to parallel signals and then sent to network processor. In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer, signals are encoded and converted from electrical signals to optical signals.
Ethernet/ VLAN
Supports flow sense and flow classification Supports uni-cast, multi-cast and broadcast of the flow Provides data priority setting Provides weighted fair queuing (WFQ) Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP or HDLC format. The concatenation is processed. The LCAS function is supported. Ethernet signals are then converted into SDH signals. In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the network processor module in packets.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
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The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
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EGS4A
STAT ACT PROG SRV
LINK ACT
EGS4A
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the EGS4A. Table 7-40 lists the type and usage of the optical interfaces.
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Table 7-40 Optical interfaces of the EGS4A Interface OUT1/IN1 OUT2/IN2 OUT3/IN3 OUT4/IN4 Interface Type LC (pluggable) LC (pluggable) LC (pluggable) LC (pluggable) Usage Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals.
Protection Principle
When the BPS protection is performed to the EGS4A, the GE and FE ports use the single-fed dual-selective scheme to get protected. The EGS4A has four four GE ports and 16 FE ports, which may be connected to many communication devices. Normally, the active board is working and services are transmitted in the two directions of the active link. On the standby link, the EGS4A disables the transmission of all ports. In this case, the ports of the opposite board are in
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the Linkdown state. At the same time, the opposite board enables the transmission and does not transmit services. In this way, the receive ports of the standby EGS4A are not in the Linkdown state. The solid lines in Figure 7-28 show how the EGS4A normally works. Figure 7-28 Normal working of the EGS4A
Active communication equipment Standby communication equipment
No.1
Active EGS4
No.2
No.3
XCS
B
No.1 No.2
Standby EGS4
No.3
BPS Protection For the BPS protection, when the active board detects the Linkdown fault of any link or any board fault, the cross-connect board switches all services to the standby board. In this way, services are protected. The lines in Figure 7-29 show how the BPS protection is performed. The services numbered 1, 2 and 3 are all switched to the standby EGS4A and corresponding communication equipment.
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No.1
Active EGS4
No.2
No.3
XCS
No.1 No.2
B
Standby communication equipment
Standby EGS4
No.3
The conditions that trigger the protection for the EGS4A are as follows:
l l
Fault at at the PHY layer of the MAC port, also Linkdown Fault in key board hardware units, such as the power supply module and the optical module
WARNING
When the protection is performed, the GE ports support auto-negotiation and 1000M full duplex modes.
Board Configuration
Two EGS4A boards should be configured for the protection. One EGS4A is the active board and the other is the standby board. For the protection, the access capacity of the slot for the standby board must be larger than that of the slot for the active board.
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Mechanical Specifications
The mechanical specifications of the EGS4A are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
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Power Consumption
In the normal temperature (25), the maximum power consumption of the EGS4A is 53 W.
7.11 EGR2
This section describes the EGR2, a 2 x GE Ethernet processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.11.1 Version Description The functional version of the EGR2 board is N2. 7.11.2 Function and Feature The EGR2 supports Layer 2 switching, port convergence, and RPR. 7.11.3 Working Principle and Signal Flow The EGR2 consists of the ethernet processing module, network processor module, RPR protocol processing module and so on. 7.11.4 Front Panel On the front panel of the EGR2, there are indicators, interfaces, barcode and laser safety class label. 7.11.5 Valid Slots The EGR2 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The EGR2 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.11.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the EGR2 indicates the optical interface type. 7.11.7 Board Configuration Reference You can use the T2000 to set parameters for the EGR2. 7.11.8 Technical Specifications The technical specifications of the EGR2 cover the optical interface specifications, board dimensions, weight and power consumption.
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EGR2 The optical interfaces are 1000Base-SX/LX/ZX Ethernet optical interfaces. The optical interfaces support the auto-negotiation, compliant with IEEE 802.3z. The optical interfaces use the hot-swappable optical module SFP. When multimode optical fiber is used, the maximum transmission distance is 550 m. When single-mode optical fiber is used, the maximum transmission distance is 10 km. The optical modules can be used for different requirements for the transmission distance, such as 40 km and 70 km.
Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG. Supports frames with a length ranging from 64 bytes to 9600 bytes. Supports Jumbo frames with a length less than 9600 bytes.
2.5 Gbit/s. Supports VC-3, VC3-2v, VC-4, and VC4-Xv (X8). Supports GFP-F and LAPS. Supports EVPL services. The frame format can be Ethernet II, IEEE 802.3, IEEE 802.1q TAG, or MPLS Martini. Supports the MPLS encapsulation and forwarding based on port and port+VLAN. Supports five types of LSP, including ingress LSP, egress LSP, transit LSP, RPR ingress LSP, and RPR transit LSP. Supports 512 LSPs.
EVPLAN
Supports EVPLAN services and uses the stack VLAN encapsulation. Supports the function of self-learning the source MAC address. For the N2EGR2, the capacity of the MAC address table is 64k. The aging time of the MAC address can be set and queried. Supports the configuration of static MAC routes (maximum: 4k). Supports data isolation based on VB+VLAN. Supports the creation, deletion and query of the VB. The maximum number of the VBs is 16. The maximum number of logical ports for each VB is 32.
MTU
The packet length can be set from 1518 bytes to 9600 bytes. After the packet length setting takes effect, the maximum length of the packets entering or going out from the IP port are limited by the MTU setting. Supports MartinioE. Supported. Supports 4096 VLAN labels, the addition and deletion of VLAN labels, and the switching function, compliant with IEEE 802.1q/p.
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Function and Feature VLAN convergence VLAN switching Port convergence RPR
EGR2 Supported (4k VLAN). Supports the replacement of VLAN in Ethernet signal frames. Supports the convergence at a maximum of two GE ports. Supports RPR, compliant with IEEE 802.17. The ring network supports a maximum of 255 nodes, and it supports the dropping of sink nodes and weighted fairness algorithm. Supports five priority levels, including A0, A1, B_EIR, B_CIR and C. Provides topology automatic discovery function, and detects the network status in real time. Supports three protection modes, including Steering, Wrapping, and Wrapping+Steering. The invalid time for signals is less than 50 ms. Supports the manual configuration of the ringlet route in the RPR ring network. Supports the ringlet self-learning, which learns the mapping relation between the MAC address and node number.
Supports broadcast packet suppression and RSTP, compliant with IEEE 802.1w. Supported. Supported. The granularity is 64 kbit/s.
Flow classification LCAS Flow control function Echo test frame Loopback function Ethernet performance monitoring Alarm and performance event Weighted fairness algorithm
Supports the port flow, port+VLAN ID flow, and port+VLAN ID +VLAN PRI flow. Dynamically increases or decreases the bandwidth, and realizes the protection function, compliant with ITU-T G.7042. Supports the IEEE 802.3x flow control based on port. Supports the Echo function of the PRP OAM, which is used to test the availability of the link. Supports inloop at the Ethernet port (PHY layer or MAC layer). Supports Ethernet performance monitoring at the port level.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supported.
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Function and Feature Topology automatic discovery Max. number of nodes Service priority level
EGR2 Supported.
E N C P
Crossconnect unit V C P
access module
Network processor
Data
Switch fabric
Crossconnect unit
Mapping module
Communication
Clock module
DC/DC converter
Fuse
Fuse
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In the receive direction, services are mapped and forwarded by adding Tunnel and VC double labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per the level (P or PE) of the equipment. Services are then routed or forwarded. The network processor module:
l l l l l
Supports flow sense and flow classification Supports uni-cast, multi-cast and broadcast of the flow Provides data priority setting Provides weighted fair queuing (WFQ) Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, the virtual concatenation supports LCAS function. The encapsulation formats are LAPS and GFP-F. In the downstream direction, virtual concatenations are received. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the RPR protocol processing module in packets.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 100 MHz.
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two optical interfaces on the front panel of the EGR2. Table 7-44 lists the type and usage of the optical interfaces.
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Table 7-44 Optical interfaces of the EGR2 Interface OUT1/IN1 OUT2/IN2 Interface Type LC (pluggable) LC (pluggable) Usage Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 1000Base-SX/LX/ZX signals.
Working mode Enabling of the LCAS Maximum packet length Mapping protocol
Table 7-46 lists the specifications of the interfaces of the EGR2. Table 7-46 Specifications of the interfaces of the EGR2 Optical Optical Interface Type Source Type 1000Base-ZX (70 km) 1000Base-ZX (40 km) 1000Base-LX (10 km) 1000Base-SX (0.55 km) MLM MLM MLM MLM Launched Optical Power (dBm) 4 to +2 2 to +5 9 to 3 9.5 to 0 Central Wavele ngth (nm) 1480 to 1580 1270 to 1355 1270 to 1355 770 to 860 Overloa d Optical Power (dBm) 3 3 3 0 Receiver Sensitivit y (dBm) 22 23 19 17 Extin ction Ratio (dB) 9 9 9 9
Mechanical Specifications
The mechanical specifications of the EGR2 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
Power Consumption
In the normal temperature (25), the maximum power consumption of the EGR2 is 40 W.
7.12 EMR0
This section describes the EMR0, a 12 x FE and 1 x GE Ethernet ring processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.12.1 Version Description The EMR0 has two versions, N1 and N2. The production of the N1 version is stopped. 7.12.2 Function and Feature The EMR0 supports Layer 2 switching, port convergence, and RPR. 7.12.3 Working Principle and Signal Flow The EMR0 consists of the ethernet processing module, network processor module, RPR protocol processing module, mapping module and so on.
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7.12.4 Front Panel On the front panel of the EMR0, there are indicators, interfaces, barcode and laser safety class label. 7.12.5 Valid Slots The EMR0 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. Without the interface board, the EMR0 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. With the interface board, the EMR0 can be housed in any of slots 1213 in the OptiX OSN 1500B subrack. 7.12.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the EMR0 indicates the optical interface type. 7.12.7 Board Configuration Reference You can use the T2000 to set parameters for the EMR0. 7.12.8 Technical Specifications The technical specifications of the EMR0 cover the optical interface specifications, board dimensions, weight and power consumption.
Replaceability
Table 7-48 Comparison of features of the N1EMR0 and N2EMR0 Item Port convergence function VLAN label switching EVPLAN services N1EMR0 Supports EVPLAN services and uses the stack VLAN encapsulation. N2EMR0 Supports the convergence function at a maximum of eight FE ports. Supports the VLAN label switching for the Ethernet data. Supports EVPLAN services and uses the stack VLAN encapsulation.
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N1EMR0 Supports the 16k MAC address table. Supports the creation, deletion and query of the VB. The maximum number of the VBs is 32. The maximum number of logical ports for each VB is 16. -
N2EMR0 Supports the 64k MAC address table. Supports the creation, deletion and query of the VB. The maximum number of the VBs is 16. The maximum number of logical ports for each VB is 32.
Supports the manual configuration of the ringlet route in the RPR ring network. Supports the Echo function of the PRP OAM, which is used to test the availability of the link. Supported. Supports the port flow, port+VLAN ID flow, and port+VLAN ID+VLAN PRI flow.
RPR OAM
Supported. Supports the port flow, port +VLAN ID flow, and port +VLAN PRI flow.
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Function and Feature Format of service frames Max. uplink bandwidth Mapping granularity Encapsulation format EVPL
EMR0 Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG . Supports frames with a length ranging from 64 bytes to 9600 bytes. Supports Jumbo frames with a length less than 9600 bytes. 2.5 Gbit/s. VC-3, VC3-2v, VC-4, and VC4-Xv (X8). Supports GFP-F and LAPS. Supports EVPL services. The frame format can be Ethernet II, IEEE 802.3, IEEE 802.1q TAG, or MPLS Martini. EVPL services support the MPLS encapsulation and forwarding based on port and port +VLAN. Supports five types of LSP, including ingress LSP, egress LSP, transit LSP, RPR ingress LSP, and RPR transit LSP. Supports 512 LSPs. Supports EVPLAN services and uses the stack VLAN encapsulation. Supports the function of self-learning the source MAC address. For the N2EMR0, the capacity of the MAC address table is 16k. The aging time of the MAC address can be set and queried. Supports the configuration of static MAC routes (maximum: 4k). Supports data isolation based on VB+VLAN. Supports the creation, deletion and query of the VB. The N2EMR0 supports a maximum of 16 VBs. The maximum number of logical ports for each VB is 32.
EVPLAN
MTU
The packet length can be set from 1518 bytes to 9600 bytes. After the packet length setting takes effect, the maximum length of the packets entering or going out from the IP port are limited by the MTU setting. Supports MartinioE. Supported. Supports 4096 VLAN labels, the addition and deletion of VLAN labels, and the switching function, compliant with IEEE 802.1q/p. Supported (4k VLAN). Supports the replacement of VLAN in Ethernet signal frames. Supports the convergence function at a maximum of eight FE ports.
MPLS Stack VLAN VLAN VLAN convergence VLAN switching Port convergence
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EMR0 Supported and compliant with IEEE 802.17. Supports a maximum of 255 nodes in the ring network, and the dropping of sink nodes. Supports weighted fairness algorithm. Supports five priority levels, including A0, A1, B_EIR, B_CIR and C. Provides topology automatic discovery function, and detects the network status in real time. Supports three protection modes, including Steering, Wrapping, and Wrapping+Steering. The invalid time for signals is less than 50 ms. Supports the ringlet self-learning, which learns the mapping relation between the MAC address and node number. The N2EMR0 supports the manual configuration of the ringlet route in the RPR ring network.
Supports broadcast packet suppression and RSTP, compliant with IEEE 802.1w. Supported. Supported. The granularity is 64 kbit/s.
Flow classification LCAS Flow control function Echo test frame Loopback function Ethernet performance monitoring Alarm and performance events Weighted fairness algorithm Topology automatic discovery
The N2EMR0 supports the port flow, port+VLAN ID flow, and port +VLAN ID+VLAN PRI flow. Dynamically increases or decreases the bandwidth and realizes the protection function, compliant with ITU-T G.7042. Supports the IEEE 802.3x flow control based on port. Supports the Echo function of the PRP OAM, which is used to test the availability of the link. Supports inloop at the Ethernet port (PHY layer or MAC layer). Supports Ethernet performance monitoring at the port level.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supported. Supported.
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E N C P
Crossconnect unit V C P
access module
Network processor
Data
Switch fabric
Crossconnect unit
Mapping module
Communication
Clock module
DC/DC converter
Fuse
Fuse
alarms are tested. The electrical signals are converted from serial signals to parallel signals and then sent to network processor. In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer, signals are encoded and converted from electrical signals to optical signals.
In the receive direction, services are mapped and forwarded by adding Tunnel and VC double labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per the level (P or PE) of the equipment. Services are then routed or forwarded. The network processor module:
l l l l l
Supports flow sense and flow classification Supports uni-cast, multi-cast and broadcast of the flow Provides data priority setting Provides weighted fair queuing (WFQ) Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping. In the upstream direction, the virtual concatenation supports LCAS function. The encapsulation formats are LAPS and GFP-F.
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In the downstream direction, virtual concatenations are received. The time delay of virtual concatenation is compensated. After aligning, packets are decapsulated as per encapsulation format. The decapsulated data are transmitted to the RPR protocol processing module in packets.
Manages and configures other modules of the boards. Performs inter-board communication through internal Ethernet interface.
The control module also contains basic logic units. This module enjoys the following functions:
l l l l l l l l
Writes and reads register Provides interface for CPU Checks, selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Controls the shutting down of the optical module Processes communication Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 100 MHz.
OUT1 IN1
FE1
FE2
FE3
FE4
EMR0
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OUT1 IN1
FE1
FE2
FE3
FE4
EMR0
Indicators
The following indicators are present on the front panel of the board:
l l l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
There are five interfaces on the front panel of the EMR0. Table 7-50 lists the type and usage of the interfaces. Table 7-50 Optical interfaces of the EMR0 Interface OUT1/IN1 FE1 FE2 FE3 FE4 Interface Type LC (pluggable) RJ-45 RJ-45 RJ-45 RJ-45 Usage Transmits and receives the 1000Base-SX/LX/ZX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals. Transmits and receives the 10Base-T/100Base-TX signals.
Table 7-52 Valid slots for the EMR0 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500B subrack Valid Slot for the EMR0 Slot 11
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Corresponding Slot for the ETF8 and EFF8 Without the interface board
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Working mode Enabling of the LCAS Maximum packet length Mapping protocol
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Table 7-54 Specifications of the optical interfaces of the EMR0 Item Optical interface type Optical source type Launched optical power (dBm) Central wavelength (nm) Overload optical power (dBm) Receiver sensitivity (dBm) Extinction ratio (dB) Specification 1000Base-ZX (70 km) MLM 4 to +2 1480 to 1580 3 22 9 1000Base-ZX (40 km) MLM 2 to +5 1270 to 1355 3 23 9 1000Base-LX (10 km) MLM 9 to 3 1270 to 1355 3 19 9 1000Base-SX (0.55 km) MLM 9.5 to 0 770 to 860 0 17 9
Mechanical Specifications
The mechanical specifications of the EMR0 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.2
Power Consumption
In the normal temperature (25), the maximum power consumption of the EMR0 is 50 W.
7.13 ADL4
This section describes the ADL4, a 1 x STM-4 ATM processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.13.1 Version Description The functional version of the ADL4 board is N1. 7.13.2 Function and Feature The ADL4 supports the ATM switching and ATM protection. 7.13.3 Working Principle and Signal Flow
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The ADL4 consists of the O/E converting module, physical layer module, ATM module and so on. 7.13.4 Front Panel On the front panel of the ADL4, there are indicators, interfaces, barcode and laser safety class label. 7.13.5 Valid Slots The ADL4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The ADL4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.13.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the ADL4 indicates the optical interface type. 7.13.7 Board Configuration Reference You can use the T2000 to set parameters for the ADL4. 7.13.8 Technical Specifications The technical specifications of the ADL4 cover the optical interface specifications, board dimensions, weight and power consumption.
ADL4 Accesses and processes 1 x STM-4 ATM services. Supports the optical interfaces of the S-4.1, L-4.1, L-4.2 and Ve-4.2 types. LC. SFP. Supports 12 x E3 signals, which are accessed by the PD3/PL3/ N1PL3A. Not supported. Supports 8 x VC-4, or 12 x VC-3 and 4 x VC-4. 1.2 Gbit/s. Supports VC-3, VC-4, or VC4-Xv (X: 14).
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Function and Feature Service type ATM connection Statistical multiplexing Flow type and QoS ATM multicast connection ATM protection (ITUT I.630) OAM function (ITU-T I.610) Maintenance feature
ADL4 Supports CBR, rt-VBR, nrt-VBR and UBR. 2048. Supported. Supports IETF RFC2514, ATM forum TM4.0. Supports spacial multicast and logical multicast. Supports unidirectional or bidirectional 1+1, 1:1, VP-Ring, VCRing protection schemes. Supports AIS, RDI, LB , and CC. Supports inloop and outloop at the ATM layer levels and the optical interface (except the outloop at external port), which are used for maintenance and fault locating. Provides rich alarms and performance events. The loopback is used for maintenance and fault locating.
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E/O
622Mbit/s
Cross-connet unit A
Mapping module
high speed bus Cross-connet unit B
LOS
Cross-connet unit
Communication
Scc unit
Clock module
3.3 V
DC/DC converter
Fuse
DC/DC converter
Mappings ATM cells into SDH frames Demappings SDH frames to ATM cells Processes ATM service physical layer functions: cell delimitation, test and generation of HEC series
ATM Module
The ATM module mainly performs ATM layer functions in the ATM protocol. These functions include:
l l l
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E3 Module
The E3 module mainly processes the ATM services at E3 rate. This module:
l l l
Mappings the ATM cells into E3 containers Demappings E3 containers to ATM cells Perform ATM physical layer function to the ATM service at E3 rate
Mapping Module
The mapping module:
l l l l
Mappings ATM cells into SDH frame payload Demappings SDH frame payload to ATM cells Supports ATM physical layer functions Supports VC4-Xv (X4) virtual concatenation
Controls writing and reading of each chip Communicates with the NE Issues configured services Reports alarms of each functional module Checks R_LOS alarms of optical modules Controls the shutting of transmission
Clock Module
This module mainly generates working clocks for each chip. The frequencies of the clocks are 50 MHz, 77 MHz and 100 MHz.
ADL4
STAT ACT PROG SRV
OUT1 IN1
ADL4
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one optical interface on the front panel of the ADL4. Table 7-56 lists the type and usage of the optical interface.
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Table 7-56 Optical interface of the ADL4 Interface OUT1/IN1 Interface Type LC (pluggable) Usage Transmits and receives STM-4 optical signals.
Port type Flow type Service type Peak cell rate (PCR) Sustainable cell rate (SCR) Maximum cell burst size Cell delay variation tolerance (CDVT)
Mechanical Specifications
The mechanical specifications of the ADL4 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.9
Power Consumption
In the normal temperature (25), the maximum power consumption of the ADL4 is 41 W.
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7.14 ADQ1
This section describes the ADQ1, a 4 x STM-1 ATM processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.14.1 Version Description The functional version of the ADQ1 board is N1. 7.14.2 Function and Feature The ADQ1 supports the ATM switching and ATM protection. 7.14.3 Working Principle and Signal Flow The ADQ1 consists of the O/E converting module, physical layer module, ATM module and so on. 7.14.4 Front Panel On the front panel of the ADQ1, there are indicators, interfaces, barcode and laser safety class label. 7.14.5 Valid Slots The ADQ1 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The ADQ1 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.14.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the ADQ1 indicates the optical interface type. 7.14.7 Board Configuration Reference You can use the T2000 to set parameters for the ADQ1. 7.14.8 Technical Specifications The technical specifications of the ADQ1 cover the optical interface specifications, board dimensions, weight and power consumption.
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Function and Feature Connector type Optical module type E3 ATM interface IMA function Max. uplink bandwidth ATM switching capability Mapping granularity Service type ATM connection Statistical multiplexing Flow type and QoS ATM multicast connection ATM protection (ITUT I.630) OAM function (ITU-T I.610) Maintenance feature
ADQ1 LC. SFP. Supports 12 x E3 signals, which are accessed by the PD3/PL3/ N1PL3A. Not supported. Supports 8 x VC-4, or 12 x VC-3 and 4 x VC-4. 1.2 Gbit/s. Supports VC-3, VC-4, or VC4-Xv (X: 14). Supports CBR, rt-VBR, nrt-VBR and UBR. 2048. Supported. Supports IETF RFC2514 and ATM forum TM4.0. Supports spacial multicast and logical multicast. Supports unidirectional or bidirectional 1+1, 1:1, VP-Ring, VCRing protection schemes. Supports AIS, RDI, LB , and CC. Supports inloop and outloop at the ATM layer levels and the optical interface (except the outloop at external port), which are used for maintenance and fault locating. Provides rich alarms and performance events, which are used for maintenance and fault locating.
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E/O
4x155Mbit/s
Cross-connet unit A
PHY module
4x155Mbit/s
Mapping module
high speed bus Cross-connet unit B
O/E
4x155Mbit/s
LOS
Cross-connet unit
Communication
Scc unit
Clock module
3.3 V
DC/DC converter
Fuse
DC/DC converter
Mappings ATM cells into SDH frames Demappings SDH frames to ATM cells Processes ATM service physical layer functions: cell delimitation, test and generation of HEC series
ATM Module
The ATM module mainly performs ATM layer functions in the ATM protocol. These functions include:
l l l
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E3 Module
The E3 module mainly processes the ATM services at E3 rate. This module:
l l l
Mappings the ATM cells into E3 containers Demappings E3 containers to ATM cells Perform ATM physical layer function to the ATM service at E3 rate
Mapping Module
The mapping module:
l l l l
Mappings ATM cells into SDH frame payload Demappings SDH frame payload to ATM cells Supports ATM physical layer functions Supports VC4-Xv (X4) virtual concatenation
Controls writing and reading of each chip Communicates with the NE Issues configured services Reports alarms of each functional module Checks R_LOS alarms of optical modules Controls the shutting of transmission
Clock Module
This module mainly generates working clocks for each chip. The frequencies of the clocks are 50 MHz, 77 MHz and 100 MHz.
ADQ1
STAT ACT PROG SRV
CLASS 1 LASER PRODUCT
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the ADQ1. Table 7-60 lists the type and usage of the optical interfaces.
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Table 7-60 Optical interfaces of the ADQ1 Interface OUT1/IN1 OUT2/IN2 OUT3/IN3 OUT4/IN4 Interface Type LC (pluggable) LC (pluggable) LC (pluggable) LC (pluggable) Usage Transmits and receives STM-1 optical signals. Transmits and receives STM-1 optical signals. Transmits and receives STM-1 optical signals. Transmits and receives STM-1 optical signals.
Port type Flow type Service type Peak cell rate (PCR) Sustainable cell rate (SCR)
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31
28
34
34
34
14
10
10
10
10
8.2
10
10
10
Mechanical Specifications
The mechanical specifications of the ADQ1 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.9
Power Consumption
In the normal temperature (25), the maximum power consumption of the ADQ1 is 37 W.
7.15 IDL4
This section describes the IDL4, a 1 x STM-4 ATM processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.15.1 Version Description The functional version of the IDL4 board is N1. 7.15.2 Function and Feature The IDL4 supports the ATM switching, IMA, and ATM protection. 7.15.3 Working Principle The IDL4 consists of the O/E converting module, physical layer module, ATM module and so on. 7.15.4 Front Panel On the front panel of the IDL4, there are indicators, interfaces, barcode and laser safety class label. 7.15.5 Valid Slots The IDL4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The IDL4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.15.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the IDL4 indicates the optical interface type. 7.15.7 Board Protection The IDL4 supports the 1+1 board-level protection. The active and standby IDL4 should be housed in paired slots. 7.15.8 Board Configuration Reference You can use the T2000 to set parameters for the IDL4. 7.15.9 Technical Specifications The technical specifications of the IDL4 cover the optical interface specifications, board dimensions, weight and power consumption.
Table 7-63 Functions and features of the IDL4 Function and Feature Basic function Optical interface type Connector type Optical module type E3 ATM interface IMA function (ATM Forum IMA 1.1 standard) IDL4 Accesses and processes 1 x STM-4 ATM services. Supports the optical interfaces of the S-4.1, L-4.1, L-4.2 and Ve-4.2 types. LC. SFP. Not supported. Accesses and processes IMA services when used with E1 service processing board N1PQ1/N1PQM. Supports a maximum of 63 IMA E1 services. One ATM port supports a maximum of 16 IMA groups. Each IMA group supports 132 E1 signals. One ATM port supports a maximum of E1 links of 16 non-IMA groups. The maximum IMA multichannel delay is 226 ms. Max. uplink bandwidth ATM switching capability Mapping granularity IMA feature Supports 8 x VC-4, or 63 x VC-12 and +7 x VC-4. 1.0 Gbit/s. Supports VC-12, VC-4, or VC4-Xc (X:14), VC12-Xv (X:132). Accesses and processes IMA services when used with E1 service processing board. Processes IMA services for a maximum of 63 x E1 signals. Supports a maximum of 16 IMA groups. Each IMA group supports 1 32 E1 signals. The maximum IMA multichannel delay is 226 ms. Service type ATM connection Statistical multiplexing Flow type and QoS ATM multicast connection ATM protection (ITU-T I.630) Supports CBR, rt-VBR, nrt-VBR and UBR. 2048. Supported. Supports IETF RFC2514 and ATM forum TM4.0. Supports spacial multicast and logical multicast. Supports unidirectional or bidirectional 1+1, 1:1, VP-Ring, VC-Ring protection schemes.
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Function and Feature Board level 1+1 protection OAM function (ITU-T I.610) Maintenance feature Alarm and performance event
IDL4 Supported. Supports AIS, RDI, LB , and CC. Supports inloop and outloop at the ATM layer levels and the optical interface (except the outloop at external port), which are used for maintenance and fault locating. Provides rich alarms and performance events, which are used for maintenance and fault locating.
Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can coexist with single E1. The IMA group can dynamically increase or decrease the bandwidth to enhance the bandwidth utilization. The IMA group can also converge 2M services, and can connect to other IMA equipment.
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622 Mbit/s
E/O
622 Mbit/s
Mapping module
high speed bus Cross-connet unit B
Clock module
+3.3 V
DC/DC converter
Fuse
Fuse
DC/DC converters
Mappings ATM cells into SDH frames Demappings SDH frames to ATM cells Processes ATM service physical layer functions: cell delimitation, test and generation of header error control (HEC) sequence
ATM Module
The ATM module mainly performs ATM layer functions in the ATM protocol. These functions include:
l l l
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IMA Module
This module mainly performs IMA protocol functions. These functions are:
l l l l
Separation and re-creation of ATM cells Frame synchronization Insertion and extraction of IMA control protocol (ICP) cells Management of IMA groups
Mapping Module
The mapping module:
l l l l
Mappings ATM cells into SDH frame payload Demappings SDH frame payload to ATM cells Supports ATM physical layer functions Supports VC4-Xv (X4) virtual concatenation
Controls writing and reading of each chip Communicates with the NE Issues configured services Reports alarms of each functional module Checks R_LOS alarms of optical modules Controls the shutting of transmission
Clock Module
This module mainly generates working clocks for each chip. The frequencies of the clocks are 50 MHz, 77 MHz and 100 MHz.
IDL4
STAT ACT PROG SRV
OUT1 IN1
IDL4
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are one optical interface on the front panel of the IDL4. Table 7-64 lists the type and usage of the optical interface.
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Table 7-64 Optical interface of the IDL4 Interface OUT1/IN1 Interface Type LC (pluggable) Usage Transmits and receives STM-4 optical signals.
Port type Flow type Service type Peak cell rate (PCR)
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Sustainable cell rate (SCR) Maximum cell burst size Cell delay variation tolerance (CDVT)
Mechanical Specifications
The mechanical specifications of the IDL4 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
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Power Consumption
In the normal temperature (25), the maximum power consumption of the IDL4 is 41 W.
7.16 IDQ1
This section describes the IDQ1, a 4 x STM-1 ATM processing board, in terms of the version, function, principle, front panel, configuration and specifications. 7.16.1 Version Description The functional version of the IDQ1 board is N1. 7.16.2 Function and Feature The IDQ1 supports the ATM switching, IMA, and ATM protection. 7.16.3 Working Principle and Signal Flow The ADQ1 consists of the O/E converting module, physical layer module, ATM module and so on. 7.16.4 Front Panel On the front panel of the IDQ1, there are indicators, interfaces, barcode and laser safety class label. 7.16.5 Valid Slots The IDQ1 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The IDQ1 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.16.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the IDQ1 indicates the optical interface type. 7.16.7 Board Protection The IDQ1 supports the 1+1 board-level protection. The active and standby IDQ1 should be housed in paired slots. 7.16.8 Board Configuration Reference You can use the T2000 to set parameters for the IDQ1. 7.16.9 Technical Specifications The technical specifications of the IDQ1 cover the optical interface specifications, board dimensions, weight and power consumption.
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Table 7-67 Functions and features of the IDQ1 Function and Feature Basic function Optical interface type Connector type Optical module type E3 ATM interface IMA function (ATM Forum IMA 1.1 standard) IDQ1 Accesses and processes 4 x STM-1 ATM services. Supports the optical interfaces of the Ie-1, S-1.1, L-1.1, L-1.2 and Ve-1.2 types. LC. SFP. Not supported. Accesses and processes IMA services when used with E1 service processing board N1PQ1/N1PQM. Supports a maximum of 63 IMA E1 services. One ATM port supports a maximum of 16 IMA groups. Each IMA group supports 132 E1 signals. One ATM port supports a maximum of E1 links of 16 non-IMA groups. The maximum IMA multichannel delay is 226 ms. Max. uplink bandwidth ATM switching capability Mapping granularity IMA feature Supports 8 x VC-4, or 63 x VC-12 and 7 x VC-4. 1.0 Gbit/s. Suppports VC-12, VC-4, or VC4-Xc (X:14), VC12-Xv (X:132). Accesses and processes IMA services when used with E1 service processing board. Processes IMA services for a maximum of 63 x E1 signals. Supports a maximum of 16 IMA groups. Each IMA group supports 1 32 E1 signals. The maximum IMA multichannel delay is 226 ms. Service type ATM connection Statistical multiplexing Flow type and QoS ATM multicast connection ATM protection (ITU-T I.630) Supports CBR, rt-VBR, nrt-VBR and UBR. 2048. Supported. Supports IETF RFC2514 and ATM forum TM4.0. Supports spacial multicast and logical multicast. Supports unidirectional or bidirectional 1+1, 1:1, VP-Ring, VC-Ring protection schemes.
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Function and Feature Board level 1+1 protection OAM function (ITU-T I.610) Maintenance feature Alarm and performance event
IDQ1 Supported. Supports AIS, RDI, LB , and CC. Supports inloop and outloop at the ATM layer levels and the optical interface (except the outloop at external port), which are used for maintenance and fault locating. Provides rich alarms and performance events, which are used for maintenance and fault locating.
Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can coexist with single E1. The IMA group can dynamically increase or decrease the bandwidth to enhance the bandwidth utilization. The IMA group can also converge 2M services, and can connect to other IMA equipment.
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4 x 155 Mbit/s
E/O
4 x 155 Mbit/s
4 x 155 Mbit/s
O/E
4 x 155 Mbit/s
PHY module
Mapping module
high speed bus Cross-connet unit B
Clock module
+3.3 V
DC/DC converter
Fuse
Fuse
DC/DC converters
Mappings ATM cells into SDH frames Demappings SDH frames to ATM cells Processes ATM service physical layer functions: cell delimitation, test and generation of header error control (HEC) sequence
ATM Module
The ATM module mainly performs ATM layer functions in the ATM protocol. These functions include:
l l l
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IMA Module
This module mainly performs IMA protocol functions. These functions are:
l l l l
Separation and re-creation of ATM cells Frame synchronization Insertion and extraction of IMA control protocol (ICP) cells Management of IMA groups
Mapping Module
The mapping module:
l l l l
Mappings ATM cells into SDH frame payload Demappings SDH frame payload to ATM cells Supports ATM physical layer functions Supports VC4-Xv (X4) virtual concatenation
Controls writing and reading of each chip Communicates with the NE Issues configured services Reports alarms of each functional module Checks R_LOS alarms of optical modules Controls the shutting of transmission
Clock Module
This module mainly generates working clocks for each chip. The frequencies of the clocks are 50 MHz, 77 MHz and 100 MHz.
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four optical interfaces on the front panel of the IDQ1. Table 7-68 lists the type and usage of the optical interfaces.
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Table 7-68 Optical interfaces of the IDQ1 Interface OUT1/IN1 OUT2/IN2 OUT3/IN3 OUT4/IN4 Interface Type LC (pluggable) LC (pluggable) LC (pluggable) LC (pluggable) Usage Transmits and receives STM-1 optical signals. Transmits and receives STM-1 optical signals. Transmits and receives STM-1 optical signals. Transmits and receives STM-1 optical signals.
Port type
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Flow type Service type Peak cell rate (PCR) Sustainable cell rate (SCR) Maximum cell burst size Cell delay variation tolerance (CDVT)
14 10
8 8.2
10 10
10 10
10 10
Mechanical Specifications
The mechanical specifications of the IDQ1 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the IDQ1 is 41 W.
7.17 MST4
This section describes the MST4, a 4-channel multi-service transparent transmission board, in terms of the version, function, principle, front panel, configuration and specifications. 7.17.1 Version Description The functional version of the MST4 board is N1. 7.17.2 Function and Feature The MST4 is used to access multiple services, and to maintain alarms. 7.17.3 Working Principle and Signal Flow The MST4 consists of the client-side access module, FC protocol processing module, encapsulation and mapping module, Communication and control module and so on. 7.17.4 Front Panel On the front panel of the MST4, there are indicators, interfaces and barcode. 7.17.5 Valid Slots The MST4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack. The MST4 can be housed in any of slots 1113 in the OptiX OSN 1500B subrack. 7.17.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the MST4 indicates the service type, optical interface type and transmission distance. 7.17.7 Board Configuration Reference You can use the T2000 to set parameters for the MST4. 7.17.8 Technical Specifications The specifications of the MST4 cover the optical interface specifications, mechanical specifications and power consumption.
Table 7-71 Functions and features of the MST4 Function and Feature Basic function Connector type Optical module type Service type MST4 Provides four independent ports to access multiple services, and supports the transparent transmission of the SAN and Video services. LC. SFP. Supports the FC100/FICON, FC200, ESCON, and DVB-ASI services.Table 7-72 lists types and rates of the services. Accesses four-channel FC services (FC100/FICON and FC200) at the same time, and the total bandwidth is less than 2.5 Gbit/s. Supports the full-rate transmission of the FC services (one-channel FC200 services or two-channel FC100 services). Accesses four-channel ESCON or DVB-ASI services, and the total bandwidth is less than 2.5 Gbit/s. Distance extension Max. uplink bandwidth Mapping granularity ESCON DVB-ASI Encapsulation format Maintenance feature Alarm and performance event The first and second ports support the distance extension function at the SDH side. (FC100: 3000 km; FC200: 1500 km) 2.5 Gbit/s (Four 622 Mbit/s buses are present on the backplane to directly connect to the cross-connect unit.) Supports VC4-Xc (X: 4, 8, 16). Accesses four-channel ESCON services, and the total bandwidth is less than 2.5 Gbit/s. Accesses four-channel DVB-ASI services, and the total bandwidth is less than 2.5 Gbit/s. Supports GFP-T, compliant with ITU-T G.7041. Supports the inloop at the port level of the client side. The loopack is used for maintenance and fault locating. Provides rich alarms and performance events, which are used for maintenance and fault locating.
Table 7-72 Services and service rates provided by the MST4 Service Type FC100/FICON FC200 Rate 1062.5 Mbit/s 2125 Mbit/s Remarks SAN service SAN service
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FC1_ RCV
FC2
FC1_ SND
FC1_ SND
FC2
FC1_ RCV
Decaps ulation
100 MHz 125 MHz 135 MHz 212.5 MHz 622 MHz
Clock module
+3.3 V +1.2 V +1.5 V +1.8 V +2.5 V
Fuse
Fuse
8B/10B conversion Synchronous processing Extraction of primitive signal and primitive sequence
Check and statistics of all special frames Modification of values of some special frames (FLOG1, PLOG1 and ELP) CRC check
According to signal flow direction, the function modules inside the chip can be classified into modules in ingress direction and ones in egress direction. The ingress direction is for processing from client side to line side. The egress direction is for line-side processing. Ingress direction: Through GFP encapsulation, 64B/65B conversion is performed to data bytes after decoding. The data bytes are then mapped under GFP protocol. Egress direction: SDH data frames are received from the line-side interface module. After the overhead is processed, GFP data frames are extracted from SDH concatenated channels and then are transmitted to the decapsulating module for decapsulation.
Writes and reads register Provides interface for CPU Checks and selects clock Performs phase discrimination and frequency division to the clock Checks the in-service state of the cross-connect, the SCC and the line boards Checks reset control circuits of each chip
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Controls the shutting down of the optical module Processes communications Controls indicators
MST4
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Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the MST4. Table 7-73 lists the type and usage of the optical interfaces. Table 7-73 Optical interfaces of the MST4 Interface IN1-IN4 OUT1-OUT4 Interface Type LC LC Usage Receives multi-service optical signals. Transmits multi-service optical signals.
Feature Code 10 11 12 13 14 15
Service Type (Optical Interface Type) 2 x FC (SM) 2 x FC (SM) 2 x FC (MM) 4 x ESCON/DVB-ASI (SM) 4 x ESCON/DVB-ASI (MM) 1 x FC2 (MM)
Board Barcode
Feature Code
Transmission Distance
SSN1MST416
16
SSN1MST417
17
2 km 2 km -
SSN1MST418
18
J1 byte C2 byte
34060288
34060278
Item Optical source type Wavelength (nm) Transmission distance (km) Max. launched optical power (dBm) Min. launched optical power (dBm) Receiver sensitivity (dBm) Overload optical power (dBm)
Specification SLM 1310 15 8 2 14 LED LED 850 0.5 -2.5 MLM 1310 2 -3 15 0 SLM
15
19
-9.5
-10
-5
31
30
17
21
14
Mechanical Specifications
The mechanical specifications of the MST4 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.9
Power Consumption
In the normal temperature (25), the maximum power consumption of the MST4 is 26 W.
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This section describes the EU08, an 8 x STM-1 electrical interface board, in terms of the version, function, working principle, front panel and specifications. 8.10 OU08 This section describes the OU08, an 8 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and parameters. 8.11 MU04 This section describes the MU04, a 4 x E4/STM-1 electrical interface board, in terms of the version, function, principle, front panel and specifications. 8.12 TSB4 This section describes the TSB4, a 4-channel interface switching board. 8.13 TSB8 This section describes the TSB8, an 8-channel optical interface switching board, in terms of the version, function, principle, front panel and specifications. 8.14 EFF8 This section describes the EFF8, an 8 x 100M Ethernet optical interface board, in terms of the version, function, principle, front panel and specifications. 8.15 ETF8 This section describes the ETF8, an 8 x 100M Ethernet twisted pair interface board, in terms of the version, function, principle, front panel and specifications. 8.16 ETS8 This section describes the ETS8, an 8 x 10/100M Ethernet twisted pair interface switching board, in terms of the version, function, principle, front panel and specifications. 8.17 DM12 This section describes the DM12, a DDN interface board, in terms of the version, function, principle, front panel and specifications.
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8.1 L12S
This section describes the L12S, a 16 x E1/T1 electrical interface switching board, in terms of the version, function, principle, front panel and specifications. 8.1.1 Version Description The functional version of the L12S is R1. 8.1.2 Function and Feature The L12S is used to receive and transmit 16 x E1/T1 electrical signals, and the L12S must be used with the PD1. 8.1.3 Working Principle and Signal Flow The L12S consists of the interface module, switch matrix module, and power supply module. 8.1.4 Front Panel On the front panel of the L12S, there are interfaces and barcode. 8.1.5 Valid Slots As the interface board for the PD1, the L12S can be housed in any of slots 6 and 7 in the OptiX OSN 1500A subrack. 8.1.6 Technical Specifications The technical specifications of the L12S cover the board dimensions, weight and power consumption.
Interface module
E1/T1
PD1
PD1
+3.3 V
Fuse
+3.3 V
Power
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Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
L12S
1-16
Interfaces
On the front panel of the L12S, there are two 2mmHM connectors, which are used to access 16 x E1/T1 electrical signals.
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Mechanical Specifications
The mechanical specifications of the L12S are as follows:
l l
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.27
Power Consumption
In the normal temperature (25), the maximum power consumption of the L12S is 4.5 W.
8.2 D12B
This section describes the D12B, a 32 x E1/T1 electrical interface board, in terms of the version, function, principle, front panel and specifications. 8.2.1 Version Description The functional version of the D12B board is N1. 8.2.2 Function and Feature The D12B is used to receive and transmit 32 x E1/T1 electrical signals, and the D12B must be used with the PQ1 or PQM. 8.2.3 Working Principle and Signal Flow The D12B consists of the interface module and power supply module. 8.2.4 Front Panel On the front panel of the D12B, there are interfaces and barcode. 8.2.5 Valid Slots
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The D12B can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. The D12B can be used as the interface board for the PQ1 or PQM. 8.2.6 Technical Specifications The technical specifications of the D12B cover the board dimensions, weight and power consumption.
E1/T1
PQ1/PQM
Interface module
E1/T1 PQ1/PQM
+3.3 V
Fuse
+3.3 V Power
Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
1 8 9 16 17 24 25 32
D12B
Interfaces
There are four DB44 interfaces on the front panel of the D12B. Table 8-2 lists the type and usage of the interfaces. Table 8-2 Interfaces on the front panel of the D12B Interface 18 916 1724 2532 Interface Type DB44 DB44 DB44 DB44 Usage Receive eight channels (18) of E1/T1 signals. Receive eight channels (916) of E1/T1 signals. Receive eight channels (1724) of E1/T1 signals. Receive eight channels (25-32) of E1/T1 signals.
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Table 8-3 Pins of the DB44 interfaces of the D12B Front View
1
Pin 38 23 37 22 36 21
Usage R1 to receive the first channel of signals. R2 to receive the second channel of signals. R3 to receive the third channel of signals. R4 to receive the fourth channel of signals. T1 to transmit the first channel of signals. T2 to transmit the second channel of signals. T3 to transmit the third channel of signals. T4 to transmit the fourth channel of signals.
Pin 34 19 33 18 32 17 31 16 11 26 10 25 9 24 8 7
Usage R5 to receive the fifth channel of signals. R6 to receive the sixth channel of signals. R7 to receive the seventh channel of signals. R8 to receive the eighth channel of signals. T5 to transmit the fifth channel of signals. T6 to transmit the sixth channel of signals. T7 to transmit the seventh channel of signals. T8 to transmit the eighth channel of signals.
44
35 20 15 30 14 29 13 28 12 27
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Mechanical Specifications
The mechanical specifications of the D12B are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.3
Power Consumption
In the normal temperature (25), the maximum power consumption of the D12B is 0 W.
8.3 D12S
This section describes the D12S, a 32 x E1/T1 electrical interface switching board, in terms of the version, function, principle, front panel and specifications. 8.3.1 Version Description The functional version of the D12S board is N1. 8.3.2 Function and Feature The D12S is used to receive and transmit 32 x E1/T1 electrical signals, and the D12S must be used with the PQ1 or PQM. 8.3.3 Working Principle and Signal Flow The D12S consists of the interface module, switch matrix module, and power supply module. 8.3.4 Front Panel On the front panel of the D12S, there are interfaces and barcode. 8.3.5 Valid Slots The D12S can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. The D12S can be used as the interface board for the PQ1 or PQM. 8.3.6 Technical Specifications The technical specifications of the D12S cover the board dimensions, weight and power consumption.
Figure 8-5 shows the block diagram for the functions of the D12S. Figure 8-5 Block diagram for the functions of the D12S
Backplane Crossconnect board
E1/T1
Interface module
E1/T1
PQ1/ PQM
PQ1/ PQM
+3.3 V
Fuse
+3.3 V
Power
Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
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18 9 16 1724 25 32
D12S
Interfaces
There are four DB44 interfaces on the front panel of the D12S. Table 8-5 lists the type and usage of the optical interfaces. Table 8-5 Interfaces on the front panel of the D12S Interface 18 916 1724 2532 Interface Type DB44 DB44 DB44 DB44 Usage Receive eight channels (18) of E1/T1 signals. Receive eight channels (916) of E1/T1 signals. Receive eight channels (1724) of E1/T1 signals. Receive eight channels (2532) of E1/T1 signals.
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Table 8-6 Pins of the DB44 interfaces of the D12S Front View
1
Pin 38 23 37 22 36 21
Usage R1 to receive the first channel of signals. R2 to receive the second channel of signals. R3 to receive the third channel of signals. R4 to receive the fourth channel of signals. T1 to transmit the first channel of signals. T2 to transmit the second channel of signals. T3 to transmit the third channel of signals. T4 to transmit the fourth channel of signals.
Pin 34 19 33 18 32 17 31 16 11 26 10 25 9 24 8 7
Usage R5 to receive the fifth channel of signals. R6 to receive the sixth channel of signals. R7 to receive the seventh channel of signals. R8 to receive the eighth channel of signals. T5 to transmit the fifth channel of signals. T6 to transmit the sixth channel of signals. T7 to transmit the seventh channel of signals. T8 to transmit the eighth channel of signals.
44
35 20 15 30 14 29 13 28 12 27
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Mechanical Specifications
The mechanical specifications of the D12S are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the D12S in the switching state is 9 W and that of the D12S in the normal state is 0 W.
8.4 L75S
This section describes the L75S, a 16 x E1 electrical interface switching board, in terms of the version, function, principle, front panel and specifications. 8.4.1 Version Description The functional version of the L75S is R1. 8.4.2 Function and Feature The L75S is used to receive and transmit 16 x E1 electrical signals, and the L75S must be used with the PD1. 8.4.3 Working Principle and Signal Flow The L75S consists of the interface module, switch matrix module, and power supply module. 8.4.4 Front Panel On the front panel of the L75S, there are interfaces and barcode. 8.4.5 Valid Slots The L75S can be housed in any slots of 67 in the subrack. The L75S can be used as the interface board for the PD1. 8.4.6 Technical Specifications The technical specifications of the L75S cover the board dimensions, weight and power consumption.
Interface module
E1
PD1
PD1
+3.3 V
Fuse
+3.3 V
Power
Interface Module
The interface module receives and transmits the E1 electrical signals.
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L75S
1-16
Interfaces
On the front panel of the L75S, there are two 2mmHM connectors, which are used to access 16 x E1 electrical signals.
Mechanical Specifications
The mechanical specifications of the L75S are as follows:
l l
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.24
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Power Consumption
In the normal temperature (25), the maximum power consumption of the L75S is 2.7 W.
8.5 D75S
This section describes the D75S, a 32 x E1/T1 electrical interface switching board, in terms of the version, function, principle, front panel and specifications. 8.5.1 Version Description The functional version of the D75S board is N1. 8.5.2 Function and Feature The D75S is used to receive and transmit 32 x E1/T1 electrical signals, and the D75S must be used with the PQ1. 8.5.3 Working Principle and Signal Flow The D75S consists of the interface module, switch matrix module, and power supply module. 8.5.4 Front Panel On the front panel of the D75S, there are interfaces and barcode. 8.5.5 Valid Slots As the interface board for the PQ1, the D75S can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. 8.5.6 Technical Specifications The technical specifications of the D75S cover the board dimensions, weight and power consumption.
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Interface module
E1/T1
PQ1/ PQM
PQ1/ PQM
+3.3 V
Fuse
+3.3 V
Power
Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
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18 9 16 1724 25 32
D75S
Interfaces
There are four DB44 interfaces on the front panel of the D75S. Table 8-9 lists the type and usage of the DB44 interfaces. Table 8-9 Interfaces on the front panel of the D75S Interface 18 916 1724 2532 Interface Type DB44 DB44 DB44 DB44 Usage Receive eight channels (18) of E1/T1 signals. Receive eight channels (916) of E1/T1 signals. Receive eight channels (1724) of E1/T1 signals. Receive eight channels (2532) of E1/T1 signals.
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Table 8-10 Pins of the DB44 interfaces of the D75S Front View
1
Pin 38 23 37 22 36 21
Usage R1 to receive the first channel of signals. R2 to receive the second channel of signals. R3 to receive the third channel of signals. R4 to receive the fourth channel of signals. T1 to transmit the first channel of signals. T2 to transmit the second channel of signals. T3 to transmit the third channel of signals. T4 to transmit the fourth channel of signals.
Pin 34 19 33 18 32 17 31 16 11 26 10 25 9 24 8 7
Usage R5 to receive the fifth channel of signals. R6 to receive the sixth channel of signals. R7 to receive the seventh channel of signals. R8 to receive the eighth channel of signals. T5 to transmit the fifth channel of signals. T6 to transmit the sixth channel of signals. T7 to transmit the seventh channel of signals. T8 to transmit the eighth channel of signals.
44
35 20 15 30 14 29 13 28 12 27
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Mechanical Specifications
The mechanical specifications of the D75S are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the D75S in the switching state is 6 W and that of the D75S in the normal state is 0 W.
8.6 D34S
This section describes the D34S, a 6 x E3/T3 electrical interface switching board, in terms of the version, function, principle, front panel and specifications. 8.6.1 Version Description The functional version of the D34S board is N1. 8.6.2 Function and Feature The D34S is used to receive and transmit 6 x E3/T3 electrical signals, and the D34S must be used with the PD3 and PQ3. 8.6.3 Working Principle and Signal Flow The D34S consists of the interface module, switch matrix module, and power supply module. 8.6.4 Front Panel On the front panel of the D34S, there are interfaces and barcode. 8.6.5 Valid Slots the D34S can be housed in any of slots 14-17 in the OptiX OSN 1500B subrack. 8.6.6 Technical Specifications The technical specifications of the D34S cover the electrical interface specifications, board dimensions, weight and power consumption.
Figure 8-11 shows the block diagram for the functions of the D34S. Figure 8-11 Block diagram for the functions of the D34S
Backplane Crossconnect board E3/T3 Interface module E3/T3 Swictch matrix module PD3 TSB8 TSB8 PD3
+3.3 V
Fuse
+3.3 V Power
Interface Module
The interface module receives and transmits the E3/T3 electrical signals.
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OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6
D34S
Interfaces
There are six pairs of electrical interfaces on the front panel of the D34S. Table 8-12 lists the type and usage of interfaces on the D34S. Table 8-12 Interfaces of the D34S Interface IN1IN6 OUT1OUT6 Interface Type SMB SMB Usage Receive six channels (16) of E3/T3 electrical signals. Transmit six channels (16) of E3/T3 electrical signals.
Mechanical Specifications
The mechanical specifications of the D34S are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the D34S in the switching state is 2 W and that of the D34S in the normal state is 0 W.
8.7 C34S
This section describes the C34S, a 3 x E3/T3 electrical interface switching board, in terms of the version, function, principle, front panel and specifications. 8.7.1 Version Description The functional version of the C34S board is N1. 8.7.2 Function and Feature The C34S is used to receive and transmit 3 x E3/T3 electrical signals, and the C34S must be used with the PL3. 8.7.3 Working Principle and Signal Flow The C34S consists of the interface module, switch matrix module, and power supply module. 8.7.4 Front Panel On the front panel of the C34S, there are interfaces and barcode. 8.7.5 Valid Slots As the interface board for the PL3, the C34S can be housed in any of slots 14 and 16 in the OptiX OSN 1500B subrack.
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8.7.6 Technical Specifications The technical specifications of the C34S cover the electrical interface specifications, board dimensions, weight and power consumption.
Interface module
E3/T3
+3.3 V
Fuse
Fuse
Interface Module
The interface module receives and transmits the E3/T3 electrical signals.
C34S
Interfaces
There are three pairs of electrical interfaces on the front panel of the C34S. Table 8-14 lists the type and usage of interfaces on the C34S. Table 8-14 Interfaces of the C34S Interface IN1IN3 OUT1OUT3 Interface Type SMB SMB Usage Receive the first three channels (13) of E3/T3 electrical signals. Transmit the first three channels (13) of E3/T3 electrical signals.
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Mechanical Specifications
The mechanical specifications of the C34S are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.3
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Power Consumption
In the normal temperature (25), the maximum power consumption of the C34S in the switching state is 2 W and that of the C34S in the normal state is 0 W.
8.8 EU04
This section describes the EU04, a 4 x STM-1 electrical interface board, in terms of the version, function, working principle, front panel and specifications. 8.8.1 Version Description The functional version of the EU04 board is N1. 8.8.2 Function and Feature The EU04 is used to receive and transmit 4 x STM-1 electrical signals, and the EU04 must be used with the SEP. 8.8.3 Working Principle and Signal Flow The EU04 consists of the interface module, switch matrix module, and power supply module. 8.8.4 Front Panel On the front panel of the EU04, there are interfaces and barcode. 8.8.5 Valid Slots As the interface board for the SEP, the EU04 can be housed in any of slots 14 and 16 in the OptiX OSN 1500B subrack. 8.8.6 Technical Specifications The technical specifications of the EU04 cover the electrical interface specifications, board dimensions, weight and power consumption.
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STM-1(e)
Interface module
STM-1(e)
+3.3 V
Fuse
Fuse
Interface Module
The interface module receives and transmits the STM-1 electrical signals.
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Interfaces
There are four pairs of electrical interfaces on the front panel of the EU04. Table 8-17 lists the type and usage of interfaces on the EU04. Table 8-17 Interfaces of the EU04 Interface IN1IN4 OUT1OUT4 Interface Type SMB SMB Usage Receive four (14) channels of electrical interfaces. Transmit four (14) channels of electrical interfaces.
Table 8-18 Valid slots for the SEP and corresponding slots for the EU04 Valid Slot for the SEP Slot 12 Slot 13 Corresponding Slot for the EU04 Slot 14 Slot 16
Mechanical Specifications
The mechanical specifications of the EU04 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the EU04 is 6 W.
8.9 EU08
This section describes the EU08, an 8 x STM-1 electrical interface board, in terms of the version, function, working principle, front panel and specifications. 8.9.1 Version Description The functional version of the EU08 board is N1.
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8.9.2 Function and Feature The EU08 is used to receive and transmit 8 x STM-1 electrical signals, and the EU08 must be used with the SEP. 8.9.3 Working Principle and Signal Flow The EU08 consists of the interface module, switch matrix module, and power supply module. 8.9.4 Front Panel On the front panel of the EU08, there are interfaces and barcode. 8.9.5 Valid Slots As the interface board for the SEP, the EU08 can be housed in any of slots 14 and 16 in the OptiX OSN 1500B subrack. 8.9.6 Technical Specifications The technical specifications of the EU08 cover the electrical interface specifications, board dimensions, weight and power consumption.
STM-1(e)
Interface module
STM-1(e)
+3.3 V
Fuse
Interface Module
The interface module receives and transmits the STM-1 electrical signals.
from the cross-connect board. When the TPS protection is not performed, the switch matrix module transmits the signals to the SEP board. When the TPS protection is performed, the switch matrix module transmits the signals to the TSB8 board for bridging. In the transmit direction, the working direction of the switch matrix module is the reverse of the receive direction.
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8
EU08
Interfaces
There are eight pairs of electrical interfaces on the front panel of the EU08.
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Table 8-20 lists the type and usage of interfaces on the EU08. Table 8-20 Interfaces of the EU08 Interface IN1IN8 OUT1OUT8 Interface Type SMB SMB Usage Receive eight (18) channels of electrical interfaces. Transmit eight (18) channels of electrical interfaces.
The OptiX OSN 1500A does not support the EU08 board.
Table 8-21 Valid slots for the SEP and corresponding slots for the EU08 Valid Slot for the SEP Slot 12 Slot 13 Corresponding Slot for the EU08 Slot 14 Slot 16
Specification
Mechanical Specifications
The mechanical specifications of the EU08 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the EU08 is 11 W.
8.10 OU08
This section describes the OU08, an 8 x STM-1 optical interface board, in terms of the version, function, working principle, front panel and parameters. 8.10.1 Version Description The OU08 has two versions, N1 and N2. The main difference between the two versions lies in the connector type for optical interfaces and the pluggability of the optical modules. 8.10.2 Function and Feature The OU08 is used to receive and transmit 8 x STM-1 optical signals, and the OU08 must be used with the SEP. 8.10.3 Working Principle and Signal Flow The OU08 consists of the interface module and power supply module. 8.10.4 Front Panel On the front panel of the OU08, there are interfaces and barcode. 8.10.5 Valid Slots As the interface board for the SEP, the OU08 can be housed in any of slots 14 and 16 in the OptiX OSN 1500B subrack. 8.10.6 Technical Specifications The technical specifications of the OU08 cover the optical interface specifications, board dimensions, weight and power consumption.
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Table 8-23 Version description of the OU08 Item Functional version Commonness Difference Specification The OU08 has two versions, N1 and N2. The N1 and N2 versions share the same working principle. The optical interface of the N1OU08 uses the LC connector. The optical interface of the N2OU08 uses the SC connector. The N1OU08 uses the pluggable optical module. The N2OU08 does not use the pluggable optical module. None.
Replaceability
STM-1(o)
Interface module
SEP
STM-1(o)
SEP
+3.3 V
Fuse
+3.3 V Power
Interface Module
In the receive direction, the interface module performs O/E convertion for the STM-1 signals, and transmits the signals to the SEP board. In the transmit direction, the interface module performs the E/O convertion for the STM-1 signals, and transmits the signals to the optical interface.
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OU08
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 OUT8 IN7 IN8
OU08
Interfaces
There are eight pairs of optical interfaces on each front panel of the N1OU08 and N2OU08. Table 8-24 lists the interface type and usage for the N1OU08. Table 8-25 lists the interface type and usage for the N2OU08. Table 8-24 Interfaces of the N1OU08 Interface IN1IN8 OUT1OUT8 Interface Type LC LC Usage Receive eight (18) channels of STM-1 optical signals. Transmit eight (18) channels of STM-1 optical signals.
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Table 8-25 Interfaces of the N2OU08 Interface IN1IN8 OUT1OUT8 Interface Type SC SC Usage Receive eight (18) channels of STM-1 optical signals. Transmit eight (18) channels of STM-1 optical signals.
Specification 155520 kbit/s NRZ S-1.1 N1OU08 (12601360) N2OU08 (12611360) MLM 15 to 8
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Mechanical Specifications
The mechanical specifications of the OU08 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the OU08 is 6 W.
8.11 MU04
This section describes the MU04, a 4 x E4/STM-1 electrical interface board, in terms of the version, function, principle, front panel and specifications. 8.11.1 Version Description The functional version of the MU04 board is N1. 8.11.2 Function and Feature The MU04 is used to receive and transmit 4 x E4/STM-1 electrical signals, and the MU04 must be used with the SPQ4. 8.11.3 Working Principle and Signal Flow The MU04 consists of the interface module, switch matrix module, and power supply module. 8.11.4 Front Panel On the front panel of the MU04, there are interfaces and barcode. 8.11.5 Valid Slots As the interface board for the SPQ4, the MU04 can be housed in any of slots 14 and 16 in the OptiX OSN 1500B subrack. 8.11.6 Technical Specifications The technical specifications of the MU04 cover the optical interface specifications, board dimensions, weight and power consumption.
E4/STM-1(e)
Interface module
E4/STM-1(e)
+3.3 V
Fuse
Interface Module
The interface module receives and transmits the E4/STM-1 electrical signals.
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MU04
Interfaces
There are four pairs of electrical interfaces on the front panel of the MU04. Table 8-28 lists the type and usage of interfaces on the MU04. Table 8-28 Interfaces of the MU04 Interface IN1IN4 OUT1OUT4 Interface Type SMB SMB Usage Receive four (14) channels of E4/STM-1 electrical interfaces. Transmit four (14) channels of E4/STM-1 electrical interfaces.
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Table 8-29 Valid slots for the SPQ4 and corresponding slots for the MU04 Valid Slot for the SPQ4 Slot 12 Slot 13 Corresponding Slot for the MU04 Slot 14 Slot 16
Mechanical Specifications
The mechanical specifications of the MU04 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the MU04 is 2 W.
8.12 TSB4
This section describes the TSB4, a 4-channel interface switching board. 8.12.1 Version Description The functional version of the TSB4 board is N1. 8.12.2 Function and Feature
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The TSB4, an four-channel electrical interface switching board, is used to provide the TPS protection. 8.12.3 Working Principle and Signal Flow The TSB4 consists of the switch matrix module and power supply module. 8.12.4 Front Panel On the front panel of the TSB4, there is the barcode. 8.12.5 Valid Slots When used with different processing boards and interface boards to realize the TPS protection, the TSB4 can be housed in different slots.The OptiX OSN 1500A does not support the TSB4. 8.12.6 Technical Specifications The technical specifications of the TSB4 cover the board dimensions, weight and power consumption.
When used with the MU04, the TSB8 provides the TPS protection for the SPQ4. When used with the C34S, the TSB8 provides the TPS protection for the PL3. When used with the EU04, the TSB8 provides the TPS protection for the SEP.
+3.3 V
Fuse
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TSB4
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Table 8-32 lists the valid slots for the TSB4 and corresponding slots for the SEP and EU04. Table 8-32 Valid slots for the TSB4 and corresponding slots for the SEP and EU04 Valid Slot for the TSB4 Slot 14 Valid Slot for the SEP Slot 13 Corresponding Slot for the EU04 Slot 16
NOTE
On the T2000, the SEP is displayed as the SEP or SEP1. When interfaces are available on the front panel of the SEP, the SEP is displayed as the SEP1 on the T2000. When the SEP is used with the interface board to realize the TPS protection, the SEP is displayed as the SEP on the T2000.
Table 8-33 lists the valid slots for the TSB4 and corresponding slots for the EFS0 and ETS8. Table 8-33 Valid slots for the TSB4 and corresponding slots for the EFS0 and ETS8 Valid Slot for the TSB4 Slot 14 Valid Slot for the EFS0 Slot 13 Corresponding Slot for the ETS8 Slot 16
Mechanical Specifications
The mechanical specifications of the TSB4 are as follows:
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Power Consumption
In the normal temperature (25), the maximum power consumption of the TSB4 is 2.5 W.
8.13 TSB8
This section describes the TSB8, an 8-channel optical interface switching board, in terms of the version, function, principle, front panel and specifications. 8.13.1 Version Description The functional version of the TSB8 board is N1. 8.13.2 Function and Feature The TSB8, an eight-channel electrical interface switching board, is used to provide the TPS protection. 8.13.3 Working Principle and Signal Flow The TSB8 consists of the switch matrix module and power supply module. 8.13.4 Front Panel On the front panel of the TSB8, there is the barcode. 8.13.5 Valid Slots When used with different processing boards and interface boards to realize the TPS protection, the TSB8 can be housed in different slots.The OptiX OSN 1500A does not support the TSB8. 8.13.6 Technical Specifications The technical specifications of the TSB8 cover the board dimensions, weight and power consumption.
When used with the MU04, the TSB8 provides the TPS protection for the SPQ4. When used with the C34S, the TSB8 provides the TPS protection for the PL3. When used with the D34S, the TSB8 provides the TPS protection for the PD3. When used with the D34S, the TSB8 provides the TPS protection for the PQ3. When used with the EU04, the TSB8 provides the TPS protection for the SEP1. When used with the EU08, the TSB8 provides the TPS protection for the SLH1/SEP1. When used with the ETS8, the TSB8 provides the TPS protection for the EFS0.
Figure 8-26 shows the block diagram for the functions of the TSB8 when it processes onechannel signals. Figure 8-26 Block diagram for the functions of the TSB8
Backplane Backplane Crossconnect board Standby processing board Swictch matrix module +3.3 V
Power module
Fuse
+3.3 V Power
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TSB8
Table 8-35 lists the valid slots for the TSB8 and corresponding slots for the PD3 and D34S.
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Table 8-35 Valid slots for the TSB8 and corresponding slots for the PD3 and D34S Valid Slot for the TSB8 Slot 14 Valid Slot for the PD3 Slot 13 Corresponding Slot for the D34S Slot 16
Table 8-36 lists the valid slots for the TSB8 and corresponding slots for the SEP and EU04. Table 8-36 Valid slots for the TSB8 and corresponding slots for the SEP and EU04 Valid Slot for the TSB8 Slot 14 Valid Slot for the SEP Slot 13 Corresponding Slot for the EU04 Slot 16
Table 8-37 lists the valid slots for the TSB8 and corresponding slots for the SEP and EU08. Table 8-37 Valid slots for the TSB8 and corresponding slots for the SEP and EU08 Valid Slot for the TSB8 Slot 14 Valid Slot for the SEP Slot 13 Corresponding Slot for the EU08 Slot 16
NOTE
On the T2000, the SEP is displayed as the SEP or SEP1. When interfaces are available on the front panel of the SEP, the SEP is displayed as the SEP1 on the T2000. When the SEP is used with the interface board to realize the TPS protection, the SEP is displayed as the SEP on the T2000.
Table 8-38 lists the valid slots for the TSB8 and corresponding slots for the EFS0 and ETS8. Table 8-38 Valid slots for the TSB8 and corresponding slots for the EFS0 and ETS8 Valid Slot for the TSB8 Slot 14 Valid Slot for the EFS0 Slot 13 Corresponding Slot for the ETS8 Slot 16
Table 8-39 lists the valid slots for the TSB8 and corresponding slots for the PL3 and C34S.
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Table 8-39 Valid slots for the TSB8 and corresponding slots for the PL3 and C34S Valid Slot for the TSB8 Slot 14 Valid Slot for the PL3 Slot 13 Corresponding Slot for the C34S Slot 16
Table 8-40 lists the valid slots for the TSB8 and corresponding slots for the PQ3 and D34S. Table 8-40 Valid slots for the TSB8 and corresponding slots for the PQ3 and D34S Valid Slot for the TSB8 Slot 14 and 15 Valid Slot for the PQ3 Slot 12 and 13 Corresponding Slot for the D34S Slot 16 and 17
Mechanical Specifications
The mechanical specifications of the TSB8 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.3
Power Consumption
In the normal temperature (25), the maximum power consumption of the TSB8 in the switching state is 5 W and that of the TSB8 in the normal state is 0 W.
8.14 EFF8
This section describes the EFF8, an 8 x 100M Ethernet optical interface board, in terms of the version, function, principle, front panel and specifications. 8.14.1 Version Description The functional version of the EFF8 board is N1. 8.14.2 Function and Feature The EFF8 is used to receive and transmit 8 x 100M Ethernet optical signals, and the EFF8 must be used with the Ethernet processing board. 8.14.3 Working Principle and Signal Flow The EFF8 consists of the interface module, switch matrix module, and power supply module. 8.14.4 Front Panel
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On the front panel of the EFF8, there are indicators, interfaces, barcode and laser safety class label. 8.14.5 Valid Slots When used with different Ethernet processing boards, the EFF8 can be housed in different slots. 8.14.6 Technical Specifications The technical specifications of the EFF8 cover the optical interface specifications, board dimensions, weight and power consumption.
100M
EFT8/ EFS0/EMS4/EMR0
Interface module
100M EFT8/EFS0/EMS4/EMR0
+3.3 V
Power module
Fuse
Interface Module
In the receive direction, the interface module performs the O/E convertion for the Ethernet signals, and transmits the signals to the EFT8, EFS0, EMS4, or EMR0 board. In the transmit direction, the interface module performs the E/O convertion for the Ethernet signals, and transmits the signals to the optical interface.
EFF8
1 2 3 4 5 6 7 8
LINKACT
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8
CLASS 1 LASER PRODUCT
EFF8
Indicators
For indication of indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight pairs of optical interfaces on the front panel of the EFF8. Table 8-41 lists the type and usage of interfaces on the EFF8.
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Table 8-41 Interfaces of the EFF8 Interface IN1IN8 OUT1 OUT8 Interface Type LC LC Usage Receives eight (18) channels of Ethernet optical signals. Transmits eight (18) channels of Ethernet optical signals.
As the interface board for the EFT8, the EFF8 can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. As the interface board for the EFS0, the EFF8 can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. As the interface board for the EMS4, the EFF8 can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. As the interface board for the EMR0, the EFF8 can be housed in any of slots 1417 in the OptiX OSN 1500B subrack.
Table 8-42 lists the valid slots for the EFT8 and corresponding slots for the EFF8. Table 8-42 Valid slots for the EFT8 and corresponding slots for the EFF8 Valid Slot for the EFT8 Slot 12 Slot 13 Corresponding Slot for the EFF8 Slots 14 and 15 Slots 16 and 17
Table 8-43 lists the valid slots for the EFS0 and corresponding slots for the EFF8. Table 8-43 Valid slots for the EFS0 and corresponding slots for the EFF8 Valid Slot for the EFS0 Slot 12 Slot 13 Corresponding Slot for the EFF8 Slots 14 and 15 Slots 16 and 17
Table 8-44 lists the valid slots for the EMS4 and corresponding slots for the EFF8.
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Table 8-44 Valid slots for the EMS4 and corresponding slots for the EFF8 Valid Slot for the EMS4 Slot 12 Slot 13 Corresponding Slot for the EFF8 Slots 14 and 15 Slots 16 and 17
Table 8-45 lists the valid slots for the EMR0 and corresponding slots for the EFF8. Table 8-45 Valid slots for the EMR0 and corresponding slots for the EFF8 Valid Slot for the EMR0 Slot 12 Slot 13 Corresponding Slot for the EFF8 Slots 14 and 15 Slots 16 and 17
Specification 10 Mbit/s or 100 Mbit/s Manchester encoding signal (10M) or MLT-3 encoding signal (100M) 100Base-FX 100Base-FX (15 km): 1261 to 1360 100Base-FX (2 km): 1270 to 1380 MLM 100Base-FX (15 km): 15 to 8 100Base-FX (2 km): 19 to 14 100Base-FX (15 km): 28 100Base-FX (2 km): 30 100Base-FX (15 km): 7
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Item
10
Mechanical Specifications
The mechanical specifications of the EFF8 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the EFF8 is 6 W.
8.15 ETF8
This section describes the ETF8, an 8 x 100M Ethernet twisted pair interface board, in terms of the version, function, principle, front panel and specifications. 8.15.1 Version Description The functional version of the ETF8 board is N1. 8.15.2 Function and Feature The ETF8 is used to receive and transmit 8 x 100M Ethernet electrical signals, and the ETF8 must be used with the Ethernet processing board. 8.15.3 Working Principle and Signal Flow The ETF8 consists of the interface module, switch matrix module, and power supply module. 8.15.4 Front Panel On the front panel of the ETF8, there are interfaces and barcode. 8.15.5 Valid Slots When used with different Ethernet processing boards, the ETF8 can be housed in different slots. 8.15.6 Technical Specifications The technical specifications of the ETF8 cover the electrical interface specifications, board dimensions, weight and power consumption.
100M
EFT8/ EFS0/EMS4/EMR0
Interface module
100M EFT8/EFS0/EMS4/EMR0
+3.3 V
Power module
Fuse
+3.3 V Power
Interface Module
In the receive direction, the interface module performs the O/E convertion for the Ethernet signals, and transmits the signals to the EFT8, EFS0, EMS4, or EMR0 board. In the transmit direction, the interface module performs the E/O convertion for the Ethernet signals, and transmits the signals to the optical interface.
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ETF8
Interfaces
There are eight electrical interfaces on the front panel of the ETF8. Table 8-47 lists the type and usage of interfaces on the ETF8. Table 8-47 Interfaces of the ETF8 Interface FE1FE8 Interface Type RJ-45 Usage Receive eight (18) channels of Ethernet electrical signals.
Table 8-48 lists the pins of the RJ-45 connector of the ETF8.
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Table 8-48 Pins of the RJ-45 connector of the ETF8 Front View Pin 1 2 3
8 7 6 5 4 3 2 1
Specification Transmitting positive Transmitting negative Receiving positive Grounding Grounding Receiving negative Grounding Grounding
4 5 6 7 8
As the interface board for the EFT8, the ETF8 can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. As the interface board for the EFS0, the ETF8 can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. As the interface board for the EMS4, the ETF8 can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. As the interface board for the EMR0, the ETF8 can be housed in any of slots 1417 in the OptiX OSN 1500B subrack.
Table 8-49 lists the valid slots for the EFT8 and corresponding slots for the ETF8. Table 8-49 Valid slots for the EFT8 and corresponding slots for the ETF8 Valid Slot for the EFT8 Slot 12 Slot 13 Corresponding Slot for the ETF8 Slots 14 and 15 Slots 16 and 17
Table 8-50 lists the valid slots for the EFS0 and corresponding slots for the ETF8.
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Table 8-50 Valid slots for the EFS0 and corresponding slots for the ETF8 Valid Slot for the EFS0 Slot 12 Slot 13 Corresponding Slot for the ETF8 Slots 14 and 15 Slots 16 and 17
Table 8-51 lists the valid slots for the EMS4 and corresponding slots for the ETF8. Table 8-51 Valid slots for the EMS4 and corresponding slots for the ETF8 Valid Slot for the EMS4 Slot 12 Slot 13 Corresponding Slot for the ETF8 Slots 14 and 15 Slots 16 and 17
Table 8-52 lists the valid slots for the EMR0 and corresponding slots for the ETF8. Table 8-52 Valid slots for the EMR0 and corresponding slots for the ETF8 Valid Slot for the EMR0 Slot 12 Slot 13 Corresponding Slot for the ETF8 Slots 14 and 15 Slots 16 and 17
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Mechanical Specifications
The mechanical specifications of the ETF8 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the ETF8 is 2 W.
8.16 ETS8
This section describes the ETS8, an 8 x 10/100M Ethernet twisted pair interface switching board, in terms of the version, function, principle, front panel and specifications. 8.16.1 Version Description The functional version of the ETS8 board is N1. 8.16.2 Function and Feature The ETS8 is used to provide the TPS protection for 8 x FE signals at the electrical interface, and the ETS8 must be used with the EFS0. 8.16.3 Working Principle and Signal Flow The ETS8 consists of the interface module, switch matrix module, and power supply module. 8.16.4 Front Panel On the front panel of the ETS8, there are interfaces and barcode. 8.16.5 Valid Slots As the interface board for the EFS0, the ETS8 can be housed in any of slots 14 and 16 in the OptiX OSN 1500B subrack. 8.16.6 Technical Specifications The technical specifications of the ETS8 cover the electrical interface specifications, board dimensions, weight and power consumption.
100M
Interface module
100M
+3.3 V
Fuse
Interface Module
The interface module receives and transmits the Ethernet optical signals.
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ETS8
Interfaces
There are eight electrical interfaces on the front panel of the ETS8. Table 8-54 lists the type and usage of interfaces on the ETS8. Table 8-54 Interfaces of the ETS8 Interface FE1FE8 Interface Type RJ-45 Usage Receive eight (18) channels of Ethernet electrical signals.
Table 8-55 lists the pins of the RJ-45 connector of the ETS8.
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Table 8-55 Pins of the RJ-45 connector of the ETS8 Front View Pin 1 2 3 4 5
8 7 6 5 4 3 2 1
Specification Transmitting positive Transmitting negative Receiving positive Grounding Grounding Receiving negative Grounding Grounding
6 7 8
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Mechanical Specifications
The mechanical specifications of the ETS8 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 0.37
Power Consumption
In the normal temperature (25), the maximum power consumption of the ETS8 in the switching state is 3 W and that of the ETS8 in the normal state is 0 W.
8.17 DM12
This section describes the DM12, a DDN interface board, in terms of the version, function, principle, front panel and specifications. 8.17.1 Version Description The functional version of the DM12 board is N1. 8.17.2 Function and Feature The DM12 is used to receive and transmit four channels of N x 64 kbit/s and 8 x framed E1 electrical signals, and the DM12 must be used with the DX1. 8.17.3 Working Principle and Signal Flow The DM12 consists of the interface module, switch matrix module, and power supply module. 8.17.4 Front Panel On the front panel of the DM12, there are interfaces and barcode. 8.17.5 Valid Slots As the interface board for the DX1, the DM12 can be housed in any of slots 1417 in the OptiX OSN 1500B subrack. 8.17.6 Technical Specifications The technical specifications of the DM12 cover the board dimensions, weight and power consumption.
Nx64kbit/s / Frame E1
Nx64kbit/s / Frame E1
DX1
+3.3 V
Fuse
+3.3 V Power
Interface Module
The interface module receives and transmits one channel of N x 64 kbit/s or framed E1 electrical signals.
Interfaces
On the front panel of the DM12, there are DB44 and DB28 interfaces. Table 8-58 lists the specifications of the interfaces. Table 8-58 Interfaces on the front panel of the DM12 Interface E1 (18) DDN1DDN4 Interface Type DB44 DB28 Usage Access 8 x framed E1 signals. Access four channels of N x 64 kbit/s signals.
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Table 8-59 Pins of the DB44 interfaces of the DM12 Front View
1
Pin 30 15 29 14 28 13
Specification T1 to transmit the first channel of signals. T2 to transmit the second channel of signals. T3 to transmit the third channel of signals. T4 to transmit the fourth channel of signals. T5 to transmit the fifth channel of signals. T6 to transmit the sixth channel of signals. T7 to transmit the seventh channel of signals. R1 to receive the first channel of signals. R2 to receive the second channel of signals.
Pin 8 7 36 21 35 20 34 19 33 18 32 17 31 16 4439, 61
Specification T8 to transmit the eighth channel of signals. R3 to receive the third channel of signals. R4 to receive the fourth channel of siganls. R5 to receive the fifth channel of signals. R6 to receive the sixth channel of signals. R7 to receive the seventh channel of signals. R8 to receive the eighth channel of signals. Grounding
44
27 12 26 11 25 10 24 9 38 23 37 22
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Table 8-60 Pins of the DB28 interfaces of the DM12 Front View
1
Pin 1 2 3 4 11 12
Pin 19 20 21 22 23 24 25 26 27 28 -
Grounds. Loopbacks the control signals. Permits the transmission. Prepares the terminating equipment. Prepares the terminal equipment.
Detects the carrier. Requests for transmission. Transmits the clock of the external equipment. Receives the clock signals.
28
13 14 15 16 17 18
Mechanical Specifications
The mechanical specifications of the DM12 are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.5
Power Consumption
In the normal temperature (25), the maximum power consumption of the DM12 in the switching state is 8 W and that of the DM12 in the normal state is 0 W.
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This section describes the CXLQ1, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.10 CXLQ4 This section describes the CXLQ4, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications.
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9.1 CXL1
This section describes the CXL1, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.1.1 Version Description The CXL1 board has two functional versions, Q2 and Q3. The main differences between the Q2 and Q3 versions are that the Q3 version supports transmitting the DCC overhead information at a two-port external clock interface, supports transparently transmitting DCC bytes in TPS group and supports the CF card and package loading function. 9.1.2 Function and Feature The CXL1 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.1.3 Working Principle and Signal Flow The CXL1 consists of the SDH overhead processing module, RST, MST and so on. 9.1.4 Jumper and DIP Switch On the CXL1, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.1.5 Front Panel On the front panel of the Q2CXL1, there are indicators, interfaces, functional button switch, barcode and laser safety class label. On the front panel of the Q3CXL1 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.1.6 Valid Slots The CXL1 can be housed in any of or slots 45 in the subrack. 9.1.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXL1 indicates the optical interface type. 9.1.8 Board Configuration Reference The physical slot that houses the CXL1 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXL1. 9.1.9 Technical Specifications The technical specifications for the CXL1 cover the optical interface specifications, board dimensions, weight and power consumption.
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Table 9-1 Version description of the CXL1 board Item Functional Version Difference Description The CXL1 board has two functional versions, Q2 and Q3. The Q3CXL1 board supports transmitting the DCC information at a two-channel external clock interface. The Q3CXL1 hardware supports the CF card, and the Q3CXL1 supports software package loading function. Q3CXL1 supports transparently transmitting DCC bytes in TPS group. Replaceability The Q3CXL1 board can fully replace the Q2CXL1 board.
Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports the processing of the SOH bytes of the STM-1 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports multiple protection modes such as two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP..
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CXL1
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Supports inloop and outloop for optical interfaces. Supports the warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. The Q3CXL1 board hardware supports the CF card, and the Q3CXL1 software supports the package loading function. The CF card is hot pluggable. The capacity is 512 MB and can be expanded to 1 GB.
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SCC Unit
Table 9-3 lists the function and feature of the SCC unit of the CXL1. Table 9-3 Function and feature of the SCC unit of the CXL1 Function and Feature Basic function Specification of the optical interface CXL1 Configures and monitors services, monitors the service performance, and collects performance events and alarm information.
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Provides 10M/100M compatible Ethernet NMS interface. Provides one 10M/100M Ethernet interface, which is used for inter-board communication. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards. Provides the RS232 OAM interface that is present on the auxiliary interface board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. The Q3CXL1 board supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Q2CXL1 processes 40-channel DCC, Q3CXL1 processes 80-channel DCC. Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU.
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Cross-Connect Unit
Table 9-4 lists the function and feature of the cross-connect unit of the CXL1. Table 9-4 Function and feature of the cross-connect unit of the CXL1 Function and Feature Basic function CXL1 Completes 20 Gbit/s non-blocking full cross-connection at the VC-4 level, and 20 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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Dynamically grooms services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels.
Protection scheme
Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-5 lists the function and feature of the clock unit of the CXL1. Table 9-5 Function and feature of the clock unit of the CXL1 Function and Feature Basic function Other function CXL1 Provides standard system synchronization clock. Supports the extraction, insertion and management of the SSM and clock ID. The Q3CXL1 board supports transmitting the DCC overhead information at a two-channel external clock interface. Input and output
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Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
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SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
Figure 9-2 shows the block diagram for the functions of the Q3CXL1 board.
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Figure 9-2 Block diagram for the functions of the Q3CXL1 board
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
source (T4) are generated. The boards apply 1 + 1 hot backup. Therefore, both the active and the standby boards tracing the same reference source to ensure the identity between the system clocks of the active and the standby boards. The synchronous timing unit can extract timing from three types of timing signal:
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Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation.
Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd 9-9
MST
MSA
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HPT
OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/ 100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXL unit. The Q3CXL1 board supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-3 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-3 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
SAP SAP
F&f interface
Power monitor
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 20 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 20 G lower order services.
Other Functions
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The CF card is hot pluggable. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-4 shows the layout of the J3 jumper and DIP switch SW1 on the CXL1 board.
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3 2 1
J3
CF card
SCC Unit
1 2 3 4
SW1
Table 9-6 lists the jumper on the CXL1 board. Table 9-6 Jumper on the CXL1 board Jumper J3 Function Enable the battery. Description 1-2: When jumpers 1 and 2 are capped, the battery is enabled.
Table 9-7 lists the DIP switch on the CXL1 board. Table 9-7 DIP switch on the CXL1 board DIP Switch SW1 Function Set the board running state Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer to Table 9-8.
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Table 9-8 Description of the DIP switch SW1 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
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OUT IN
CXL1
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OUT IN
RESET ALM CUT CF R/W CF ON/OFF
CXL1
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXL1, there are one optical interface and two switches. Table 9-9 lists the type and usage of the optical interface and switches on the CXL1. Table 9-9 Optical interface and switches on the CXL1 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch CF card insersion / removal switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound. Changes the state of the CF card.
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CF ON/OFF
When the CF card is in the read/write state, or when it is reading or writing data, the indicator changes to red and then the CF card changes to the read/write prohibited state if the switch is pressed for five seconds. In this case, you can remove the CF card. When the CF card is in the read/write prohibited state, the indicator changes to green if the switch is pressed for five seconds. Then the CF card restores to the read/ write state.
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11
L-1.1 (LC)
12
L-1.2 (LC)
13
Ve-1.2 (LC)
14
I-1 (LC)
Displayed Slot
The CXL1 is housed in one slot in the subrack. The logical boards for the CXL1 are the Q1SL1, EXCL and GSCC. Table 9-11 lists the logical slots displayed on the T2000.
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Table 9-11 Logical slots displayed on the T2000 for the CXL1 Board CXL1 Logical Board Q1SL1 ECXL GSCC Logical Slot Slots 45 Slots 8081 Slots 8283
Board Parameters
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Specification 155520 kbit/s NRZ I-1 1260 to 1360 MLM, LED 15 to 8 S-1.1 1261 to 1360 MLM 15 to 8 L-1.1 1263 to 1360 MLM, SLM 5 to 0 L-1.2 1480 to 1580 SLM 5 to 0 Ve-1.2 1480 to 1580 SLM 3 to 0
23 8
28 8
34 10
34 10
34 10
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Cross-Connect Capacity
The cross-connect capacity of the CXL1 is as follows:
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Higher order cross-connect capacity: 20 Gbit/s Lower order cross-connect capacity: 20 Gbit/s Access capacity: 18.75 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specifications for the CXL1 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg):
Power Consumption
At the normal temperature (25), the maximum power consumption for the CXL1 is as follows:
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9.2 CXL4
This section describes the CXL4, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.2.1 Version Description The CXL4 board has two functional versions, Q2 and Q3. The main differences between the Q2 and Q3 versions are that the Q3 version supports transmitting the DCC overhead information at
9-20 Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
a two-port external clock interface, supports transparently transmitting DCC bytes in TPS group and supports the CF card and package loading function. 9.2.2 Function and Feature The CXL4 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.2.3 Working Principle and Signal Flow The CXL4 consists of the SDH overhead processing module, RST, MST and so on. 9.2.4 Jumper and DIP Switch On the CXL4, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.2.5 Front Panel On the front panel of the Q2CXL4, there are indicators, interfaces, functional button switch, barcode and laser safety class label. On the front panel of the Q3CXL4 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.2.6 Valid Slots The CXL4 can be housed in any of or slots 45 in the subrack. 9.2.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXL4 indicates the optical interface type. 9.2.8 Board Configuration Reference The physical slot that houses the CXL4 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXL4. 9.2.9 Technical Specifications The technical specifications for the CXL4 cover the optical interface specifications, board dimensions, weight and power consumption.
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Item Replaceability
Description The Q3CXL4 board can fully replace the Q2CXL4 board.
Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports VC-12, VC-3, and VC-4 services and VC4-4c concatenation services.
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Supports the processing of the SOH bytes of the STM-4 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports multiple protection modes such as two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP..
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CXL4
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Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. The Q3CXL4 board hardware supports the CF card, and the Q3CXL1 software supports the package loading function. The CF card is hot pluggable. The capacity is 512 MB and can be expanded to 1 GB.
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SCC Unit
Table 9-15 lists the function and feature of the SCC unit of the CXL4 Table 9-15 Function and feature of the SCC unit of the CXL4 Function and Feature Basic function Specification of the optical interface CXL4 Configures and monitors services, monitors the service performance, and collencts performance events and alarm information.
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Provides 10M/100M compatible Ethernet NMS interface. Provides one 10M/100M Ethernet interface, which is used for inter-board communication. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards. Provides the RS232 OAM interface that is present on on the auxiliary interface board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. The Q3CXL4 board supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Q2CXL4 processes 40-channel DCC, Q3CXL4 processes 80-channel DC. Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU.
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Cross-Connect Unit
Table 9-16 lists the function and feature of the cross-connect unit of the CXL4. Table 9-16 Function and feature of the cross-connect unit of the CXL4 Function and Feature Basic function CXL4 Completes 20 Gbit/s non-blocking full cross-connection at the VC-4 level, and 20 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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Dynamically grooms services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels. Supports concatenation services at the VC4-4c level.
Protection scheme
Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-17 lists the function and feature of the clock unit of the CXL4. Table 9-17 Function and feature of the clock unit of the CXL4 Function and Feature Basic function Other function CXL4 Provides standard system synchronization clock. Supports the extraction, insertion and management of the SSM and clock ID. The Q3CXL4 board supports transmitting the DCC overhead information at a two-port external clock interface. Input and output
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Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
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SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
SAP SAP
F&f interface
Power monitor
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
Figure 9-8shows the block diagram for the functions of the Q3CXL4 board.
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Figure 9-8 Block diagram for the functions of the Q3CXL4 board
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
source (T4) are generated. The boards apply 1 + 1 hot backup. Therefore, both the active and the standby boards tracing the same reference source to ensure the identity between the system clocks of the active and the standby boards. The synchronous timing unit can extract timing from three types of timing signal:
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Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation.
Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd 9-27
MST
MSA
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HPT
OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/ 100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXL unit. The Q3CXL4 board supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-9 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-9 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
SAP SAP
F&f interface
Power monitor
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 20 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 20 G lower order services.
Other Functions
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The CF card is hot pluggable. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-10 shows the layout of the J3 jumper and DIP switch SW1 on the CXL4 board.
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3 2 1
J3
CF card
SCC Unit
1 2 3 4
SW1
Table 9-18 lists the jumper on the CXL4 board. Table 9-18 Jumper on the CXL4 board Jumper J3 Function Enable the battery. Description 1-2: When jumpers 1 and 2 are capped, the battery is enabled.
Table 9-19 lists the DIP switch on the CXL board. Table 9-19 DIP switch on the CXL4 board DIP Switch SW1 Function Set the board running state. Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer to Table 9-20.
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Table 9-20 Description of DIP switch SW1 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
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OUT IN
RESET
ALM CUT
CXL4
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OUT IN
RESET ALM CUT CF R/W CF ON/OFF
CXL4
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXL4, there are one optical interface and two switches. Table 9-21 lists the type and usage of the optical interface and switches on the CXL4. Table 9-21 Optical interface and switches on the CXL4 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound. Changes the state of the CF card.
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CF ON/OFF
When the CF card is in the read/write state, or when it is reading or writing data, the indicator changes to red and then the CF card changes to the read/write prohibited state if the switch is pressed for five seconds. In this case, you can remove the CF card. When the CF card is in the read/write prohibited state, the indicator changes to green if the switch is pressed for five seconds. Then the CF card is restored to the read/write state.
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11
L-4.1 (LC)
12
L-4.2 (LC)
13
Ve-4.2 (LC)
14
I-4 (LC)
Displayed Slot
The CXL4 is housed in one slot in the subrack. The logical boards for the CXL4 are the Q1SL4, EXCL and GSCC. Table 9-23 lists the logical slots displayed on the T2000.
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Table 9-23 Logical slots displayed on the T2000 for the CXL4 Board CXL4 Logical Board Q1SL4 ECXL GSCC Logical Slot Slots 45 Slots 8081 Slots 8283
Board Parameters
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Specification 622080 kbit/s NRZ I-4 1261 to 1360 MLM 15 to 8 S-4.1 1274 to 1356 MLM 15 to 8 L-4.1 1280 to 1335 SLM 3 to 2 L-4.2 1480 to 1580 SLM 3 to 2 Ve-4.2 1480 to 1580 SLM 3 to 2
23 8
28 8
28 8
28 8
34 13
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Cross-Connect Capacity
The cross-connect capacity of the CXL4 is described as follows:
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Higher order cross-connect capacity: 20 Gbit/s Lower order cross-connect capacity: 20 Gbit/s Access capacity: 18.75 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specifications for the CXL4 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg):
Power Consumption
At the normal temperature (25), the maximum power consumption of the CXL4 is:
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9.3 CXL16
This section describes the CXL16, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.3.1 Version Description The CXL1 board has two functional versions, Q2 and Q3. The main differences between the Q2 and Q3 versions are that the Q3 version supports transmitting the DCC overhead information at
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a two-port external clock interface, supports transparently transmitting DCC bytes in TPS group and supports the CF card and package loading function. 9.3.2 Function and Feature The CXL16 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.3.3 Working Principle and Signal Flow The CXL16 consists of the SDH overhead processing module, RST, MST and so on. 9.3.4 Jumper and DIP Switch On the CXL16, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.3.5 Front Panel On the front panel of the Q2CXL16, there are indicators, interfaces, functional button switch, barcode and laser safety class label. On the front panel of the Q3CXL16 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.3.6 Valid Slots The CXL16 can be housed in any of slots 45 in the subrack. 9.3.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXL16 indicates the optical interface type. 9.3.8 Board Configuration Reference The physical slot that houses the CXL16 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXL16. 9.3.9 Technical Specifications The technical specifications for the CXL16 cover the optical interface specifications, board dimensions, weight and power consumption.
Item Replaceability
Description The Q3CXL16 board can fully replace the Q2CXL16 board.
Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports VC-12, VC-3, and VC-4 services and VC4-4c, VC4-8c, and VC4-16c concatenation services.
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Supports the processing of the SOH bytes of the STM-16 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports the two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP.
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CXL16
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Supports inloop and outloop for optical interfaces. Supports warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services. The Q3CXL16 board hardware supports the CF card, and the Q3CXL16 software supports the package loading function. The CF card is hot pluggable. The capacity is 512 MB and can be expanded to 1 GB.
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SCC Unit
Table 9-27 lists the function and feature of the SCC unit of the CXL16 Table 9-27 Function and feature of the SCC unit of the CXL16 Function and Feature Basic function Specification of the optical interface CXL16 Configures and monitors services, monitors the service performance, and collects performance events and alarm information.
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Provides 10M/100M compatible Ethernet NMS interface. Provides one 10M/100M Ethernet interface, which is used for inter-board communication. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards. Provides the RS232 OAM interface that is present on on the auxiliary interface board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. The Q3CXL16 board supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Q2CXL16 processes 40-channel DCC, Q3CXL16 processes 80channel DCC. Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU.
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Cross-Connect Unit
Table 9-28 lists the function and feature of the cross-connect unit of the CXL16. Table 9-28 Function and feature of the cross-connect unit of the CXL16 Function and Feature Basic function CXL16 Completes 20 Gbit/s non-blocking full cross-connection at the VC-4 level, and 20 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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Dynamically grooms services, such as the cross-connect and broadcast services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels. Supports concatenation services at the VC4-4c, VC4-8c and VC4-16c levels.
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Protection scheme
Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-29 lists the function and feature of the clock unit of the CXL16. Table 9-29 Function and feature of the clock unit of the CXL16 Function and Feature Basic function Other function CXL16 Provides standard system synchronization clock. Supports the extraction, insertion and management of the SSM and clock ID. The Q3CXL16 board supports transmitting the DCC overhead information at a two-port external clock interface.
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CXL16
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Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
SAP SAP
F&f interface
Power monitor
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
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Figure 9-14shows the block diagram for the functions of the Q3CXL16 board. Figure 9-14 Block diagram for the functions of the Q3CXL16 board
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
sources are from the line board (T1), the tributary board (T2), the external synchronous clock source (T3) and so on. The synchronous system clock source (T0) and 2 M external synchronous source (T4) are generated. The boards apply 1 + 1 hot backup. Therefore, both the active and the standby boards tracing the same reference source to ensure the identity between the system clocks of the active and the standby boards. The synchronous timing unit can extract timing from three types of timing signal:
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Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification.
Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd 9-45
MST
MSA
Issue 02 (2007-03-29)
In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
HPT
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXL unit. The Q3CXL16 board supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-15 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-15 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
SAP SAP
F&f interface
Power monitor
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 20 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 20 G lower order services.
Other Functions
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
DC Converter Module
This module provides the board with required DC voltages. It converts the 48/60 V power supply to the following voltages: +5V, +1.6V, +1.8V +1.2V and+3.3V.
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The CF card is hot pluggable. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-16 shows the layout of the J3 jumper and DIP switch SW1 on the CXL16 board.
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3 2 1
J3
CF card
SCC Unit
1 2 3 4
SW1
Table 9-30 lists the jumper on the CXL16 board. Table 9-30 Jumper on the CXL16 board Jumper J3 Function Enable the battery. Description 1-2: When jumpers 2 and 3 are capped, the battery is enabled.
Table 9-31 lists the DIP switch on the CXL board. Table 9-31 DIP switch on the CXL16 board DIP Switch SW2 Function Set the board running state. Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer toTable 9-32.
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Table 9-32 Description of the DIP switch SW1 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
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CXL16
STAT ACTX ACTC PROG SRVX SRVL SYNC ALMC
CLASS 1 LASER PRODUCT
OUT IN
CXL16
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OUT IN
RESET ALM CUT CF R/W CF ON/OFF
CXL16
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXL16, there are one optical interface and two switches. Table 9-33 lists the type and usage of the optical interface and switches on the CXL16. Table 9-33 Optical interface and switches on the CXL16 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch CF card insertion / removal switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound. Changes the state of the CF card.
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CF ON/OFF
When the CF card is in the read/write state, or when it is reading or writing data, the indicator changes to red and then the CF card changes to the read/write prohibited state if the switch is pressed for five seconds. In this case, you can remove the CF card. When the CF card is in the read/write prohibited state, the indicator changes to green if the switch is pressed for five seconds. Then the CF card is restored to the read/write state.
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11
L-16.1
12
L-16.2
14
I-16
Displayed Slot
The CXL16 is housed in one slot in the subrack. The logical boards for the CXL16 are the Q1SL16, EXCL and GSCC. Table 9-35 lists the logical slots displayed on the T2000. Table 9-35 Logical slots displayed on the T2000 for the CXL16 Board CXL16 Logical Board Q1SL16 ECXL
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Board
Board Parameters
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18 3 8.2
18 0 8.2
27 9 8.2
28 9 8.2
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Cross-Connect Capacity
The cross-connect capacity of the CXL16 described as follows:
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Higher order cross-connect capacity: 20 Gbit/s Lower order cross-connect capacity: 20 Gbit/s Access capacity: 18.75 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specifications for the CXL16 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg):
Power Consumption
At the normal temperature (25), the maximum power consumption of the CXL16 is as follows:
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9.4 CXLL1
This section describes the CXLL1, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.4.1 Version Description The functional version of CXLL1 board is R1. 9.4.2 Function and Feature The CXLL1 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.4.3 Working Principle and Signal Flow The CXLL1 consists of the SDH overhead processing module, RST, MST and so on. 9.4.4 Jumper and DIP Switch
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On the CXL, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.4.5 Front Panel On the front panel of the CXLL1 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.4.6 Valid Slots The CXLL1 can be housed in any of slots 45 in the subrack. 9.4.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXLL1 indicates the optical interface type. 9.4.8 Board Configuration Reference The physical slot that houses the CXLL1 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXLL1. 9.4.9 Technical Specifications The technical specifications for the CXLL1 cover the optical interface specifications, board dimensions, weight and power consumption.
Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports the processing of the SOH bytes of the STM-1 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
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CXLL1 Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports multiple protection modes such as two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP..
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Maintenance feature
Supports inloop and outloop for optical interfaces. Supports the warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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SCC Unit
Table 9-38 lists the function and feature of the SCC unit of the CXLL1. Table 9-38 Function and feature of the SCC unit of the CXLL1 Function and Feature Basic function Specification of the optical interface CXLL1 Configures and monitors services, monitors the service performance, and collects performance events and alarm information.
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Provides 10M/100M compatible Ethernet NMS interface, which is present on the AUC board. Provides one 10M/100M Ethernet interface, which is used for inter-board communication and is present on the AUX board. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards and is present on the AUX board. Provides the RS232 OAM interface that is present on the AUX board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Supports the CF card, and supports the package loading function. The capacity is 512 MB and can be expanded to 1 GB. Processes 40-channel DCC.
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Function and Feature Fan alarm management PIU management Protection scheme
CXLL1 Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU. Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-39 lists the function and feature of the cross-connect unit of the CXLL1. Table 9-39 Function and feature of the cross-connect unit of the CXLL1 Function and Feature Basic function CXLL1 Completes 15 Gbit/s non-blocking full cross-connection at the VC-4 level, and 5 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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Dynamically grooms services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels. Supports VC--4-4c, VC-4-8c and VC-4-16c concatenation services.
Protection scheme
Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-40 lists the function and feature of the clock unit of the CXLL1. Table 9-40 Function and feature of the clock unit of the CXLL1 Function and Feature Basic function CXLL1 Provides standard system synchronization clock.
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CXLL1 Supports the extraction, insertion and management of the SSM and clock ID. Supports transmitting the DCC overhead information at a twochannel external clock interface.
Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
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SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering
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MST
MSA
HPT
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HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/ 100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXLL unit. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-20 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-20 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-16
O/E
DEMUX
RST
16x155 Mbit/s data
MST
MSA
HPT
STM-16
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 15 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 5 G lower order services.
Other Functions
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-21 shows the layout of the J7 jumper and DIP switch SW2 on the CXL board. Figure 9-21 Jumper and DIP switch of the CXL board
Power module
CPU
1 2 3 4
SW2
1 2 3
J7
CF card
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Table 9-41 lists the jumper on the CXL board. Table 9-41 Jumper on the CXL board Jumper J7 Function Enable the battery. Description 1-2: When jumpers 2 and 3 are capped, the battery is enabled.
Table 9-42 lists the DIP switch on the CXL board. Table 9-42 DIP switch on the CXL board DIP Switch SW2 Function Set the board running state Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer to Table 9-43.
Table 9-43 Description of the DIP switch SW2 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
OUT IN
CF R/W RESET ALM CUT
CXLL1
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXLL1, there are one optical interface and two switches. Table 9-44 lists the type and usage of the optical interface and switches on the CXLL1. Table 9-44 Optical interface and switches on the CXLL1 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound.
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Table 9-45 Relation between the board feature code and the optical interface type Board Barcode SSR1CXLL110 SSR1CXLL111 SSR1CXLL112 SSR1CXLL113 SSR1CXLL114 Feature Code 10 11 12 13 14 Optical Interface Type S-1.1 (LC) L-1.1 (LC) L-1.2 (LC) Ve-1.2 (LC) I-1 (LC)
Displayed Slot
The CXLL1 is housed in one slot in the subrack. The logical boards for the CXLL1 are the R1SLN, RCXL and GSCC. Table 9-46 lists the logical slots displayed on the T2000. Table 9-46 Logical slots displayed on the T2000 for the CXLL1 Board CXLL1 Logical Board R1SLN RCXL GSCC Logical Slot Slots 45 Slots 8081 Slots 8283
Board Parameters
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Table 9-47 Specifications for the optical interfaces of the CXLL1 Item Nominal bit rate Line code Optical interface type Working wavelength (nm) Optical source type Mean launched optical power (dBm) Receiver sensitivity (dBm) Min. overload (dBm) Min. extinction ratio (dB) Specification 155520 kbit/s NRZ I-1 1260 to 1360 MLM, LED 15 to 8 S-1.1 1261 to 1360 MLM 15 to 8 L-1.1 1263 to 1360 MLM, SLM 5 to 0 L-1.2 1480 to 1580 SLM 5 to 0 Ve-1.2 1480 to 1580 SLM 3 to 0
23 8 8.2
28 8 8.2
34 10 10
34 10 10
34 10 10
Cross-Connect Capacity
The cross-connect capacity of the CXLL1 is as follows:
l l l
Higher order cross-connect capacity: 15 Gbit/s Lower order cross-connect capacity: 5 Gbit/s Access capacity: 10 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specifications for the CXLL1 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg):1.0kg
Power Consumption
At the normal temperature (25), the maximum power consumption for the CXLL1 is 50W.
9.5 CXLL4
This section describes the CXLL4, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.5.1 Version Description The functional version of CXLL4 board is R1. 9.5.2 Function and Feature The CXLL4 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.5.3 Working Principle and Signal Flow The CXLL4 consists of the SDH overhead processing module, RST, MST and so on. 9.5.4 Jumper and DIP Switch On the CXL, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.5.5 Front Panel On the front panel of the CXLL4 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.5.6 Valid Slots The CXLL4 can be housed in any of slots 45 in the subrack. 9.5.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXLL4 indicates the optical interface type. 9.5.8 Board Configuration Reference The physical slot that houses the CXLL4 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXLL4. 9.5.9 Technical Specifications The technical specifications for the CXLL4 cover the optical interface specifications, board dimensions, weight and power consumption.
Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports the processing of the VC-12, VC-3, VC-4 services and VC4-4c concatenation services..
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Supports the processing of the SOH bytes of the STM-4 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports multiple protection modes such as two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP..
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Maintenance feature
Supports inloop and outloop for optical interfaces. Supports the warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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SCC Unit
Table 9-49 lists the function and feature of the SCC unit of the CXLL4.
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Table 9-49 Function and feature of the SCC unit of the CXLL4 Function and Feature Basic function Specification of the optical interface CXLL4 Configures and monitors services, monitors the service performance, and collects performance events and alarm information.
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Provides 10M/100M compatible Ethernet NMS interface, which is present on AUX. Provides one 10M/100M Ethernet interface, which is used for inter-board communication and present on AUX board. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards and present on AUX board. Provides the RS232 OAM interface that is present on the AUX board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Maintenance feature DCC processing capability Fan alarm management PIU management Protection scheme
Supports the CF card, and supports the package loading function. The capacity is 512 MB and can be expanded to 1 GB. Processes 40-channel DCC. Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU. Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-50 lists the function and feature of the cross-connect unit of the CXLL4. Table 9-50 Function and feature of the cross-connect unit of the CXLL4 Function and Feature Basic function CXLL4 Completes 15 Gbit/s non-blocking full cross-connection at the VC-4 level, and 5 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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CXLL4
l l l l l
Dynamically grooms services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels. Supports a maximum of 1024 SNCP protection pairs. Supports VC-4-4c concatenation services.
Protection scheme
Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-51 lists the function and feature of the clock unit of the CXLL4. Table 9-51 Function and feature of the clock unit of the CXLL4 Function and Feature Basic function Other function CXLL4 Provides standard system synchronization clock. Supports the extraction, insertion and management of the SSM and clock ID. Supports transmitting the DCC overhead information at a twochannel external clock interface. Input and output
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Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
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SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering
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MST
MSA
HPT
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HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/ 100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXLL unit. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-24 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-24 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-16
O/E
DEMUX
RST
16x155 Mbit/s data
MST
MSA
HPT
STM-16
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 15 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 5 G lower order services.
Other Functions
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-25 shows the layout of the J7 jumper and DIP switch SW2 on the CXL board. Figure 9-25 Jumper and DIP switch of the CXL board
Power module
CPU
1 2 3 4
SW2
1 2 3
J7
CF card
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Table 9-52 lists the jumper on the CXL board. Table 9-52 Jumper on the CXL board Jumper J7 Function Enable the battery. Description 1-2: When jumpers 2 and 3 are capped, the battery is enabled.
Table 9-53 lists the DIP switch on the CXL board. Table 9-53 DIP switch on the CXL board DIP Switch SW2 Function Set the board running state. Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer to Table 9-54.
Table 9-54 Description of DIP switch SW2 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
OUT IN
CF R/W RESET ALM CUT
CXLL4
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXLL4, there are one optical interface and two switches. Table 9-55 lists the type and usage of the optical interface and switches on the CXLL4. Table 9-55 Optical interface and switches on the CXLL4 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound.
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Table 9-56 Relation between the board feature code and the optical interface type Board Barcode SSR1CXLL410 SSR1CXLL411 SSR1CXLL412 SSR1CXLL413 SSR1CXLL414 Feature Code 10 11 12 13 14 Optical Interface Type S-4.1 (LC) L-4.1 (LC) L-4.2 (LC) Ve-4.2 (LC) I-4 (LC)
Displayed Slot
The CXLL4 is housed in one slot in the subrack. The logical boards for the CXLL4 are the R1SLN, RCXL and GSCC. Table 9-57 lists the logical slots displayed on the T2000. Table 9-57 Logical slots displayed on the T2000 for the CXLL4 Board CXLL4 Logical Board R1SLN RCXL GSCC Logical Slot Slots 45 Slots 8081 Slots 8283
Board Parameters
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Table 9-58 Specifications for the optical interfaces of the CXLL4 Item Nominal bit rate Line code Optical interface type Working wavelength (nm) Optical source type Mean launched optical power (dBm) Receiver sensitivity (dBm) Min. overload (dBm) Min. extinction ratio (dB) Specification 622080 kbit/s NRZ I-4 1260 to 1360 MLM 15 to 8 S-4.1 1274 to 1356 MLM 15 to 8 L-4.1 1280 to 1335 SLM 3 to 2 L-4.2 1480 to 1580 SLM 3 to 2 Ve-4.2 1480 to 1580 SLM 3 to 2
23 8 8.2
28 8 8.2
28 18 10
28 8 10
34 13 10.5
Cross-Connect Capacity
The cross-connect capacity of the CXLL4 is as follows:
l l l
Higher order cross-connect capacity: 15 Gbit/s Lower order cross-connect capacity: 5 Gbit/s Access capacity: 10 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specifications for the CXLL4 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg):1.0kg
Power Consumption
At the normal temperature (25), the maximum power consumption for the CXLL4 is 50W.
9.6 CXLL16
This section describes the CXLL16, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.6.1 Version Description The functional version of CXLL16 board is R1. 9.6.2 Function and Feature The CXLL16 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.6.3 Working Principle and Signal Flow The CXLL16 consists of the SDH overhead processing module, RST, MST and so on. 9.6.4 Jumper and DIP Switch On the CXL, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.6.5 Front Panel On the front panel of the CXLL16 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.6.6 Valid Slots The CXLL16 can be housed in any of slots 45 in the subrack. 9.6.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXLL16 indicates the optical interface type. 9.6.8 Board Configuration Reference The physical slot that houses the CXLL16 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXLL16. 9.6.9 Technical Specifications The technical specifications for the CXLL16 cover the optical interface specifications, board dimensions, weight and power consumption.
Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports the processing of the VC-12, VC-3, VC-4 services, and VC-4-4c, VC-4-8c, VC-4-16c concatenation services.
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Supports the processing of the SOH bytes of the STM-16 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports multiple protection modes such as two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP..
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Maintenance feature
Supports inloop and outloop for optical interfaces. Supports the warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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SCC Unit
Table 9-60 lists the function and feature of the SCC unit of the CXLL16.
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Table 9-60 Function and feature of the SCC unit of the CXLL16 Function and Feature Basic function Specification of the optical interface CXLL16 Configures and monitors services, monitors the service performance, and collects performance events and alarm information.
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Provides 10M/100M compatible Ethernet NMS interface, which is present on the AUX board. Provides one 10M/100M Ethernet interface, which is used for inter-board communication and is present on the AUX board. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards and is present on the AUX board. Provides the RS232 OAM interface that is present on the auxiliary interface board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Maintenance feature DCC processing capability Fan alarm management PIU management Protection scheme
Supports the CF card, and supports the package loading function. The capacity is 512 MB and can be expanded to 1 GB. Processes 40-channel DCC. Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU. Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-61 lists the function and feature of the cross-connect unit of the CXLL16. Table 9-61 Function and feature of the cross-connect unit of the CXLL16 Function and Feature Basic function CXLL16 Completes 15 Gbit/s non-blocking full cross-connection at the VC-4 level, and 5 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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CXLL16
l l l l l
Dynamically grooms services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels. Supports a maximum of 1024 SNCP protection pairs. Supports VC-4-4c, VC-4-8c and VC-4-16c services.
Protection scheme
Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-62 lists the function and feature of the clock unit of the CXLL16. Table 9-62 Function and feature of the clock unit of the CXLL16 Function and Feature Basic function Other function CXLL16 Provides standard system synchronization clock. Supports the extraction, insertion and management of the SSM and clock ID. Supports transmitting the DCC overhead information at a twochannel external clock interface. Input and output
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Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
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SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering
Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
MST
MSA
HPT
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HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/ 100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXLL unit. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-28 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-28 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-16
O/E
DEMUX
RST
16x155 Mbit/s data
MST
MSA
HPT
STM-16
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 15 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 5 G lower order services.
Other Functions
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-29 shows the layout of the J7 jumper and DIP switch SW2 on the CXL board. Figure 9-29 Jumper and DIP switch of the CXL board
Power module
CPU
1 2 3 4
SW2
1 2 3
J7
CF card
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Table 9-63 lists the jumper on the CXL board. Table 9-63 Jumper on the CXL board Jumper J7 Function Enable the battery. Description 1-2: When jumpers 2 and 3 are capped, the battery is enabled.
Table 9-64 lists the DIP switch on the CXL board. Table 9-64 DIP switch on the CXL board DIP Switch SW2 Function Set the board running state. Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer toTable 9-65.
Table 9-65 Description of the DIP switch SW2 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
OUT IN
CF R/W RESET ALM CUT
CXLL16
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXLL16, there are one optical interface and two switches. Table 9-66 lists the type and usage of the optical interface and switches on the CXLL16. Table 9-66 Optical interface and switches on the CXLL16 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound.
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Table 9-67 Relation between the board feature code and the optical interface type Board Barcode SSR1CXLL1601 SSR1CXLL1602 SSR1CXLL1603 SSR1CXLL1604 Feature Code 01 02 03 04 Optical Interface Type I-16 (LC) S-16.1 (LC) S-16.2(LC) L-16.2 (LC)
Displayed Slot
The CXLL16 is housed in one slot in the subrack. The logical boards for the CXLL16 are the R1SLN, RCXL and GSCC. Table 9-68 lists the logical slots displayed on the T2000. Table 9-68 Logical slots displayed on the T2000 for the CXLL16 Board CXLL16 Logical Board R1SLN RCXL GSCC Logical Slot Slots 45 Slots 8081 Slots 8283
Board Parameters
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Table 9-69 Specifications for the optical interfaces of the CXLL16 Item Nominal bit rate Line code Optical interface type Working wavelength (nm) Optical source type Mean launched optical power (dBm) Receiver sensitivity (dBm) Min. overload (dBm) Min. extinction ratio (dB) Specification 2488320 kbit/s NRZ I-16 1266 to 1360 MLM 10 to 3 18 3 8.2 S-16.1 1260 to 1360 SLM 5 to 0 18 0 8.2 L-16.1 1280 to 1335 SLM 2 to 3 27 9 8.2 L-16.2 1500 to 1580 SLM 2 to 3 28 9 8.2
Cross-Connect Capacity
The cross-connect capacity of the CXLL16 is as follows:
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Higher order cross-connect capacity: 15 Gbit/s Lower order cross-connect capacity: 5 Gbit/s Access capacity: 10 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specification for the CXLL16 is as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
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Power Consumption
At the normal temperature (25), the maximum power consumption for the CXLL4 is 50W.
9.7 CXLD1
This section describes the CXLD1, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.7.1 Version Description The functional version of CXLD1 board is R1. 9.7.2 Function and Feature The CXLD1 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.7.3 Working Principle and Signal Flow The CXLD1 consists of the SDH overhead processing module, RST, MST and so on. 9.7.4 Jumper and DIP Switch On the CXL, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.7.5 Front Panel On the front panel of the CXLD1 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.7.6 Valid Slots The CXLD1 can be housed in any of slots 45 in the subrack. 9.7.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXLD1 indicates the optical interface type. 9.7.8 Board Configuration Reference The physical slot that houses the CXLD1 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXLD1. 9.7.9 Technical Specifications The technical specifications for the CXLD1 cover the optical interface specifications, board dimensions, weight and power consumption.
Table 9-70 Function and feature of the SDH processing unit of the CXLD1 Function and Feature Basic function Specification of the optical interface Specification of the optical module CXLD1 Transmits and receives 2 x STM-1 optical signals. Supports the optical interfaces of the I-1, S-1.1, L-1.1, L-1.2, and Ve-1.2 types.
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Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports the processing of the SOH bytes of the STM-1 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports multiple protection modes such as two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP..
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Maintenance feature
Supports inloop and outloop for optical interfaces. Supports the warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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SCC Unit
Table 9-71 lists the function and feature of the SCC unit of the CXLD1. Table 9-71 Function and feature of the SCC unit of the CXLD1 Function and Feature Basic function CXLD1 Configures and monitors services, monitors the service performance, and collects performance events and alarm information.
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CXLD1
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Provides 10M/100M compatible Ethernet NMS interface, which is present on the AUX board. Provides one 10M/100M Ethernet interface, which is used for inter-board communication and is present on the AUX board. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards and is present on the AUX board. Provides the RS232 OAM interface that is present on the auxiliary interface board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Maintenance feature DCC processing capability Fan alarm management PIU management Protection scheme
Supports the CF card, and supports the package loading function. The capacity is 512 MB and can be expanded to 1 GB. Processes 40-channel DCC. Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU. Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-72 lists the function and feature of the cross-connect unit of the CXLD1. Table 9-72 Function and feature of the cross-connect unit of the CXLD1 Function and Feature Basic function CXLD1 Completes 15 Gbit/s non-blocking full cross-connection at the VC-4 level, and 5 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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Dynamically grooms services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels. Supports VC-4-4c, VC-4-8c and VC-4-16c concatenation services.
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CXLD1 Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-73 lists the function and feature of the clock unit of the CXLD1. Table 9-73 Function and feature of the clock unit of the CXLD1 Function and Feature Basic function Other function CXLD1 Provides standard system synchronization clock. Supports the extraction, insertion and management of the SSM and clock ID. Supports transmitting the DCC overhead information at a twochannel external clock interface. Input and output
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Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
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SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering
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MST
MSA
HPT
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HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/ 100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXLL unit. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-32 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-32 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-16
O/E
DEMUX
RST
16x155 Mbit/s data
MST
MSA
HPT
STM-16
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 15 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 5 G lower order services.
Other Functions
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-33 shows the layout of the J7 jumper and DIP switch SW2 on the CXL board. Figure 9-33 Jumper and DIP switch of the CXL board
Power module
CPU
1 2 3 4
SW2
1 2 3
J7
CF card
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Table 9-74 lists the jumper on the CXL board. Table 9-74 Jumper on the CXL board Jumper J7 Function Enable the battery. Description 1-2: When jumpers 2 and 3 are capped, the battery is enabled.
Table 9-75 lists the DIP switch on the CXL board. Table 9-75 DIP switch on the CXL board DIP Switch SW2 Function Set the board running state. Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer to Table 9-76.
Table 9-76 Description of DIP switch SW2 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
CXLD1
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXLD1, there are one optical interface and two switches. Table 9-77 lists the type and usage of the optical interface and switches on the CXLD1. Table 9-77 Optical interface and switches on the CXLD1 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound.
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Table 9-78 Relation between the board feature code and the optical interface type Board Barcode SSR1CXLD110 SSR1CXLD111 SSR1CXLD112 SSR1CXLD113 SSR1CXLD114 Feature Code 10 11 12 13 14 Optical Interface Type S-1.1 (LC) L-1.1 (LC) L-1.2 (LC) Ve-1.2 (LC) I-1 (LC)
Displayed Slot
The CXLD1 is housed in one slot in the subrack. The logical boards for the CXLD1 are the R1SLD41, RCXL and GSCC. Table 9-79 lists the logical slots displayed on the T2000. Table 9-79 Logical slots displayed on the T2000 for the CXLD1 Board CXLL1 Logical Board R1SLD41 RCXL GSCC Logical Slot Slots 45 Slots 8081 Slots 8283
Board Parameters
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Table 9-80 Specifications for the optical interfaces of the CXLD1 Item Nominal bit rate Line code Optical interface type Working wavelength (nm) Optical source type Mean launched optical power (dBm) Receiver sensitivity (dBm) Min. overload (dBm) Min. extinction ratio (dB) Specification 155520 kbit/s NRZ I-1 1260 to 1360 MLM, LED 15 to 8 S-1.1 1261 to 1360 MLM 15 to 8 L-1.1 1263 to 1360 MLM, SLM 5 to 0 L-1.2 1480 to 1580 SLM 5 to 0 Ve-1.2 1480 to 1580 SLM 3 to 0
23 8 8.2
28 8 8.2
34 10 10
34 10 10
34 10 10
Cross-Connect Capacity
The cross-connect capacity of the CXLD1 is as follows:
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Higher order cross-connect capacity: 15 Gbit/s Lower order cross-connect capacity: 5 Gbit/s Access capacity: 10 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specification for the CXLD1 is as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
At the normal temperature (25), the maximum power consumption for the CXLD1 is 50W.
9.8 CXLD4
This section describes the CXLD4, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.8.1 Version Description The functional version of CXLD4 board is R1. 9.8.2 Function and Feature The CXLD4 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.8.3 Working Principle and Signal Flow The CXLD4 consists of the SDH overhead processing module, RST, MST and so on. 9.8.4 Jumper and DIP Switch On the CXLD4, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.8.5 Front Panel On the front panel of the CXLD4 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.8.6 Valid Slots The CXLD4 can be housed in any of slots 45 in the subrack. 9.8.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXLD4 indicates the optical interface type. 9.8.8 Board Configuration Reference The physical slot that houses the CXLD4 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXLD4. 9.8.9 Technical Specifications The technical specifications for the CXLD4 cover the optical interface specifications, board dimensions, weight and power consumption.
Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports the processing of the VC-12, VC-3, VC-4 services and VC4-4c concatenation services..
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Supports the processing of the SOH bytes of the STM-4 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports multiple protection modes such as two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP..
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Maintenance feature
Supports inloop and outloop for optical interfaces. Supports the warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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SCC Unit
Table 9-82 lists the function and feature of the SCC unit of the CXLD4.
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Table 9-82 Function and feature of the SCC unit of the CXLD4 Function and Feature Basic function Specification of the optical interface CXLD4 Configures and monitors services, monitors the service performance, and collects performance events and alarm information.
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Provides 10M/100M compatible Ethernet NMS interface, which is present on AUX. Provides one 10M/100M Ethernet interface, which is used for inter-board communication and present on AUX board. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards and present on AUX board. Provides the RS232 OAM interface that is present on the AUX board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Maintenance feature DCC processing capability Fan alarm management PIU management Protection scheme
Supports the CF card, and supports the package loading function. The capacity is 512 MB and can be expanded to 1 GB. Processes 40-channel DCC. Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU. Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-83 lists the function and feature of the cross-connect unit of the CXLD4. Table 9-83 Function and feature of the cross-connect unit of the CXLD4 Function and Feature Basic function CXLD4 Completes 15 Gbit/s non-blocking full cross-connection at the VC-4 level, and 5 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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CXLD4
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Dynamically grooms services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels. Supports a maximum of 1024 SNCP protection pairs. Supports VC-4-4c concatenation services.
Protection scheme
Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-84 lists the function and feature of the clock unit of the CXLD4. Table 9-84 Function and feature of the clock unit of the CXLD4 Function and Feature Basic function Other function CXLD4 Provides standard system synchronization clock. Supports the extraction, insertion and management of the SSM and clock ID. Supports transmitting the DCC overhead information at a twochannel external clock interface. Input and output
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Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
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SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering
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MST
MSA
HPT
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HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/ 100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXLL unit. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-36 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-36 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-16
O/E
DEMUX
RST
16x155 Mbit/s data
MST
MSA
HPT
STM-16
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 15 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 5 G lower order services.
Other Functions
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-37 shows the layout of the J7 jumper and DIP switch SW2 on the CXLD4 board. Figure 9-37 Jumper and DIP switch of the CXLD4 board
Power module
CPU
1 2 3 4
SW2
1 2 3
J7
CF card
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Table 9-85 lists the jumper on the CXLD4 board. Table 9-85 Jumper on the CXLD4 board Jumper J7 Function Enable the battery. Description 1-2: When jumpers 2 and 3 are capped, the battery is enabled.
Table 9-86 lists the DIP switch on the CXLD4 board. Table 9-86 DIP switch on the CXLD4 board DIP Switch SW2 Function Set the board running state. Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer to Table 9-87.
Table 9-87 Description of DIP switch SW2 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
CXLD4
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXLD4, there are one optical interface and two switches. Table 9-88 lists the type and usage of the optical interface and switches on the CXLD4. Table 9-88 Optical interface and switches on the CXLD4 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound.
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Table 9-89 Relation between the board feature code and the optical interface type Board Barcode SSR1CXLD410 SSR1CXLD411 SSR1CXLD412 SSR1CXLD413 SSR1CXLD414 Feature Code 10 11 12 13 14 Optical Interface Type S-4.1 (LC) L-4.1 (LC) L-4.2 (LC) Ve-4.2 (LC) I-4 (LC)
Displayed Slot
The CXLD4 is housed in one slot in the subrack. The logical boards for the CXLD4 are the R1SLD41, RCXL and GSCC. Table 9-90 lists the logical slots displayed on the T2000. Table 9-90 Logical slots displayed on the T2000 for the CXLD1 Board CXLD4 Logical Board R1SLD41 RCXL GSCC Logical Slot Slots 45 Slots 8081 Slots 8283
Board Parameters
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Table 9-91 Specifications for the optical interfaces of the CXLD4 Item Nominal bit rate Line code Optical interface type Working wavelength (nm) Optical source type Mean launched optical power (dBm) Receiver sensitivity (dBm) Min. overload (dBm) Min. extinction ratio (dB) Specification 622080 kbit/s NRZ I-4 1260 to 1360 MLM 15 to 8 S-4.1 1274 to 1356 MLM 15 to 8 L-4.1 1280 to 1335 SLM 3 to 2 L-4.2 1480 to 1580 SLM 3 to 2 Ve-4.2 1480 to 1580 SLM 3 to 2
23 8 8.2
28 8 8.2
28 18 10
28 8 10
34 13 10.5
Cross-Connect Capacity
The cross-connect capacity of the CXLD4 is as follows:
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Higher order cross-connect capacity: 15 Gbit/s Lower order cross-connect capacity: 5 Gbit/s Access capacity: 10 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specifications for the CXLD4 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg):1.0kg
Power Consumption
At the normal temperature (25), the maximum power consumption for the CXLD4 is 50W.
9.9 CXLQ1
This section describes the CXLQ1, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.9.1 Version Description The functional version of CXLQ1 board is R1. 9.9.2 Function and Feature The CXLQ1 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.9.3 Working Principle and Signal Flow The CXLQ1 consists of the SDH overhead processing module, RST, MST and so on. 9.9.4 Jumper and DIP Switch On the CXLQ1, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.9.5 Front Panel On the front panel of the CXLQ1 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.9.6 Valid Slots The CXLQ1 can be housed in any of slots 45 in the subrack. 9.9.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXLQ1 indicates the optical interface type. 9.9.8 Board Configuration Reference The physical slot that houses the CXLQ1 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXLQ1. 9.9.9 Technical Specifications The technical specifications for the CXLQ1 cover the optical interface specifications, board dimensions, weight and power consumption.
Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports the processing of the SOH bytes of the STM-1 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports multiple protection modes such as two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP..
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Maintenance feature
Supports inloop and outloop for optical interfaces. Supports the warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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SCC Unit
Table 9-93 lists the function and feature of the SCC unit of the CXLQ1.
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Table 9-93 Function and feature of the SCC unit of the CXLQ1 Function and Feature Basic function Specification of the optical interface CXLQ1 Configures and monitors services, monitors the service performance, and collects performance events and alarm information.
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Provides 10M/100M compatible Ethernet NMS interface, which is present on the AUX board. Provides one 10M/100M Ethernet interface, which is used for inter-board communication and is present on the AUX board. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards and is present on the AUX board. Provides the RS232 OAM interface that is present on the auxiliary interface board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Maintenance feature DCC processing capability Fan alarm management PIU management Protection scheme
Supports the CF card, and supports the package loading function. The capacity is 512 MB and can be expanded to 1 GB. Processes 40-channel DCC. Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU. Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-94 lists the function and feature of the cross-connect unit of the CXLQ1. Table 9-94 Function and feature of the cross-connect unit of the CXLQ1 Function and Feature Basic function CXLQ1 Completes 15 Gbit/s non-blocking full cross-connection at the VC-4 level, and 5 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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CXLQ1
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Dynamically grooms services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels. Supports VC-4-4c, VC-4-8c and VC-4-16c concatenation services.
Protection scheme
Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-95 lists the function and feature of the clock unit of the CXLQ1. Table 9-95 Function and feature of the clock unit of the CXLQ1 Function and Feature Basic function Other function CXLQ1 Provides standard system synchronization clock. Supports the extraction, insertion and management of the SSM and clock ID. Supports transmitting the DCC overhead information at a twochannel external clock interface. Input and output
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Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
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SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering
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MST
MSA
HPT
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HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/ 100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXLL unit. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-40 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-40 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-16
O/E
DEMUX
RST
16x155 Mbit/s data
MST
MSA
HPT
STM-16
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 15 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 5 G lower order services.
Other Functions
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-41 shows the layout of the J7 jumper and DIP switch SW2 on the CXLQ1 board. Figure 9-41 Jumper and DIP switch of the CXLQ1 board
Power module
CPU
1 2 3 4
SW2
1 2 3
J7
CF card
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Table 9-96 lists the jumper on the CXL board. Table 9-96 Jumper on the CXLQ1 board Jumper J7 Function Enable the battery. Description 1-2: When jumpers 2 and 3 are capped, the battery is enabled.
Table 9-97 lists the DIP switch on the CXLQ1 board. Table 9-97 DIP switch on the CXLQ1 board DIP Switch SW2 Function Set the board running state. Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer to Table 9-98.
Table 9-98 Description of DIP switch SW2 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
CXLQ1
Indicators
The following indicators are present on the front panel of the board:
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Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
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For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXLQ1, there are one optical interface and two switches. Table 9-99 lists the type and usage of the optical interface and switches on the CXLQ1. Table 9-99 Optical interface and switches on the CXLQ1 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound.
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Table 9-100 Relation between the board feature code and the optical interface type Board Barcode SSR1CXLQ110 SSR1CXLQ111 SSR1CXLQ112 SSR1CXLQ113 SSR1CXLQ114 Feature Code 10 11 12 13 14 Optical Interface Type S-1.1 (LC) L-1.1 (LC) L-1.2 (LC) Ve-1.2 (LC) I-1 (LC)
Displayed Slot
The CXLQ1 is housed in one slot in the subrack. The logical boards for the CXLQ1 are the R1SLQ41, RCXL and GSCC. Table 9-101 lists the logical slots displayed on the T2000. Table 9-101 Logical slots displayed on the T2000 for the CXLQ1 Board CXLQ1 Logical Board R1SLQ41 RCXL GSCC Logical Slot Slots 45 Slots 8081 Slots 8283
Board Parameters
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Table 9-102 Specifications for the optical interfaces of the CXLQ1 Item Nominal bit rate Line code Optical interface type Working wavelength (nm) Optical source type Mean launched optical power (dBm) Receiver sensitivity (dBm) Min. overload (dBm) Min. extinction ratio (dB) Specification 155520 kbit/s NRZ I-1 1260 to 1360 MLM, LED 15 to 8 S-1.1 1261 to 1360 MLM 15 to 8 L-1.1 1263 to 1360 MLM, SLM 5 to 0 L-1.2 1480 to 1580 SLM 5 to 0 Ve-1.2 1480 to 1580 SLM 3 to 0
23 8 8.2
28 8 8.2
34 10 10
34 10 10
34 10 10
Cross-Connect Capacity
The cross-connect capacity of the CXLQ1 is as follows:
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Higher order cross-connect capacity: 15 Gbit/s Lower order cross-connect capacity: 5 Gbit/s Access capacity: 10 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specification for the CXLQ1 is as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
At the normal temperature (25), the maximum power consumption for the CXLQ1 is 50W.
9.10 CXLQ4
This section describes the CXLQ4, an integrated board of the SCC, cross-connect, clock and line units, in terms of the version, principle, function, principle, front panel and specifications. 9.10.1 Version Description The functional version of CXLQ4 board is R1. 9.10.2 Function and Feature The CXLQ4 is used to process SDH signals, control communication, groom services, and to input and output the clock. 9.10.3 Working Principle and Signal Flow The CXLQ4 consists of the SDH overhead processing module, RST, MST and so on. 9.10.4 Jumper and DIP Switch On the CXLQ4, there are a jumper and a DIP switch, which are used to set the input voltage and running state of the board. 9.10.5 Front Panel On the front panel of the CXLQ4 board, there are indicators, interfaces, barcode, functional button switch, laser safety class label, and CF card slot. 9.10.6 Valid Slots The CXLQ4 can be housed in any of slots 45 in the subrack. 9.10.7 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the CXLQ4 indicates the optical interface type. 9.10.8 Board Configuration Reference The physical slot that houses the CXLD4 is different from the logical slot displayed on the T2000. You can use the T2000 to set parameters for the CXLQ4. 9.10.9 Technical Specifications The technical specifications for the CXLQ4 cover the optical interface specifications, board dimensions, weight and power consumption.
Supports detection and query of the information on the optical module. Supports the function of setting the on/off state of the laser and the ALS function.
Supports the processing of the VC-12, VC-3, VC-4 services and VC4-4c concatenation services..
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Supports the processing of the SOH bytes of the STM-4 signals. Supports the transparent transmission and termination of the POH bytes. Supports the setting and query of the J0/J1/C2 bytes.
Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports multiple protection modes such as two-fiber MSP protection ring, four-fiber MSP protection ring, linear MSP protection, and SNCP..
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Maintenance feature
Supports inloop and outloop for optical interfaces. Supports the warm reset and cold reset. The warm reset does not affect services. Supports the function of querying the manufacturing information of the board. Supports the in-service loading of the FPGA. Supports the upgrade of the board software without affecting services.
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SCC Unit
Table 9-104 lists the function and feature of the SCC unit of the CXLQ4.
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Table 9-104 Function and feature of the SCC unit of the CXLQ4 Function and Feature Basic function Specification of the optical interface CXLQ4 Configures and monitors services, monitors the service performance, and collects performance events and alarm information.
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Provides 10M/100M compatible Ethernet NMS interface, which is present on AUX. Provides one 10M/100M Ethernet interface, which is used for inter-board communication and present on AUX board. Provides one 10M Ethernet interface, which is used for communication between the active and standby SCC boards and present on AUX board. Provides the RS232 OAM interface that is present on the AUX board to connect to the PC or workstation. Supports the remote maintenance by using the RS232 DCE modem. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
Maintenance feature DCC processing capability Fan alarm management PIU management Protection scheme
Supports the CF card, and supports the package loading function. The capacity is 512 MB and can be expanded to 1 GB. Processes 40-channel DCC. Manages fan alarms. Provides the in-service check function for the PIU board, and the failure check function for the lightning protection module of the PIU. Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-105 lists the function and feature of the cross-connect unit of the CXLQ4. Table 9-105 Function and feature of the cross-connect unit of the CXLQ4 Function and Feature Basic function CXLQ4 Completes 15 Gbit/s non-blocking full cross-connection at the VC-4 level, and 5 Gbit/s non-blocking full cross-connection at the VC-12 or VC-3 level. Provides two 4M HDLC fast emergency channels, which are used for the MSP and SNCP protection switching.
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CXLQ4
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Dynamically grooms services. Adds or deletes services without interrupting services. Supports the SNCP protection at the VC-3 and VC-12 levels. Supports a maximum of 1024 SNCP protection pairs. Supports VC-4-4c concatenation services.
Protection scheme
Supports the 1+1 hot backup (non-revertive) for the cross-connect unit.
Clock Unit
Table 9-106 lists the function and feature of the clock unit of the CXLQ4. Table 9-106 Function and feature of the clock unit of the CXLQ4 Function and Feature Basic function Other function CXLQ4 Provides standard system synchronization clock. Supports the extraction, insertion and management of the SSM and clock ID. Supports transmitting the DCC overhead information at a twochannel external clock interface. Input and output
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Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and selects the external timing source. Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
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SETG
155MHz PLL
STM-1
O/E
DEMUX
RST
STM-1 16x155 Mbit/s data
MST
MSA
HPT
O/E
MUX
Performance report
K1/K2 bytes
DCC
Laser control
DCC process
DCC
Line unit
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
Timing signal (T1) from STM-N Timing signal (T2) from PDH Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
T0, system clock (38 MHz) T4, external timing (2 Mbit/s or 2 MHz) output by line
In receive direction, it converts the received optical signals into electrical signals. In transmit direction, it converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. The SPI detects the R_LOS alarm and provides the laser shut down function.
MUX/DEMUX Module
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In receive direction, the DEMUX part demultiplexes the high rate electrical signals into multiple parallel electrical signals, and recovery the clock signal at the same time. In transmit direction, the MUX part multiplexes the parallel electrical signals received from the SDH overhead processing module into high rate electrical signals.
RST
In receiving direction, performs frame alignment detection (A1, A2), regenerator section trace recovery (J0) and mismatch detection, BIP-8 errored block count. In transmitting direction, it performs frame alignment insertion, regenerator section path trace insertion, BIP-8 calculation and insertion. In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI and MS_AIS detection. In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI and MS_AIS insertion. Provides extraction or insertion of K1 byte and K2 byte. In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection, pointer justification. In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS generation. OH termination J1 path trace message recovery REI information recovering
Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd Issue 02 (2007-03-29)
MST
MSA
HPT
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HP_RDI detection (path status monitoring UNEQ and AIS detection (signal label monitoring) VC-4 BIP-8 errored block count
Traces the clock signal from the active and the standby cross-connect unit. Implements laser controlling function. Selects the clock and frame header from the active or the standby cross-connect units. Controls the indicator on the board. CPU control unit, which controls and monitors other function modules. The unit also initializes other function modules after power on. ETH interface, which provides 10/ 100 Mbit/s Ethernet interface for network management. OAM interface, which provides serial port for network management. This port can be used as the MODEM port and thus can be configured as a serial port to connect to MODEM port in running state. COM interface for commissioning port Ethernet port for inter-board communication: 10 Mbit/s Ethernet port between the active and the standby CXLL unit. Supports receiving the BIP-8 check for the overhead of the SCC unit, and provides the interface to query the check result.
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Cross-connect Module
The cross-connect module consists of two parts:
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SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP switching Higher and lower order cross-connect module, which performs the functions of higher and lower order cross-connect units. This module consists of higher order cross-connect unit and lower order cross-connect unit.
Figure 9-44 illustrates the block diagram of higher and lower order cross-connect modules.
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Figure 9-44 Block diagram of higher and lower order cross-connect modules
Time & synchronizaton (SETS) T1 T2 T3 T4(Clock external output) T0 Line units
38MHz OSC
SETG
155MHz PLL
STM-16
O/E
DEMUX
RST
16x155 Mbit/s data
MST
MSA
HPT
STM-16
O/E
MUX
Performance report
K1/K2 bytes
DCC
Cross-connec unit B
Laser control
DCC process
DCC
Line unit
Other unit
Another CXL
AUX AUX
F&f interface
Power monitor
EOW
Boot ROM
FLASH
RAM
NVRAM
DC/DC converter
Fuse
DC/DC converter
The upper half part is the higher order cross-connect unit, which fully cross-connects 15 G higher order services with VC-4 as the minimum service grooming granularity. The lower half part is the lower order cross-connect unit, which cross-connects 5 G lower order services.
Other Functions
l
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Collects performance data of the optical module and shuts output of the optical module Collects and processes DCC of each board Inserts the DCC back into each line board after processing Monitors the power supply of the board Resets the unit Cuts alarms
CF Card
The CF card serves as the storage area of the database, system parameters, NE software package, logs and black box. The capacity is 512 MB and can be expanded to 1 GB.
CAUTION
Jumpers are used for test and maintenance. Do not change the setting of jumpers at random. Otherwise, the board may become faulty. Figure 9-45 shows the layout of the J7 jumper and DIP switch SW2 on the CXLQ4 board. Figure 9-45 Jumper and DIP switch of the CXLQ4 board
Power module
CPU
1 2 3 4
SW2
1 2 3
J7
CF card
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Table 9-107 lists the jumper on the CXLQ4 board. Table 9-107 Jumper on the CXLQ4 board Jumper J7 Function Enable the battery. Description 1-2: When jumpers 2 and 3 are capped, the battery is enabled.
Table 9-108 lists the DIP switch on the CXLQ4 board. Table 9-108 DIP switch on the CXLQ4 board DIP Switch SW2 Function Set the board running state. Description On: indicates the binary value 1. The DIP switch adopts four bits, which are queued according to the switch numbering. The number 4 indicates the highest bit. For details, refer to Table 9-109.
Table 9-109 Description of DIP switch SW2 Value 0b0000 0b0001 0b0011 0b0100 0b1011 0b1100 0b1101 0b1110 0b1111 Description Indicates the running state when the watchdog is started. It is the default state. Changes to the self-test state of the SDRAM Burst. Indicates the commissioning state. Indicates the running state when the watchdog is stopped. Erases the database. Erases the NE software, including the patch. Erases the database and NE software (including the patch). Erases the database, NE software and NE.ini file. Erases the extended BIOS and system parameter zone in the file system and FLASH memory.
CXLQ4
Indicators
The following indicators are present on the front panel of the board:
l l
Board hardware state indicator (STAT), which is green or red when lit. Activating state indicator for the services at the cross-connect unit (ACTX), which is green when lit. Active/standby state indicator for the SCC units (ACTC), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow when lit. Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when lit. Synchronization clock state indicator (SYNC), which is red or green when lit. Alarm cutting indicator (ALMC), which is yellow when lit.
l l l
l l
For indication of these indicators, see A Equipment and Board Alarm Indicators.
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Interfaces
On the front panel of the CXLQ4, there are one optical interface and two switches. Table 9-110 lists the type and usage of the optical interface and switches on the CXLQ4. Table 9-110 Optical interface and switches on the CXLQ4 Interface IN OUT RESET ALM CUT Interface Type LC LC Warm reset switch Alarm cut switch Usage Receives optical signals. The pluggable optical module is used for easy maintenance. Transmits optical signals. The pluggable optical module is used for easy maintenance. Press the switch to reset the SCC unit. Press the switch to mute the alarm. Press the switch for three seconds to mute the alarm permanently. Press the switch again for three seconds to resume the alarm sound.
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Table 9-111 Relation between the board feature code and the optical interface type Board Barcode SSR1CXLQ410 SSR1CXLQ411 SSR1CXLQ412 SSR1CXLQ413 SSR1CXLQ414 Feature Code 10 11 12 13 14 Optical Interface Type S-4.1 (LC) L-4.1 (LC) L-4.2 (LC) Ve-4.2 (LC) I-4 (LC)
Displayed Slot
The CXLQ4 is housed in one slot in the subrack. The logical boards for the CXLQ4 are the R1SLQ41, RCXL and GSCC. Table 9-112 lists the logical slots displayed on the T2000. Table 9-112 Logical slots displayed on the T2000 for the CXLQ1 Board CXLQ4 Logical Board R1SLQ41 RCXL GSCC Logical Slot Slots 45 Slots 8081 Slots 8283
Board Parameters
l l l
Table 9-113 Specifications for the optical interfaces of the CXLQ4 Item Nominal bit rate Line code Optical interface type Working wavelength (nm) Optical source type Mean launched optical power (dBm) Receiver sensitivity (dBm) Min. overload (dBm) Min. extinction ratio (dB) Specification 622080 kbit/s NRZ I-4 1260 to 1360 MLM 15 to 8 S-4.1 1274 to 1356 MLM 15 to 8 L-4.1 1280 to 1335 SLM 3 to 2 L-4.2 1480 to 1580 SLM 3 to 2 Ve-4.2 1480 to 1580 SLM 3 to 2
23 8 8.2
28 8 8.2
28 18 10
28 8 10
34 13 10.5
Cross-Connect Capacity
The cross-connect capacity of the CXLQ4 is as follows:
l l l
Higher order cross-connect capacity: 15 Gbit/s Lower order cross-connect capacity: 5 Gbit/s Access capacity: 10 Gbit/s
External input clock: two channels, 2048 kbit/s or 2048 kHz External output clock: two channels, 2048 kbit/s or 2048 kHz
Mechanical Specifications
The mechanical specifications for the CXLQ4 are as follows:
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Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg):1.0kg
Power Consumption
At the normal temperature (25), the maximum power consumption for the CXLQ4 is 50W.
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10 Auxiliary Boards
10
About This Chapter
Auxiliary Boards
This chapter describes the auxiliary boards, such as the EOW, AUX, AMU, and FANA. 10.1 EOW This section describes the EOW, an orderwire processing board, in terms of the version, function, principle, front panel and specifications. 10.2 AUX This section describes the AUX, a system auxiliary interface board, in terms of the version, function, working principle, front panel and specifications. 10.3 AMU This section describes the AMU, an orderwire processing and alarm concatenation board, in terms of the version, function, principle, front panel and specifications. 10.4 FAN This section describes the FAN, a fan control board, in terms of the version, function, principle, front panel, configuration and specifications.
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10 Auxiliary Boards
10.1 EOW
This section describes the EOW, an orderwire processing board, in terms of the version, function, principle, front panel and specifications. 10.1.1 Version Description The functional version of the EOW is R1. 10.1.2 Function and Feature The EOW is used to extract, insert, and process the overhead bytes E1 and E2, and other data bytes. 10.1.3 Working Principle and Signal Flow The EOW consists of the clock module, switch module, OHP module, and DC/DC converter module. 10.1.4 Front Panel On the front panel of the EOW, there are indicators and interfaces. 10.1.5 Valid Slots The EOW can be housed in slot 9 in the subrack. 10.1.6 Technical Specifications The technical specifications of the EOW cover the board dimensions, weight and power consumption.
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S1~S4 interface
S1~S4
Phone interface
OHP module
E1/E2
Switch module
SLIC
+3.3 V +5 V +1.8 V
+3.3 V
DC/DC converter
Fuse
DC/DC converter
Fuse
Clock Module
The clock module first divides frequencies of the system clock and header sent from the crossconnect board. The system clock and header are then transmitted to other modules as OHP Process module and the switch module.
Switch Module
The switch module performs non-blocking switching of 4096 x 4096 or 1024 x 1024 timeslots under control of micro processor. The switch module can switch any timeslot of overhead signal sent from the SCC to any timeslot of output overhead signals.
OHP Module
l l l l l
Processes E1 and E2 bytes sent by the CXL board. Realizes interconnection between orderwire audio interface. Interconnects with orderwire phone port through SLIC unit. Processes serial1serial4 sent from the CXL board. Provides S1S4 as RS232/RS422 serial transparent data interfaces, the level of which can be set by software.
DC/DC Converter
Through the DC/DC converter module, the power converting module generates required DC voltages for each chip. The following DC voltages are provided: +1.8 V, +3.3 V, +5 V. In addition, protection is provided to board +3.3 V power supply.
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EOW
STAT PROG
PHONE S1 S2 S3 S4
EOW
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Board software state indicator (PROG), which is green or red when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are five interfaces on the front panel of the EOW. Table 10-2 lists the type and usage of these interfaces.
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Table 10-2 Interfaces on the front panel of the EOW Interface PHONE S1 S2 S3 S4 Interface Type RJ-11 RJ-45 RJ-45 RJ-45 RJ-45 Usage Orderwire phone interface Broadcast data interface S1 Broadcast data interface S2 Broadcast data interface S3 Broadcast data interface S4
Table 10-3 lists the pins of the PHONE interface. Table 10-3 Pins of the PHONE interface of the EOW Front View Pin 4 5 13 and 68 Usage Signal 1 Signal 2 Not defined
Table 10-4 lists the pins of the S1, S2, S3 and S4 interfaces. Table 10-4 Pins of the S1, S2, S3 and S4 interfaces of the EOW Front View Pin 1 2 3 4
8 7 6 5 4 3 2 1
Usage RS-422 data transmitting positive RS-422 data transmitting negative RS-422 data receiving positive RS232 data receive end Grounding RS-422 data receiving negative Not defined RS232 data transmit end
5 6 7 8
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Mechanical Specifications
The mechanical specifications of the EOW are as follows:
l l
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.4
Power Consumption
In the normal temperature (25), the maximum power consumption of the EOW is 10 W.
10.2 AUX
This section describes the AUX, a system auxiliary interface board, in terms of the version, function, working principle, front panel and specifications. 10.2.1 Version Description The AUX has two versions, R1 and R2. 10.2.2 Function and Feature The AUX is used to provide various management and auxiliary interfaces, and to provide the central backup of the +3.3 V power supply for the boards in the subrack. 10.2.3 Working Principle and Signal Flow The AUX consists of the control module, communication module, DC/DC converter module and so on. 10.2.4 Front Panel On the front panel of the AUX, there are many types of interfaces. 10.2.5 Valid Slots The AUX can be housed in slot 10 in the subrack. 10.2.6 Technical Specifications The technical specifications of the AUX cover the board dimensions, weight and power consumption.
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Housekeeping input/output
-48 V/ -60 V
Control module
100/10 Mbit/s
2 X 100/10 Mbit/s
CXL
Communication module
100/10 Mbit/s 100/10 Mbit/s Ehernet bus Other unit +3.3 V
+1.8 V
DC/DC converter
DC/DC converter
Fuse
Figure 10-4 shows the block diagram for the functions of the R2AUX.
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Housekeeping input/output
-48 V/ -60 V
Control module
CXL
100/10 Mbit/s
2 x 100/10 Mbit/s
CXL
Communication module
100/10 Mbit/s 100/10 Mbit/s Ehernet bus Other unit -48 V/ -60 V -48 V/ -60 V +3.3 V backup power
+3.3 V +1.8 V
DC/DC converter
DC/DC converter
Fuse
Communication Module
This module applies LAN Switch principle to construct inter-board communication for the OptiX OSN 1500. This module provides:
l
13 x 10/100 Mbit/s FE interfaces (12 for other boards and 1 for the local board) to connect the SCC, the cross-connect, the line and the tributary boards for inter-board communication of the OptiX OSN 1500. 2 x 10/100 Mbit/s FE interfaces on the front panel. One interface is the commissioning network interface for service slots, which forms a VLAN with the 13 inter-board communication network interfaces. The other interface is the interface for network management. 2 x 10/100 Mbit/s FE interfaces to connect network interfaces of the CXLA and the CXLB boards. These two interfaces and one network interface on the front panel are of the same VLAN.
Control Module
The control module mainly consists of CPUs and monitors the running state of the board.
10 Auxiliary Boards
Over-voltage and under-voltage of 48 V and backup +3.3 V powers System lightening protection fault
Other Function
l l l l
F&f interface OAM serial interface for network management Two-in and two-out BITS clock interface (120 ohms) COM, ETH, F&f and OAM interfaces
Communication Module
This module applies LAN Switch principle to construct inter-board communication for the OptiX OSN 1500. This module provides:
l
13 x 10/100 Mbit/s FE interfaces (12 for other boards and 1 for the local board) to connect the SCC, the cross-connect, the line and the tributary boards for inter-board communication of the OptiX OSN 1500. 2 x 10/100 Mbit/s FE interfaces on the front panel. One interface is the commissioning network interface for service slots, which forms a VLAN with the 13 inter-board communication network interfaces. The other interface is the interface for network management. 2 x 10/100 Mbit/s FE interfaces to connect network interfaces of the CXLA and the CXLB boards. These two interfaces and one network interface on the front panel are of the same VLAN.
Control Module
The control module mainly consists of CPLDs and reports the local board state to the CXL board through the control bus with the CXL board. This module also obtains the control information of the local board.
10 Auxiliary Boards
Over-voltage and under-voltage of 48 V and backup +3.3 V powers System lightening protection fault
Other Function
l l l l
F&f interface OAM serial interface for network management Two-in and two-out BITS clock interface (120 ohms) COM, ETH, F&f and OAM interfaces
AUX
Interfaces
There are five interfaces on the front panel of the AUX. Table 10-6 lists the type and usage of these interfaces.
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10 Auxiliary Boards
Table 10-6 Interfaces on the front panel of the AUX Interface ETH COM CLK ALM OAM/F&f Interface Type RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 Usage NM interface Commissioning interface 120-ohm external clock input/output interface 3 x input and 1 x output alarm interface Serial NM and management interface
Table 10-7 lists the pins of the CLK interface. Table 10-7 Pins of the CLK interface of the AUX Front View Pin 1 2 3 4
8 7 6 5 4 3 2 1
Usage Receiving negative for 120-ohm clock 1 Receiving positive for 120-ohm clock 1 Receiving negative for 120-ohm clock 2 Transmitting negative for 120-ohm clock 1 Transmitting positive for 120-ohm clock 1 Receiving positive for 120-ohm clock 2 Transmitting negative for 120-ohm clock 2 Transmitting positive for 120-ohm clock 2
5 6 7 8
Table 10-8 lists the pins of the ETH and COM interfaces. Table 10-8 Pins of the ETH and COM interfaces of the AUX Front View Pin 1 2 3 4
8 7 6 5 4 3 2 1
Usage Transmitting positive Transmitting negative Receiving positive Not defined Not defined Receiving negative
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Front View
Pin 78
Table 10-9 lists the pins of the ALM interface. Table 10-9 Pins of the ALM interface of the AUX Front View Pin 1 2 3
8 7 6 5 4 3 2 1
Usage Positive for critical and major alarm signal output Negative for critical and major alarm signal output Positive for minor and warning alarm signal output Positive for alarm signal output 1 Negative for alarm signal output 1 Negative for minor and warning alarm signal output Positive for alarm signal output 2 Negative for alarm signal output 2
4 5 6 7 8
Controlled by the software, a specific interface can be used as the OAM or F&f interface. Table 10-10 lists pins of the interface used as the OAM interface. Table 10-10 Pins of the OAM interface of the AUX Front View Pin 1 2 3 4
8 7 6 5 4 3 2 1
Usage Requests for transmission. Prepares the DTE. Transmits data. Grounds. Grounds. Receives data. Prepare the DCE. Prepares for the receiving of signals.
5 6 7 8
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Table 10-11 lists the pins of the interface used as the F&f interface. Table 10-11 Pins of the F&f interface of the AUX Front View Pin 4 5 8 13 and 67
8 7 6 5 4 3 2 1
Usage RS232 receive end Grounding end RS232 transmit end Not defined
Mechanical Specifications
The mechanical specifications of the AUX are as follows:
l l
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the AUX is 19 W.
10.3 AMU
This section describes the AMU, an orderwire processing and alarm concatenation board, in terms of the version, function, principle, front panel and specifications. 10.3.1 Version Description The functional version of the AMU board is R1. 10.3.2 Function and Feature The AMU is used to provide various auxiliary, orderwire and broadcast data interfaces for the equipment. 10.3.3 Working Principle and Signal Flow The AMU consists of the clock module, overhead processing module and power supply module. 10.3.4 Front Panel
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10 Auxiliary Boards
On the front panel of AMU, there are board indicators and interfaces of many types. 10.3.5 Valid Slots The AMU can be housed in slot 9 in the subrack. 10.3.6 Technical Specifications The technical specifications of the AMU cover the board dimensions, weight and power consumption.
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Reference clock
CXL unit
S1~S4 E1/E2
CXL unit
-48 V
Clock Module
The clock module extracts and processes the reference clock signals from the CXL.
10 Auxiliary Boards
AMU
STAT PROG
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Board software state indicator (PROG), which is green or red when lit. Connection status indicator (LINK), which is green when lit. Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are five interfaces on the front panel of the AMU. Table 10-13 lists the type and usage of these interfaces. Table 10-13 Interfaces on the front panel of the AMU Interface PHONE
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Usage Broadcast data interface S1 Broadcast data interface S2 Cabinet alarm indicator output interface Cabinet concatenated alarm indicator input interface
Table 10-14 lists the pins of the PHONE interface. Table 10-14 Pins of the PHONE interface of the AMU Front View Pin 4 5 13 and 68 Usage Signal 1 Signal 2 Not defined
Table 10-15 lists the pins of the S1 and S2 interfaces. Table 10-15 Pins of the S1 and S2 interfaces of the AMU Front View Pin 1 2 3
8 7 6 5 4 3 2 1
Usage RS-422 data transmitting positive RS-422 data transmitting negative RS-422 data receiving positive RS232 data receive end Grounding RS-422 data receiving negative Not defined RS232 data transmit end
4 5 6 7 8
Table 10-16 lists the pins of the LAMP1 and LAMP2 interfaces.
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Table 10-16 Pins of the LAMP1 and LAMP2 interfaces of the AMU Front View Pin 1 2 3
8 7 6 5 4 3 2 1
Usage Positive for critical alarm signals Negative for critical alarm signals Positive for major alarm signals Positive for power indicator signals Negative for power indicator signals Negative for major alarm signals Positive for minor alarm signals Negative for minor alarm signals
4 5 6 7 8
Subrack 2
LAMP1 LAMP2
Subrack 1 Cabinet
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Mechanical Specifications
The mechanical specifications of the AMU are as follows:
l l
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 0.5
Power Consumption
In the normal temperature (25), the maximum power consumption of the AMU is 8 W.
10.4 FAN
This section describes the FAN, a fan control board, in terms of the version, function, principle, front panel, configuration and specifications. 10.4.1 Version Description The functional version of the FAN board is R1. 10.4.2 Function and Feature The FAN is used to adjust the fan speed, check the fan status, report the fault of the fan control board, and to report the off-service alarm of the fan. 10.4.3 Working Principle and Signal Flow The FAN consists of the power interface unit, soft start unit, state detecting unit and fans. 10.4.4 Front Panel There are no indicators on the front panel of the FAN. 10.4.5 Valid Slots The FAN can be housed in slot 20 in the subrack. 10.4.6 Technical Specifications The technical specifications of the FAN cover the board dimensions, weight, power consumption and working voltage.
10 Auxiliary Boards
Table 10-17 Functions and features of the FAN Function and Feature Hot swap function Status check function Alarm check function FAN Provides the hot swap function for the fan frame. Provides the function of fan status check. Reports the fan alarm and in-service information.
- 48 V
48 V
GND
- 48 V
GND
10 Auxiliary Boards
One OptiX OSN 1500 subrack uses one fan tray assembly. Figure 10-11 shows the appearance of the front panel of the FAN. Figure 10-11 Front panel of the FAN
FAN
RUN ALM
Indicators
The following indicators are present on the front panel of the board:
l l
Board running state (RUN), which is green when lit. Fan alarm indicator (ALM), which is red when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Mechanical Specifications
The mechanical specifications of the FAN are as follows:
l l
Board dimensions (mm): 120 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25) and with 48 V input voltage, the maximum power consumption of the FAN is 20 W.
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Working Voltage
The working voltage for the FAN can be 48 V20% DC.
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11
About This Chapter
This chapter describes the WDM processing boards, such as the CMR2, CMR4, MR2, MR2A, MR2B, MR2C, MR4, LWX, OBU1, and FIB. 11.1 CMR2 This section describes the TN11CMR2, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.2 CMR4 This section describes the TN11CMR4, a four-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.3 MR2 This section describes the TN11MR2, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.4 MR2A This section describes the MR2A, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.5 MR2B This section describes the MR2B, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.6 MR2C This section describes the MR2C, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.7 MR4 This section describes the TN11MR4, a four-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.8 LWX This section describes the LWX, an arbitrary rate wavelength converting board, in terms of the version, function, principle, front panel, configuration and specifications. 11.9 OBU1
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This section describes the TN11OBU1, an optical booster amplifier board, in terms of the version, function, principle, front panel, configuration and specifications. 11.10 FIB This section describes the FIB, a wavelength filter and isolation board, in terms of the version, function, principle, front panel, configuration and specifications.
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11.1 CMR2
This section describes the TN11CMR2, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.1.1 Version Description The functional version of the CMR2 board is TN11. 11.1.2 Function and Feature The CMR2 is used to the dense wavelength division multiplexing (DWDM) system. The spacing wavelength is 20 nm. The CMR2 supports functions and features such as add/drop multiplexing and channel expansion. 11.1.3 Working Principle and Signal Flow The CMR2 consists of the OADM optical module, control and communication module, and DC/ DC converter module. 11.1.4 Front Panel On the front panel of the CMR2, there are board indicators, interfaces and laser safety class label. 11.1.5 Valid Slots The CMR2 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, or any of slots 1113 in the OptiX OSN 1500B subrack. 11.1.6 Board Feature Code The board feature code of the CMR2 contains eight characters, which indicate the wavelengths for the 2-channel optical signals processed by the board. 11.1.7 Technical Specifications The technical specifications of the CMR2 cover the optical interface specifications, board dimensions, weight, power consumption and laser safety class.
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CMR2 Provides the intermediate port used for expansion. Under certain conditions, the capacity of upstream and downstream channels can be expanded when the intermediate port is connected to other optical add/drop multiplexing boards.
IN
Add
OUT
Back plane
-48 V/-60 V
-48 V/-60 V
SCC
The CMR2 mainly includes the optical add/drop multiplexer (OADM) module adding/dropping two channels of signals. The OADM adds/drops and multiplexes two channels of signals. It also provides concatenation interfaces to connect other add/drop multiplexing boards for more powerful add/drop capability. The CMR2 is a passive board that has no interface with the backplane.
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OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths from the signal. These two dropped wavelengths are output from the MO optical interface. The MI optical interface receives one multiplexed signal that travels over the main optical path. The Add optical module adds two wavelengths through optical interfaces A01 and A02 and multiplexes them with the signal in the main optical path into one signal. This multiplexed signal is output through OUT.
Controls the entire board operation. Collects the information, such as the alarms and performance events, working status, and voltage detection, of each functional module of the board. Communicates data with the SCC.
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CMR2
STAT
LASER RADIATION
DO NOT VIEW DIRECTLY WITH OPTICAL INSTRUMENTS
OUT IN MO MI D1 A1 D2 A2
CMR2
Indicator
On the front panel of the CMR2, there is one board hardware state indicator (STAT), which is red or green when lit. For indication of the indicator, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight optical interfaces on the front panel of the CMR2. Table 11-2 lists the type and usage of the optical interfaces.
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Table 11-2 Optical interfaces of the CMR2 Interface A1A2 D1D2 IN OUT MO MI Interface Type LC LC LC LC LC LC Usage Receive the signals output from the optical wavelength converting board or centralized client-side equipment. Transmit signals to the optical wavelength converting board or centralized client-side equipment. Receives multiplexed signals. Transmits multiplexed signals. Acts as a concatenation output optical interface and connects to the input optical interfaces of other OADM boards. Acts as a concatenation input optical interface and connects to the output optical interfaces of other OADM boards.
"1471" indicates that the wavelength for the first channel of optical signals is 1471 nm. "1571" indicates that the wavelength for the second channel of optical signals is 1571 nm.
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Mechanical Specifications
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.8
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Power Consumption
l
In the normal temperature (25), the maximum power consumption of the CMR2 is 0.2 W. In the high temperature (55), the maximum power consumption of the CMR2 is 0.3 W.
11.2 CMR4
This section describes the TN11CMR4, a four-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.2.1 Version Description The functional version of the CMR4 board is TN11. 11.2.2 Function and Feature The CMR4 is used to dense wavelength division multiplexing (DWDM) system. The spacing wavelength is 20 nm. The CMR4 supports functions and features such as add/drop multiplexing and channel expansion. 11.2.3 Working Principle and Signal Flow The CMR4 consists of the OADM optical module, control and communication module, and DC/ DC converter module. 11.2.4 Front Panel On the front panel of the CMR4, there are board indicators, interfaces and laser safety class label. 11.2.5 Valid Slots The CMR4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, or any of slots 1113 in the OptiX OSN 1500B subrack. 11.2.6 Board Feature Code The board feature code of the CMR4 contains eight characters, which indicate the wavelengths for the 4-channel optical signals processed by the board. 11.2.7 Technical Specifications The technical specifications of the CMR4 cover the optical interface specifications, board dimensions, weight, power consumption and laser safety class.
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Table 11-5 Functions and features of the CMR4 Function and Feature Basic function Channel expansion CMR4 Adds/Drops four wavelengths to/from the multiplexed signals. Provides the intermediate port used for expansion. Under certain conditions, the capacity of upstream and downstream channels can be expanded when the intermediate port is connected to other optical add/drop multiplexing boards.
IN
Add
OUT
Back plane
-48 V/-60 V
-48 V/-60 V
SCC
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream station. The Drop optical module drops through optical interfaces D01D04 four wavelengths from the signal. These four dropped wavelengths are output from the MO optical interface. The MI optical interface receives one multiplexed signal that travels over the main optical path. The Add optical module adds four wavelengths through optical interfaces A01A04 and
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multiplexes them with the signal in the main optical path into one signal. This multiplexed signal is output through OUT.
Controls the entire board operation. Collects the information, such as the alarms and performance events, working status, and voltage detection, of each functional module of the board. Communicates data with the SCC.
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CMR4
STAT
LASER RADIATION
DO NOT VIEW DIRECTLY WITH OPTICAL INSTRUMENTS
OUT IN MO MI D1 A1 D2 A2 D3 A3 D4 A4
CMR4
Indicator
One the front panel of the CMR4, there is one board hardware state indicator (STAT), which is red or green when lit. For indication of the indicator, see A Equipment and Board Alarm Indicators.
Interfaces
There are twelve optical interfaces on the front panel of the CMR4. Table 11-6 lists the type and usage of these optical interfaces.
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Table 11-6 Optical interfaces of the CMR4 Interface A1A4 D1D4 IN OUT MI Interface Type LC LC LC LC LC Usage Receive the signals output from the optical wavelength converting board or centralized client-side equipment. Transmit signals to the optical wavelength converting board or centralized client-side equipment. Receives multiplexed signals. Transmits multiplexed signals. Acts as a concatenation input optical interface and connects to the output optical interfaces of other OADM boards. Acts as a concatenation output optical interface and connects to the input optical interfaces of other OADM boards.
MO
LC
Characters 34
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Barcode Characters 56
Description The characters are two middle characters of the four that indicate the wavelength for the third channel of optical signals. The characters are two middle characters of the four that indicate the wavelength for the fourth channel of optical signals.
Characters 78
"47" indicates that the wavelength for the first channel of optical signals is 1471 nm. "49" indicates that the wavelength for the second channel of optical signals is 1491 nm. "59" indicates that the wavelength for the third channel of optical signals is 1591 nm. "61" indicates that the wavelength for the fourth channel of optical signals is 1611 nm.
> 25
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Optical Interface
0.5 dB passband bandwidth (nm) Insertion loss (dB) in the channel for adding wavelengths Insertion loss (dB) Isolation (dB) Return loss (dB)
Mechanical Specifications
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.9
Power Consumption
l
In the normal temperature (25), the maximum power consumption of the CMR4 is 0.2 W. In the high temperature (55), the maximum power consumption of the CMR4 is 0.3 W.
11.3 MR2
This section describes the TN11MR2, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.3.1 Version Description The functional version of the MR2 board is TN11. 11.3.2 Function and Feature The MR2 is used to the dense wavelength division multiplexing (DWDM) system. The spacing wavelength is 0.8 nm. The MR2 supports functions and features such as add/drop multiplexing and channel expansion. 11.3.3 Working Principle and Signal Flow The MR2 consists of the OADM optical module, control and communication module, and DC/ DC converter module. 11.3.4 Front Panel
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On the front panel of the MR2, there are board indicators, interfaces and laser safety class label. 11.3.5 Valid Slots The MR2 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, or any of slots 1113 in the OptiX OSN 1500B subrack. 11.3.6 Board Feature Code The board feature code of the MR2 contains eight characters, which indicate the frequency for the 2-channel optical signals processed by the board. 11.3.7 Technical Specifications The technical specifications of the MR2 cover the optical interface specifications, board dimensions, weight, power consumption and laser safety class.
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IN
Add
OUT
Back plane
-48 V/-60 V
-48 V/-60 V
SCC
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths from the signal. These two dropped wavelengths are output from the MO optical interface. The MI optical interface receives one multiplexed signal that travels over the main optical path. The Add optical module adds two wavelengths through optical interfaces A01 and A02 and multiplexes them with the signal in the main optical path into one signal. This multiplexed signal is output through OUT.
Controls the entire board operation. Collects the information, such as the alarms and performance events, working status, and voltage detection, of each functional module of the board. Communicates data with the SCC.
MR2
STAT
LASER RADIATION
DO NOT VIEW DIRECTLY WITH OPTICAL INSTRUMENTS
OUT IN MO MI D1 A1 D2 A2
MR2
Indicator
On the front panel of the MR2, there is one board hardware state indicator (STAT), which is red or green when lit. For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight optical interfaces on the front panel of the MR2. Table 11-10 lists the type and usage of the optical interfaces.
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Table 11-10 Optical interfaces of the MR2 Interface A1A2 D1D2 IN OUT MO Interface Type LC LC LC LC LC Usage Receive the signals output from the optical wavelength converting board or centralized client-side equipment. Transmit signals to the optical wavelength converting board or centralized client-side equipment. Receives multiplexed signals. Transmits multiplexed signals. Acts as a concatenation output optical interface and connects to the input optical interfaces of other OADM boards. Acts as a concatenation input optical interface and connects to the output optical interfaces of other OADM boards.
MI
LC
"9360" indicates that the frequency of the first channel of optical signals is 193.60 THz. "9370" indicates that the frequency of the second channel of optical signals is 193.70 THz.
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Mechanical Specifications
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.9
Power Consumption
l l
In the normal temperature (25), the maximum power consumption of the MR2 is 0.2 W. In the high temperature (55), the maximum power consumption of the MR2 is 0.3 W.
11.4 MR2A
This section describes the MR2A, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.4.1 Version Description The functional version of the MR2A board is N1. 11.4.2 Function and Feature The MR2A is used to the dense wavelength division multiplexing (DWDM) system. The spacing wavelength is 0.8 nm. The MR2A supports functions and features such as add/drop multiplexing, channel expansion and query of wavelengths. 11.4.3 Working Principle and Signal Flow The MR2A consists of the OADM module, control and communication module, and DC/DC converter module. 11.4.4 Front Panel On the front panel of the MR2A, there are interfaces and laser safety class label. 11.4.5 Valid Slots The MR2A can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, or any of slots 1113 in the OptiX OSN 1500B subrack. 11.4.6 Technical Specifications The technical specifications of the MR2A cover the optical interface specifications, board dimensions, weight, power consumption and laser safety class.
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Table 11-13 Functions and features of the MR2A Function and Feature Basic function MR2A Adds/Drops two arbitrary adjacent wavelengths, which are compliant with ITU-T G.692 (DWDM). The signals are transparently transmitted, and the working wavelength ranges from 1535.82 nm to 1560.61 nm. The MR2A can be used as the two-channel wavelength adding/ dropping OTM station. Two MR2C boards can be concatenated and upgraded to the four-channel wavelength adding/dropping OTM station. See Figure 11-7. Realizes the two-channel wavelength adding/dropping OADM station, when used with the LWX. See Figure 11-8. Supports the ITU-T-compliant standard wavelength with a channel spacing of 100 GHz.
OTM function
IN OUT
MO IN MI OUT
MO IN MI OUT MR2A
Drop Add
MO
MI
A1
(2)
A2
(1) (2)
MR2A can serve as an OTM station adding/dropping two channels. Two MR2A boards connected in serial can serve as an OTM station adding/dropping four channels.
Figure 11-8 MR2A and LWX used as the two-channel wavelength adding/dropping OADM station
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IN
Add
OUT
Back plane
-48 V/-60 V
-48 V/-60 V
SCC
The MR2A mainly includes the optical add/drop multiplexer (OADM) module adding/dropping two channels of signals. The OADM adds/drops and multiplexes two channels of signals. It also provides concatenation interfaces to connect other add/drop multiplexing boards for more powerful add/drop capability. The MR2A is a passive board that has no interface with the backplane.
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths from the signal. These two dropped wavelengths are output from the MO optical interface. The MI optical interface receives one multiplexed signal that travels over the main optical path. The Add optical module adds two wavelengths through optical interfaces A01 and A02 and multiplexes them with the signal in the main optical path into one signal. This multiplexed signal is output through OUT.
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Controls the entire board operation. Collects the information, such as the alarms and performance events, working status, and voltage detection, of each functional module of the board. Communicates data with the SCC.
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Interfaces
There are four pairs of LC optical interfaces on the front panel of the MR2A. Table 11-14 lists the type and usage of the optical interfaces. Table 11-14 Optical interfaces of the MR2A Interface A01A02 D01D02 IN OUT MO/MI Interface Type LC LC LC LC LC Usage Adds two wavelengths of signals from the local. Drops two wavelengths of signals to the local. Receives multiplexed signals of two wavelengths. Transmits multiplexed signals of two wavelengths. Acts as a concatenation optical interface and concatenates several MR2A boards.
Line code Channel spacing (GHz) Insertion loss (dB) in the channel for adding or dropping wavelengths Adjacent channel isolation (dB)
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> 25
11-25
Mechanical Specifications
The mechanical specifications of the MR2A are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the MR2A does not consume power.
11.5 MR2B
This section describes the MR2B, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.5.1 Version Description The functional version of the MR2B board is N1. 11.5.2 Function and Feature The MR2B is used to the dense wavelength division multiplexing (DWDM) system. The spacing wavelength is 0.8 nm. The MR2B supports functions and features such as add/drop multiplexing, channel expansion and query of wavelengths. 11.5.3 Working Principle and Signal Flow The MR2B consists of the OADM module, control and communication module, and DC/DC converter module. 11.5.4 Front Panel On the front panel of the MR2B, there are interfaces and laser safety class label. 11.5.5 Valid Slots The MR2B can be housed in any of slots 23, 69, and 1213 in the OptiX OSN 1500A subrack, or any of slots 13, 69, and 1113 in the OptiX OSN 1500B subrack. 11.5.6 Technical Specifications The technical specifications of the MR2B cover the optical interface specifications, board dimensions, weight, power consumption and laser safety class.
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OTM function
IN OUT
MO IN MI OUT
MO IN MI OUT MR2B
Drop Add
MO
MI
A1
(2)
A2
(1) MR2B can serve as an OTM station adding/dropping two channels. (2) Two MR2B boards connected in serial can serve as an OTM station adding/dropping four channels.
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Figure 11-12 MR2B and LWX used as the two-channel wavelength adding/dropping OADM station
IN
Add
OUT
Back plane
-48 V/-60 V
-48 V/-60 V
SCC
The MR2B mainly includes the optical add/drop multiplexer (OADM) module adding/dropping two channels of signals. The OADM adds/drops and multiplexes two channels of signals. It also
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provides concatenation interfaces to connect other add/drop multiplexing boards for more powerful add/drop capability. The MR2B is a passive board that has no interface with the backplane.
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths from the signal. These two dropped wavelengths are output from the MO optical interface. The MI optical interface receives one multiplexed signal that travels over the main optical path. The Add optical module adds two wavelengths through optical interfaces A01 and A02 and multiplexes them with the signal in the main optical path into one signal. This multiplexed signal is output through OUT.
Controls the entire board operation. Collects the information, such as the alarms and performance events, working status, and voltage detection, of each functional module of the board. Communicates data with the SCC.
MR2B
CLASS 1 LASER PRODUCT
MR2B
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Interfaces
There are four pairs of optical interfaces on the front panel of the MR2B. Table 11-17 lists the type and usage of the optical interfaces. Table 11-17 Optical interfaces of the MR2B Interface A01A02 D01D02 IN OUT MO/MI Interface Type LC LC LC LC LC Usage Adds two wavelengths of signals from the local. Drops two wavelengths of signals to the local. Receives multiplexed signals of two wavelengths. Transmits multiplexed signals of two wavelengths. Acts as a concatenation optical interface and concatenates several MR2B boards.
Line code Channel spacing (GHz) Insertion loss in the wavelength-adding channel (dB) Adjacent channel isolation (dB)
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Mechanical Specifications
The mechanical specifications of the MR2B are as follows:
l l
Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W) Weight (kg): 1.0
Power Consumption
In the normal temperature (25), the MR2B does not consume power.
11.6 MR2C
This section describes the MR2C, a dual-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.6.1 Version Description The functional version of the MR2C board is N1. 11.6.2 Function and Feature The MR2C is used to the dense wavelength division multiplexing (DWDM) system. The spacing wavelength is 0.8 nm. The MR2C supports functions and features such as add/drop multiplexing, channel expansion and query of wavelengths. 11.6.3 Working Principle and Signal Flow The MR2C consists of the OADM module, control and communication module, and DC/DC converter module. 11.6.4 Front Panel On the front panel of the MR2C, there are interfaces and laser safety class label. 11.6.5 Valid Slots The MR2C can be housed in any of slots 1417 in the OptiX OSN 1500B subrack.The MR2C can be housed in any of slots 1926 and 2936 in the subrack. If an extended subrack is used, the MR2C can also be housed in any of slots 6976 and 7986. 11.6.6 Technical Specifications The technical specifications of the MR2C cover the optical interface specifications, board dimensions, weight, power consumption and laser safety class.
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OTM function
IN OUT
MO IN MI OUT
MO IN MI OUT MR2C
Drop Add
MO
MI
A1
(2)
A2
(1) MR2C can serve as an OTM station adding/dropping two channels. (2) Two MR2C boards connected in serial can serve as an OTM station adding/dropping four channels.
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Figure 11-16 Two-channel wavelength adding/dropping OADM station realized by the MR2C and LWX
IN
Add
OUT
Back plane
-48 V/-60 V
-48 V/-60 V
SCC
The MR2C mainly includes the optical add/drop multiplexer (OADM) module adding/dropping two channels of signals. The OADM adds/drops and multiplexes two channels of signals. It also
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provides concatenation interfaces to connect other add/drop multiplexing boards for more powerful add/drop capability. The MR2C is a passive board that has no interface with the backplane.
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths from the signal. These two dropped wavelengths are output from the MO optical interface. The MI optical interface receives one multiplexed signal that travels over the main optical path. The Add optical module adds two wavelengths through optical interfaces A01 and A02 and multiplexes them with the signal in the main optical path into one signal. This multiplexed signal is output through OUT.
Controls the entire board operation. Collects the information, such as the alarms and performance events, working status, and voltage detection, of each functional module of the board. Communicates data with the SCC.
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Interfaces
There is four pairs of optical interfaces on the front panel of the MR2C. Table 11-20 lists the type and usage of the optical interfaces. Table 11-20 Optical interfaces of the MR2C Interface A01A02 D01D02 IN OUT MO/MI Interface Type LC LC LC LC LC Usage Adds two wavelengths of signals from the local. Drops two wavelengths of signals to the local. Receives multiplexed signals of two wavelengths. Transmits multiplexed signals of two wavelengths. Acts as a concatenation optical interface and concatenates several MR2C boards.
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Line code Channel spacing (GHz) Insertion loss in the add/ drop channel (dB) Adjacent channel isolation (dB) Non-adjacent channel isolation (dB) 0.5 dB channel bandwidth (nm)
Mechanical Specifications
The mechanical specifications of the MR2C are as follows:
l l
Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W) Weight (kg): 1.0
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Power Consumption
In the normal temperature (25), the MR2C does not consume power.
11.7 MR4
This section describes the TN11MR4, a four-channel optical add/drop multiplexing board, in terms of the version, function, principle, front panel, configuration and specifications. 11.7.1 Version Description The functional version of the MR4 board is TN11. 11.7.2 Function and Feature The MR4 is used to the dense wavelength division multiplexing (DWDM) system. The spacing wavelength is 0.8 nm. The MR4 supports functions and features such as add/drop multiplexing and channel expansion. 11.7.3 Working Principle and Signal Flow The MR4 consists of the OADM optical module, control and communication module, and DC/ DC converter module. 11.7.4 Front Panel On the front panel of the MR4, there are board indicators, interfaces and laser safety class label. 11.7.5 Valid Slots The MR4 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, or any of slots 1113 in the OptiX OSN 1500B subrack. 11.7.6 Board Feature Code The feature code of the MR4 has eight numbers, which identify the frequency of the first and fourth channels of optical signals the board process. 11.7.7 Technical Specifications The technical specifications of the MR4 cover the optical interface specifications, board dimensions, weight, power consumption and laser safety class.
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MR4 Provides the intermediate port used for expansion. Under certain conditions, the capacity of upstream and downstream channels can be expanded when the intermediate port is connected to other optical add/drop multiplexing boards.
IN
Add
OUT
Back plane
-48 V/-60 V
-48 V/-60 V
SCC
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream station. The Drop optical module drops through optical interfaces D01D04 four wavelengths from the signal. These four dropped wavelengths are output from the MO optical interface. The MI optical interface receives one multiplexed signal that travels over the main optical path. The Add optical module adds four wavelengths through optical interfaces A01A04 and multiplexes them with the signal in the main optical path into one signal. This multiplexed signal is output through OUT.
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Controls the entire board operation. Collects the information, such as the alarms and performance events, working status, and voltage detection, of each functional module of the board. Communicates data with the SCC.
MR4
STAT
LASER RADIATION
DO NOT VIEW DIRECTLY WITH OPTICAL INSTRUMENTS
OUT IN MO MI D1 A1 D2 A2 D3 A3 D4 A4
MR4
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Indicator
On the front panel of the MR4, there is one board hardware state indicator (STAT), which is red or green when lit. For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are twelve optical interfaces on the front panel of the MR4. Table 11-23 lists the type and usage of the optical interfaces. Table 11-23 Optical interfaces of the MR4 Interface A1A4 D1D4 IN OUT MI Interface Type LC LC LC LC LC Usage Receive the signals output from the optical wavelength converting board or centralized client-side equipment. Transmit signals to the optical wavelength converting board or centralized client-side equipment. Receives multiplexed signals. Transmits multiplexed signals. Acts as a concatenation input optical interface and connects to the output optical interfaces of other OADM boards. Acts as a concatenation output optical interface and connects to the input optical interfaces of other OADM boards.
MO
LC
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Table 11-24 Board feature code Barcode First four characters Indication Frequency of optical signals Description The four characters are the last four characters of the figure that marks the frequency of the first channel of optical signals. The four characters are the last four characters of the figure that marks the frequency of the fourth channel of optical signals.
"9210" indicates that the frequency of the first channel of optical signals is 192.10 THz. "9240" indicates that the frequency of the fourth channel of optical signals is 192.40 THz.
The four channels of optical signals the MR4 processes are successive:
l l
The frequency of the second channel of optical signals is 192.20 THz. The frequency of the third channel of optical signals is 192.30 THz.
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Optical Interface
0.5 dB passband bandwidth (nm) Insertion loss in the wavelength-adding channel (dB) Insertion loss (dB) Isolation (dB) Return loss (dB)
Mechanical Specifications
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.9
Power Consumption
l l
In the normal temperature (25), the maximum power consumption of the MR4 is 0.2 W. In the high temperature (55), the maximum power consumption of the MR4 is 0.3 W.
11.8 LWX
This section describes the LWX, an arbitrary rate wavelength converting board, in terms of the version, function, principle, front panel, configuration and specifications. 11.8.1 Version Description The functional version of the LWX board is N1. 11.8.2 Function and Feature The LWX is used to realize the convertion between the wavelength at an arbitrary rate (10 Mbit/ s to 2.7 Gbit/s, NRZ code) at the client side and the G.692 wavelength. 11.8.3 Working Principle and Signal Flow The LWX consists of the O/E conversion module, cross-connect module, CDR module and so on.
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11.8.4 Front Panel On the front panel of the LWX, there are indicators and interfaces. 11.8.5 Valid Slots The LWX can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, or any of slots 1113 in the OptiX OSN 1500B subrack. 11.8.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The feature code of the LWX indicates the schemes the optical interfaces use to receive and transmit signals. 11.8.7 Technical Specifications The technical specifications of the LWX cover the optical interface specifications, board dimensions, weight and power consumption.
Supports the ALS function. When no signals are received, the corresponding optical transmit module is automatically turned off. Provides the inloop and outloop at the optical interface level, which are used for locating faults.
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LWX Provides rich alarms and performance events for easy maintenance.
Supports the ITU-T-compliant standard wavelength with a channel spacing of 100 GHz.
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O/ E
22 Crossconnection
Multi-rate CDR
O/ E
LOS
10 Mbit/s~2.7 Gbit/s
O/ E
2 2 Crossconnection
Multi-rate CDR
Loopback control
Reference clock
O/ E
Clock
Optical splitter
O/ E
Data
Communication
SCC Unit
Fuse
Fuse
The optical module at client side applies SFP encapsulation and can be configured as different types of optical module. This module supports accessing optical signals at the rate of 10 Mbit/s-2.7 Gbit/s. At WDM side, the module can be configured as an optical tranceiver module or an optical tranceiver module and an optical receiver module. When two modules are configured at WDM side, an optical splitter is used to realize dual feeding. In the receive direction, the module converts the received optical signals into electrical signals.
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In the transmit direction, the module converts the electrical signals into SDH optical signals, and then send optical signals to fibers for transmission. Detect the R_LOS alarm and provide the function to shut down the laser.
Cross-connect Module
l l l l
Supports data selection from client side to WDM side and from WDM side to client side Supports WDM side optical module selection Supports loopback of client side signals Supports loopback of WDM side signals
CDR Module
l l
Supports recovering data and clock signals from 10 Mbit/s to 2.7 Gbit/s Supports reading rates of accessed services
Supports Ethernet communication Supports reference clock of the CDR module Selects and configures services of other modules Implements laser controlling function Selects the clock from the active or the standby cross-connect board Control the indicator on the board
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LWX
STAT ACT PROG SRV
CLASS 1 LASER PRODUCT
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are six optical interfaces on the front panel of the LWX. Table 11-27 lists the type and usage of the optical interfaces.
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Table 11-27 Optical interfaces on the front panel of the LWX Interface IN1/IN2 OUT1/OUT2 TX RX Interface Type LC LC LC LC Usage Receives signals from the optical add/drop multiplexing board, MR2A. Transmits signals to the optical add/drip multiplexing board, MR2A. Transmits signals to the client-side equipment. Receives signals from the client-side equipment.
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Table 11-29 Specifications of the client-side optical interfaces of the LWX Item Nominal bit rate Line code Optical source type Transmission distance (km) Specification 10 Mbit/s to 2.7 Gbit/s NRZ SLM 15 SLM 40 SLM 80
Feature of the transmitter at S point Working wavelength range (nm) Max. mean launched optical power (dBm) Min. mean launched optical power (dBm) Min. extinction ratio (dB) Side mode suppression ratio (dB) Eye pattern 1260 to 1360 0 5 +8.2 30 1260 to 1360 +3 2 +8.2 30 1500 to 1580 +3 2 +8.2 30
Feature of the receiver at S point Receiver type Wavelength range (nm) of the received signals Receiver sensitivity (dBm) Min. overload (dBm) Max. reflection coefficient (dB) PIN 1200 to 1600 PIN 1200 to 1600 APD 1200 to 1600
18 0 27
18 9 27
28 9 27
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Table 11-30 Specifications of the WDM-side optical interfaces of the LWX Item Channel spacing (GHz) Line code Specification 100 NRZ
Feature of the transmitter at Sn point Target transmission distance (km) of optical interfaces Max. mean launched optical power (dBm) Min. mean launched optical power (dBm) Min. extinction ratio (dB) Nominal central frequency (THz) Central frequency deviation (GHz) Max. 20 dB spectral width (nm) Min. side mode suppression ratio (dB) Dispersion compensation (ps/nm) Eye pattern 640 170 (2 mW) 170 (10 mW) 360
+7
+3
+3
+5
+3
0.2
0.4
0.4
0.4
35
35
35
35
12800
2400
3200
1600
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Item Receiver type Receiving wavelength range (nm) Receiver sensitivity (dBm) Min. overload (dBm) Max. reflection coefficient (dB)
28
18
9 27
0 27
Mechanical Specifications
The mechanical specifications of the LWX are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.1
Power Consumption
In the normal temperature (25), the maximum power consumption of the LWX is 30 W.
11.9 OBU1
This section describes the TN11OBU1, an optical booster amplifier board, in terms of the version, function, principle, front panel, configuration and specifications. 11.9.1 Version Description The functional version of the OBU1 is TN11. 11.9.2 Function and Feature The OBU1 supports the in-service optical performance monitoring, gain-locking technology, and transient control technology. 11.9.3 Working Principle and Signal Flow The OBU1 consists of the EDFA optical module, optical splitter, and the control and communication module. 11.9.4 Front Panel On the front panel of the OBU1, there are indicators, interfaces, and laser safety class label. 11.9.5 Valid Slots The OBU1 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, or any of slots 1113 in the OptiX OSN 1500B subrack. 11.9.6 Board Feature Code
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The feature code of the OBU1 contains six characters and indicates the gain and maximum nominal input optical power of the optical signals. 11.9.7 Technical Specifications The technical specifications of the OBU1 cover the optical interface specifications, board dimensions, weight, power consumption and laser safety class.
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The OBU1 is of two types: OBU101 and OBU102. The OBU101 is used at the receive end. The OBU102 is used at the transmit end.
Splitter
Pumping current
PIN
Power supply module +5 V +5 V +5 V DC/DC converter DC/DC converter Delayed startup Fuse
Signal Flow
The OBU1 accesses the multiplexed optical signals, which are amplified by the EDFA optical module. The OBU1 then outputs the amplified optical signals through the OUT port. The OBU1 also outputs few monitoring signals to the test instrument for performance analysis.
Optical Splitter
The splitter is used to split the optical signals received from the EDFA optical module into two channels of signals with different power. One channel of signlas are output from OUT optical
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interface and then transmitted in the main optical channel. The other channel of signals are output to the MON port for sepctrum detection and monitoring. The power of signals at the MON is one ninety-nineth of that at the OUT interface. In other words, the power of signals at MON is 20 dB lower than that at the OUT interface.
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OBU1
STAT ACT PROG SRV
LASER RADIATION
DO NOT VIEW DIRECTLY WITH OPTICAL INSTRUMENTS
MON OUT IN
OBU1
Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are three pairs of optical interfaces on the front panel of the OBU1. Table 11-32 lists the type and usage of the optical interfaces.
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Table 11-32 Optical interfaces of the OBU1 Interface IN OUT MON Interface Type LC LC LC Usage Inputs multiplexed signals to be amplified. Outputs the amplified multiplexed signals. Connects to the test instrument to monitor the inservice performance.
For example, the feature code of the TN11OBU1 is G23I-3. The feature code indicates that the gain is 23 dB and the maximum nominal input optical power is 3 dBm.
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Table 11-34 Specifications of optical interfaces of the OBU1 Item Specification OBU1C01 Working wavelength range (nm) Range of input optical power (dBm) Range of output optical power (dBm) Input power (dBm) of a typical single wavelength Maximum nominal output optical power (dBm) of a single wavelength Path gain (dB) Noise figure (dB) Gain flatness (dB) Pre-incline of the gain spectral form 1529 to 1561 32 to 4 12 to 16 20 0 OBU1C02 1529 to 1561 32 to 3 9 to 20 19 4
Mechanical Specifications
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.3
Power Consumption
l
In the normal temperature (25), the maximum power consumption of the OBU1 is 16 W. In the high temperature (55), the maximum power consumption of the OBU1 is 17.6 W. In the normal temperature (25), the maximum power consumption of the OBU1 is 18 W. In the high temperature (55), the maximum power consumption of the OBU1 is 19.8 W.
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11.10 FIB
This section describes the FIB, a wavelength filter and isolation board, in terms of the version, function, principle, front panel, configuration and specifications. 11.10.1 Version Description The functional version of the FIB board is N1. 11.10.2 Function and Feature The FIB, a filter and isolation board, is used to filter and isolate 1 x STM-16 optical signals. 11.10.3 Working Principle and Signal Flow The FIB consists of an isolator and a filter. 11.10.4 Front Panel On the front panel of the FIB, there are two pairs of optical interfaces. 11.10.5 Valid Slots The FIB can be housed in any of slots 1213 in the subrack. 11.10.6 Technical Specifications The technical specifications of the FIB cover the optical interface specifications, board dimensions, weight and power consumption.
Single span
BA17
G.652
Erbium doped
G.652
ROP
ISO
Filter
1550.12
Optical receiver
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Table 11-35 Functions and features of the FIB Function and Feature Optical isolator Optical filter FIB The isolator lets optical signals pass in a unidirectional manner. The working wavelength ranges from 1529 nm to 1561 nm. The filter filters all signals carried in wavelengths except those in the 1550.12 nm wavelength.
After travelling for a long distance in fibers, optical signals are heavily attenuated and then degraded. The degraded signals cannot be normally received by optical receiver. In this case, the ROP should be used to amplify the gain of the optical signals. The ROP has high optical power. To prevent other factors from affecting the ROP, use the FIB to filter wavelengths. The filter of the FIB lets optical signals pass in a unidirectional manner. The filter filters all signals carried in other wavelengths except those in the 1550.12 nm wavelength. In this way, the optical receiver can normally receive optical signals.
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OUT IN
FIB
Interfaces
On the front panel of the FIB, there are a LC optical interface and a LSH optical interface, which are used to receive and transmit 1-channel 2.5 Gbit/s optical signals. The optical interfaces use pluggable optical modules for easy maintenance. Table 11-36 Optical interfaces of the FIB Interface IN OUT Interface Type LSH LC Usage Receive 1-channel 2.5 Gbit/s optical signals. Transmit 1-channel 2.5 Gbit/s optical signals.
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Mechanical Specifications
The mechanical specifications of the FIB are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg): 0.4
Power Consumption
The FIB does not consume power.
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12
About This Chapter
This chapter describes the optical amplifier boards, such as the BA2, BPA, and COA, and the dispersion compensation boards, such as the DCU. 12.1 BA2 This section describes the BA2, 2-channel optical booster amplifier board, in terms of the version, function, working principle, front panel and specifications. 12.2 BPA This section describes the BPA, one-channel amplifier and one-channel pre-amplifier board, in terms of the version, function, principle, front panel and specifications. 12.3 COA This section describes the COA, a case-shaped optical amplifier, in terms of the version, function, principle, front panel, installation position and specifications.
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12.1 BA2
This section describes the BA2, 2-channel optical booster amplifier board, in terms of the version, function, working principle, front panel and specifications. 12.1.1 Version Description The functional version of the BA2 board is N1. 12.1.2 Function and Feature During the long-haul transmission of optical signals, the attenuation of signals is high. The BA should be used, and thus the optical receiver can normally receive optical signals. 12.1.3 Working Principle and Signal Flow The BA2 consists of the EDFA module, control module, communication module, and DC/DC converter module. 12.1.4 Front Panel On the front panel of the BA2, there are indicators and interfaces. 12.1.5 Valid Slots The BA2 can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, or any of slots 1113 in the OptiX OSN 1500B subrack. 12.1.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the BA2 indicates the output optical power of the optical interfaces. 12.1.7 Technical Specifications The technical specifications of the BA2 cover the optical interface specifications, board dimensions, weight and power consumption.
Receive
The BA2 amplifies the power of two-channel optical signals. Table 12-1 lists the functions and features of the BA2.
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Table 12-1 Functions and features of the BA2 Function and Feature Basic function BA2 Increases the launched optical power of the line board to 1315 dBm or 1518 dBm. Thus, when the G.652 optical fiber with a loss of 0.275 dB/km is used, the transmission distance can be 120 km, 130 km, or above. Automatically controls the optical power and laser temperature of the EDFA module. Automatically monitors the input and output optical power of the EDFA module and queries the optical power. Protects the EDFA module. When no optical signals are input, the laser is automatically turned off. When optical signals are input, the laser is automatically turned on. Performance and alarm monitoring Software upgrade Reports the performance parameters of the laser. Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports the software upgrade and expansion without interrupting services.
EDFA
NOTE
The BA2 provides the IPA function. When the IPA function is enabled, the pumping laser is turned off if no input signals are detected on the receive end of the line board. Thus, this function is used to prevent the high laser power from damaging eyes.
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Fiber distributor
Input isolate
WDM coupler
Output isolate
Filter
Optical splitter
Optical output
Laser pump
Manual control
Laser shutdown
LOS in
Control&Generation alarms
Control module
Communication module
+3.3 V 5V
Fuse
Fuse
EDFA Module
The optical amplifier unit consists of two EDFA modules. One is BA and the other PA. When the board is used as a pre-amplifier (PA), an optical filter with 1550.12 nm as the central wavelength is added to the optical output end of the module. A booster amplifier (BA) does not have the filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the erbium fiber inside the EDFA module. Bump light and input signal light are coupled into the erbium fiber through an optical coupler. The input and output optical signals of the module are led out by two fiber splitters as per a specific coupling ratio. The optical signals are then converted to optical current by two PIN photoelectrical diodes. The input and output powers of the EDFA module are determined as per the optical signals. The module also applies optical isolating measures at the input and the output ends to improve the performance of the module.
Control Module
The control module:
l l l l
Detects and drives bump electricity Controls the pump temperature of laser Detects input and output power Reports alarms
The control module consists of A/D converting unit, D/A converting unit and CPU. The A/D converting unit converts the temperature value of the cooling electricity and the input/output
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optical power from analog values to digital values. The converted values are then sent to CPU, which generates performance reporting event or alarm. The A/D converting unit also converts bump electricity from analog values to digital values. The converted values are then sent to CPU. After the CPU processes the converted values, the D/A converting unit controls precisely the driving analog circuit of the bump laser of the EDFA optical module. The internal temperature of the bump laser module is kept at 25. The temperature sensor inside the bump laser outputs temperature change to drive cooler to keep the internal temperature of the bump laser module at 25.
Communication Module
The communication module supports ethernet communication.
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BA2
STAT ACT PROG SRV
OUT IN
BA2
Figure 12-4 shows the appearance of the front panel of the double-interface BA2.
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Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the single-interface BA2, there are a pair of optical interfaces, which transmit and receive one channel of optical signals. A pluggable optical module is used for easy maintenance. On the front panel of the double-interface BA2, there are two pairs of optical interfaces, which transmit and receive two channels of optical signals. Two pluggable optical modules are used for easy maintenance.
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WARNING
In practical engineering, if two LC optical interfaces are available on the front panel of the singleinterface BA2, only one optical interface (IN1/OUT1) is available. In the case of the BA2 with two LC optical interfaces on the front panel, determine whether the BA2 is a single-interface BA2 or a double-interface BA2 according to 12.1.6 Board Feature Code. Table 12-2 lists the type and usage of the single-interface BA2. Table 12-2 Optical interfaces of the single-interface BA2 Interface IN OUT Interface Type LC LC Usage Receives the first channel of optical signals. Transmits the first channel of optical signals.
Table 12-3 lists the type and usage of the double-interface BA2. Table 12-3 Optical interfaces of the double-interface BA2 Interface IN1 OUT1 IN2 OUT2 Interface Type LC LC LC LC Usage Receives the first channel of optical signals. Transmits the first channel of optical signals. Receives the second channel of optical signals. Transmits the second channel of optical signals.
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Table 12-4 Relation between the board feature code and output optical power for the BA2 Board Barcode SSN1BA201 SSN1BA202 SSN1BA203 SSN1BA204 SSN1BA205 Feature Code 01 02 03 04 05 Output Optical Power 14 dBm for dual-channel optical power amplification 17 dBm for dual-channel optical power amplification 14 dBm for optical power amplification 17 dBm for optical power amplification 14 or 17 dBm for dual-channel optical power amplification
Mechanical Specifications
The mechanical specifications of the BA2 are as follows:
l
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Power Consumption
In the normal temperature (25), the maximum power consumption of the BA2 is 20 W.
12.2 BPA
This section describes the BPA, one-channel amplifier and one-channel pre-amplifier board, in terms of the version, function, principle, front panel and specifications. 12.2.1 Version Description The BPA board has two versions, N1 and N2. The difference between the two versions lies in the components of the EDFA optical module. 12.2.2 Function and Feature During the long-haul transmission of optical signals, the attenuation of signals is high. The BA and PA should be used, and thus the optical receiver can normally receive optical signals. 12.2.3 Working Principle and Signal Flow The BPA consists of the EDFA module, control module, communication module, and DC/DC converter module. 12.2.4 Front Panel On the front panel of the BPA, there are indicators and interfaces. 12.2.5 Valid Slots The BPA can be housed in any of slots 1213 in the OptiX OSN 1500A subrack, or any of slots 1113 in the OptiX OSN 1500B subrack. 12.2.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the BPA indicates the output optical power of the optical interfaces. 12.2.7 Technical Specifications The technical specifications for the BPA cover the optical interface specifications, board dimensions, weight and power consumption.
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Item Replaceability
Description The two versions can fully replace each other. If the ALS function is used, the N2BPA board is used to replace the N1BPA board. In this case, the ALS function needs to be enabled on the BPA board. If the N1BPA board is used to replace the N2BPA board, the ALS function needs to be enabled on the line board. If the ALS function is disabled, this restriction is not required.
Receive
Transmit
PA
Receive
Table 12-7 lists the functions and features of the BPA. Table 12-7 Functions and features of the BPA Function and Feature Basic function BPA Increases the launched optical power of the line board to 1315 dBm or 1518 dBm. Thus, when the G.652 optical fiber with a loss of 0.275 dB/km is used, the transmission distance can be 120 km, 130 km, or above. Provides the PA module to preamplify the received optical signals. Increases the power of the small volume of optical signals by 2225 dB(N1BPA), 22dB33dB(N2BPA), and thus enhances the sensitivity of the receiver to 37 dBm.
Function of the PA
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BPA
l
Automatically controls the optical power and laser temperature of the EDFA module. Automatically monitors the input and output optical power of the EDFA module and queries the optical power. Protects the EDFA module. When no optical signals are input, the laser is automatically turned off. When optical signals are input, the laser is automatically turned on.
Reports the performance parameters of the laser. Provides rich alarms and performance events for easy management and maintenance of the equipment. Supports the software upgrade and expansion without interrupting services.
a: The BPA does not support the alarm in the test state and the query of the power supply voltage.
Optical part
Drive module
SCC
Communication module
Control module
Figure 12-7 shows the block diagram for the functions of the N2BPA board.
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Figure 12-7 Block diagram for the working principle of the N2BPA
Optical input Optical output Optical input Optical output
Optical part
Drive module
SCC
Communication module
Control module
Optical Part
The N1BPA board consists of two EDFA optical modules, but the N2BPA board consists of one EDFA optical module only. The EDFA optical module magnifies the optical power.
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Indicators
The following indicators are present on the front panel of the board:
l l l l
Board hardware state indicator (STAT), which is green or red when lit. Service activating state indicator (ACT), which is green when lit. Board software state indicator (PROG), which is green or red when lit. Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the BPA, there are two pairs of LC optical interfaces.Table 12-8 lists the type and usage of these optical interfaces. Table 12-8 Optical interfaces of the BPA Interface BIN Interface Type LC Usage Receives one channel of optical signals for amplification.
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Interface Type LC LC LC
Usage Transmits one channel of amplified optical signals. Receives one channel of optical signals for preamplification. Transmits one channel of pre-amplified optical signals.
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Table 12-10 Specifications for the optical interfaces of the BPA Item Nominal bit rate Optical interface type Line code Input wavelength (nm) Specification 2488320 kbit/s and 9953280 kbit/s V-16.2, U-16.2, L-64.2, V-64.2, U-64.2 NRZ BA: 1530 to 1565 PA: 1550.12 Range of input optical power (dBm) BA: 6 to +3 PA28 to 10 (working with the 10G line board) PA38 to10 (woking with the line board of less than 10G) Output optical power (dBm) Sensitivity (dBm) Noise figure (dB) N1BPA+13 to +15 or +15 to +17 (BA) N2BPA+13 to +15 (BA) PA: 37 BA: < 6.5 PA: < 6
NOTE
When performing loopback to the PA module of the BPA, prevent the damage caused by high input optical power to the optical module.
Mechanical Specifications
The mechanical specifications for the BPA are as follows:
l l
Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W) Weight (kg):
Power Consumption
At the normal temperature (25), the maximum power consumption of the BPA is as follows:
l l
12.3 COA
This section describes the COA, a case-shaped optical amplifier, in terms of the version, function, principle, front panel, installation position and specifications.
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12.3.1 Version Description The COA has three versions, 61, 62 and N1. 12.3.2 Function and Feature The COA is used to integrate the EDFA module, drive circuit, and communication circuit in an aluminium case. 12.3.3 Working Principle and Signal Flow The 61COA and N1COA consist of the EDFA module, control module, communication module, and DC/DC converter module. 12.3.4 Front Panel On the front panel of the COA, there are indicators and interfaces. 12.3.5 Installation Position The COA is case-shaped, and thus it is does not occupy a slot in the subrack. 12.3.6 Board Feature Code The code behind the board name in the barcode is the board feature code. The board feature code of the 61COA indicates the output optical power of the optical interfaces. 12.3.7 Technical Specifications The technical specifications of the COA cover the dimensions, weight and power consumption.
The COA is an external and independent amplifier, which does not occupy a slot and can work independently. The maximum numbers of the 61COA, N1COA, and 62COA that can be configured in a system are two, two, and one respectively.
The application of the 61COA and N1COA in the optical transmission system is the same as that of the BA2 and BPA. Table 12-12 lists the functions and features of the 61COA and N1COA. Table 12-12 Functions and features of the 61COA and N1COA Function and Feature Function of the BA 61COA and N1COA The 61COA enhances the launched optical power to 1315 dBm or 1517 dBm, and thus the valid transmission distance of optical signals can be extended. The N1COA is a PA, with a receiver sensitivity of 38 dBm. Supports the ALS function. Communicates with the CXL through the RS232 serial port, reports the alarms and performance events from the COA to the T2000, and receives the configuration commands issued by the T2000.
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62COA
The 62COA, a case-shaped Raman optical amplifier, is used at the receive end of the SDH equipment. The 62COA inputs counter-propagated pumping optical signals to fibers for distributed Raman amplification. Different from that of the 61COA, the gain medium of Raman amplification is the line fiber that can realize better noise performance. Thus, the 62COA can extend the transmission distance, lower the signal-to-noise ratio and realize ultra long hop transmission for a single span. Figure 12-10 lists the appearance of the 62COA. Figure 12-10 Appearance of the case-shaped 62COA
4
2 3
3. COA board
The 62COA, a case-shaped Raman optical amplifier, is used at the receive end of the transmission system. During the transmission, the 62COA amplifies optical signals based on the stimulated Raman scattering of the fiber. The 62COA provides optical transmission for more than 170 km, when used with the EDFA. See Figure 12-11. Figure 12-11 Application of the optical Raman amplifier (62COA)
Raman Amplifier Signal light EDFA Fiber Transmitting end Pump light Coupler Pump light Laser Receiving end Optical receiver
During the optical transmission, the Raman amplifier amplifies optical signals by inputing counter-propagated pumping optical signals to fibers for distributed Raman amplification. Thus, the phase of optical signals is significantly different from that of pumping signals. The power
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fluctuation of the Raman pumping is offset in the counter-propagation, and thus the noise caused by the pumping can be effectively suppressed. Table 12-13 lists the functions and features of the 62COA. Table 12-13 Functions and features of the 62COA Function and Feature Basic function 62COA Configured at the receive end of the SDH system, and provides extra long-haul transmission (more than 170 km), when used with an EDFA at the transmit end with an output power of 17 dBm. The 62COA is a PA, with a receiver sensitivity of -39 dBm. Supports the ALS function. Communicates with the CXL through the RS232 serial port, reports the alarms and performance events from the COA to the T2000, and receives the configuration commands issued by the T2000.
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Figure 12-12 Block diagram for the functions of the 61COA and N1COA
Optical input EDFA module Doped erbium fiber
Fiber distributor
Input isolate
WDM coupler
Output isolate
Filter
Optical splitter
Optical output
Laser pump
Manual control
Laser shutdown
LOS in
Control&Generation alarms
Control module
Communication module
+3.3 V 5V
Fuse
Fuse
EDFA Module
The optical amplifier unit consists of two EDFA modules. One is BA and the other PA. When the board is used as a pre-amplifier (PA), an optical filter with 1550.12 nm as the central wavelength is added to the optical output end of the module. A booster amplifier (BA) does not have the filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the erbium fiber inside the EDFA module. Bump light and input signal light are coupled into the erbium fiber through an optical coupler. The input and output optical signals of the module are led out by two fiber splitters as per a specific coupling ratio. The optical signals are then converted to optical current by two PIN photoelectrical diodes. The input and output powers of the EDFA module are determined as per the optical signals. The module also applies optical isolating measures at the input and the output ends to improve the performance of the module.
Control Module
The control module:
l l l l
Detects and drives bump electricity Controls the pump temperature of laser Detects input and output power Reports alarms
The control module consists of A/D converting unit, D/A converting unit and CPU. The A/D converting unit converts the temperature value of the cooling electricity and the input/output
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optical power from analog values to digital values. The converted values are then sent to CPU, which generates performance reporting event or alarm. The A/D converting unit also converts bump electricity from analog values to digital values. The converted values are then sent to CPU. After the CPU processes the converted values, the D/A converting unit controls precisely the driving analog circuit of the bump laser of the EDFA optical module. The internal temperature of the bump laser module is kept at 25. The temperature sensor inside the bump laser outputs temperature change to drive cooler to keep the internal temperature of the bump laser module at 25.
Communication Module
The communication module supports ethernet communication.
11
Figure 12-14 shows the appearance of the front panel of the 62COA.
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1. SC/PC optical interface 4. Fan board 7. RS232 -2 10. Power input interface
2. LSH optical interface 5. RJ-45 8. DIP switch (85 bits) 11. Power switch
Indicators
The following indicators are present on the front panel of the board:
l l
Board running state (RUN), which is green when lit. Fan alarm indicator (ALM), which is red when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the 61COA and N1COA, there are one pair of SC/PC optical interfaces, which are used to input or output one channel of optical signals. The input optical interface of the 62COA is connected to the LSH flange and the output optical interface is connected to the SC flange. Figure 12-15 shows the SC/PC optical interfaces of the 61COA and N1COA.
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Figure 12-16 shows the flange and fiber connector used at the input optical interface of the 62COA. Figure 12-16 LSH flange and fiber connector
NOTE
The dust cap is specially designed for the LSH fiber jumper. Do not remove the cap during fiber connection. For normal fiber connection, directly insert the fiber jumper into the LSH flange.
The COA has two RS232 serial interfaces, which are connected to the SCC unit for reporting of alarms and performance events. Table 12-14 lists the pins of the RS232 interface.
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RS232-2 2 3 5
Definition Pin for receiving data Pin for transmitting data Pin for common grounding
The RS232-2 interface is used in the case of several COA on one NE. Use the serial interface cable to connect the RS232-2 interface of the COA numbered 1 to the RS232-1 interface of the COA numbered 2. Then connect the RS232-2 interface of the COA numbered 2 to the RS232-1 of the COA numbered 1. Connect the RS232-1 and RS232-2 interfaces in this way. All the COA use the RS232-1 interface of the COA numbered 1 to communicate with the SCC unit in the subrack. The COA has two MONITOR interfaces. The MONITOR-1 and MONITOR-2 interfaces are the alarm output interfaces when the 61COA is used separately. The two interfaces are the same. Table 12-15 lists the pins of the MONITOR-1 and MONITOR-2 interfaces. Table 12-15 Pins of the MONITOR-1 and MONITOR-2 interfaces Front View MONITOR1 1, 6 2, 7
1
The 62COA has one RJ-45 connector, through which the 62COA is connected to the computer for software loading. Table 12-16 lists the pins of the RJ-45 connector of the 62COA.
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9
TIP
For the communication with the CXL, the RS232-1 interface of the COA is connected to the F&f interface through the serial control cable.
MONITOR-2 1, 6 2, 7
Definition The input optical power of the EDFA module is too low. The working current of the pump laser of the EDFA module crosses the threshold. The cooling current of the pump laser of the EDFA module crosses the threshold. The ambient temperature of the EDFA crosses the threshold. Digital ground.
3, 8
3, 8
4, 9 5
4, 9 5
Table 12-16 Pins of the RJ-45 connector of the 62COA Front View Pin 1 2 3 4
8 7 6 5 4 3 2 1
Description Transmitting positive Transmitting negative Receiving positive Not defined Not defined Receiving negative Not defined
5 6 78
The DIP switch of the 61COA or N1COA is on the lower left panel and is used to set the ID for 61COA or N1COA. When you turn it upside, it is OFF. When you turn it downside, it is ON. The SCC uses the IDs to identify and communicate with the 61COA or N1COA. The DIP switch of the 62COA is used to set the ID of 62COA and the type of fibers. The DIP switch has eight bits, from the left to right. The most left one is 8 and the most right one is 1. For each bit, when you turn it upside, it means 0; when you turn it downside, it means 1. The first four bits (14) are used to set the board ID, which ranges from 20 to 35 and from 20 to 27 in actual using. The fifth bit is used to set the fiber type. If it is turned as 0, it indicates the fiber is of the G.652 type. If it is turned as 1, it indicates the fiber is of the G.655 type.
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Table 12-18 Specifications of the optical interfaces of the COA Item Specification 61COA Line code Working wavelength (nm) Range of input optical power (dBm) Output optical power (dBm) Pump wavelength (nm) Max. on/off gain (dB) Noise figure (dB) NRZ 1550 BA: -6 to +3 PA: -10 to -37 +13 to +15 NA NA NA +15 to +17 -10 to -37 1550.12 39 to 20 (2.5 Gbit/s signals without FEC) NA 1451.2 > 15 (for the G.652 fiber) < 1.5 N1COA 62COA
Mechanical Specifications
The mechanical specifications of the 61COA and N1COA are as follows:
l l
Board dimensions (mm): 50 (H) x 190 (D) x 240 (W) Weight (kg): 3.5
Board dimensions (mm): 86 (H) x 436 (D) x 294 (W) Weight (kg): 8.0
Power Consumption
In the normal temperature (25), the maximum power consumption of the 61COA and N1COA is 10 W. In the normal temperature (25), the maximum power consumption of the 62COA is 75 W.
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13
About This Chapter
This chapter describes the power interface boards, such as the UPM (CAU), PIU, and PIUA. 13.1 UPM This section describes the UPM, an uninterruptable power module, in terms of the version, function, principle, front panel and specifications. 13.2 PIU This section describes the PIU, a power interface unit, in terms of the version, function, principle, front panel, configuration and specifications. 13.3 PIUA This section describes the PIUA, a power interface unit, in terms of the version, function, principle, front panel, configuration and specifications.
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13.1 UPM
This section describes the UPM, an uninterruptable power module, in terms of the version, function, principle, front panel and specifications. 13.1.1 Version Description None 13.1.2 Function and Feature The UPM, a special power supply system, is coded GIE4805S. 13.1.3 Working Principle and Signal Flow The UPM receives power from one channel of 220 V AC mains supply, which is rectified to 48 V DC power supply by the rectifier module. Finally, the UPM provides two channels of DC power supplies and one channel of battery power supply. 13.1.4 Rear Panel On the rear panel of UPM, there are indicators and interfaces of many types. 13.1.5 Valid Slots The UPM is in case shape, and thus it does not occupy a slot in the subrack. On the T2000, the logical slot of the UPM is slot 50. 13.1.6 Technical Specifications The technical specifications of the UPM cover dimensions and weight.
80 E4 GI
5S
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One the T2000, the UPM is displayed as a CAU board. Thus, add a CAU on the T2000 to manage and maintain the UPM.
The storage battery of the UPM is used with the power supply case. If the external AC current normally charges the storage battery, the storage battery can provide power for four hours when the external 110 V or 220 V AC current is interrupted. When the UPM provides power supply for the OptiX OSN equipment, only one power supply case should be connected to the storage battery group. The OptiX OSN equipment requires two power supply cases and one storage battery group composed of four 12 V 40 Ah storage batteries. If the equipment does not require the storage battery, only configure one power supply case. The standard full configuration for each power supply case requires two rectifier modules and one monitoring module. Table 13-1 lists the functions and features of the UPM. Table 13-1 Functions and features of the UPM Item Two-channel hot backup UPM The converting portion of the UPM has the hot backup function of two-channel AC/DC rectifier modules. In addition, the two rectifier modules with the function of load balance can work at the same. If one rectifier module fails, the other one immediately takes over the entire load. As a result, the working equipment is not affected, and the system stability is enhanced. In the UPM power supply system, the AC/DC rectifier modules have the hot swap function. When the faulty rectifier module is removed, the other rectifier module is not affected. Thus, the system maintainability is enhanced. The UPM can protect the storage battery. When the mains supply is interrupted, the power supply system can automatically switch to the storage battery. Thus, the normal running of equipment is not affected. The capacity of the storage battery module is 40 Ah. The UPM integrates the monitoring module and T2000 monitoring module. The monitoring module monitors and controls the parameters and states of the rectifier module, AC/DC power distribution, and storage battery group in real time, and then reports the parameters and states to the T2000. The storage battery automaticallly realizes the floating charging and current limiting management. The band loading capacity of each rectifier module is 270 W.
When the UPM works normally, the monitoring module controls the rectifier module, battery loop circuit and loading loop circuit, which then work according to the preset parameters and user settings. The monitoring module also monitors their status and data. When the mains power supply goes faulty, the battery power supply system supplies power to the equipment. Before the mains power supply goes faulty, the battery power supply system must be present. When the mains power supply fails and the battery starts discharging, the monitoring module reports the alarms indicating the fault of the mains power supply. As the battery discharges, the battery voltage decreases. When the battery voltage decreases to 45 V, the monitoring module reports the alarm indicating the undervoltage. When the battery voltage decreases to 43 V, the battery cuts off the connection to the equipment and protects itself. When the mains power supply recovers, the UPM works normally.
! CAUTION
DO NOT INVERT POLARITY
5
AC100~240 ALM Vout ALM Vout RUN
6
ALM
RS232
1 1. AC input 5. Load
3 4. Battery interface
Indicators
The following indicators are for the rectifier module on the left of the UPM.
l l
Rectifier module fault indicator (ALM), which is red when lit. Rectifier module output state indicator (Vout), which is green when lit.
The following indicators are for the monitoring module on the top panel of the UPM.
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Power supply system fault indicator (ALM), which is red when lit. Power supply system indicator (RUN), which is green when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four interfaces on the rear panel of the UPM. Table 13-2 lists the type and usage of these interfaces. Table 13-2 Interfaces on the rear panel of the UPM Interface AC100240 Red switch button Interface Type Power interface Button Usage Acts as a socket for the AC mains supply and accesses 110 V or 220 V AC power supply. Locates on the right of the panel of the rectifier module. Press the switch button to enable or disable the functioning of the rectifier module. The power supply system can connect to the SCC of the OptiX OSN equipment through this interface to realize the functions such as the alarm reporting and remote control. Connect the RS232 serial interface of one power box to the F&f interface of the OptiX OSN equipment. The T2000 then can monitor the battery and the power box. Connect the RS232 interface of the other power box to the ALM1 interface of the OptiX OSN equipment. The T2000 then can monitor the other power box. Three power output interfaces are on the most right of the power box. The top interface is a battery interface, which can be connected to the socket on the battery by using battery cables. The bottom two are loading interfaces, which can be connected to the OptiX OSN equipment and supply power to the equipment.
RS232
Power interface
Table 13-3 lists the pins of the RS232 interface. Table 13-3 Pins of the RS232 interface of the UPM Item Pin for receiving data Pin for transmitting data Pin for common grounding
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Pin 2 3 5
Item Pins for alarms indicating faults of the rectifier module Pins for normal state of the rectifier module Pins for alarms indicating the off state of the AC power supply Pins for the normal state of the AC power supply Pins for the alarm indicating undervoltage discharged from the battery Pins for the alarm indicating no discharge from the battery
Pin 89
89 87
Off On
87 86
Off On
86
Off
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Item Number of backup battery groups Charging current of the backup battery Fuse of the backup battery Undervoltage DC point of the battery Termination voltage point of the battery Floating charge voltage of the battery Regulated voltage precision Non-balance of load sharing
Rated efficiency of the integrated 80% device Peak stray noise voltage Voltage drop in the power panel (20) Electrical network adjustment rate 200 mV 500 mV 0.1%
Mechanical Specifications
The mechanical specifications of the UPM are as follows:
l l
Dimensions of the UPM (mm): 438 (H) x 240 (D) x 44 (W) Dimensions of a battery (mm): 197 (H) x 165 (D) x 170 (W)
13.2 PIU
This section describes the PIU, a power interface unit, in terms of the version, function, principle, front panel, configuration and specifications. The OptiX OSN 1500B supports the PIU and the OptiX OSN 1500A does not. 13.2.1 Version Description The functional version of the PIU is R1. 13.2.2 Function and Feature The PIU is used to access the power supply, and to provide the lightning protection and filtering. 13.2.3 Working Principle and Signal Flow
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The PIU consists of the protecting unit, filter unit, power detecting unit and clock protecting unit. 13.2.4 Front Panel On the front panel of the PIU, there are indicators and power interfaces. 13.2.5 Valid Slots The PIU can be housed in any of slots 1819 in the OptiX OSN 1500B subrack. 13.2.6 Technical Specifications The technical specifications of the PIU cover the dimensions, weight, power consumption, input voltage and fuse tube.
NEG(-)
RTN(+)
RTN(+)
Clock input
LED indication
Clock output
Filter Unit
The filter unit uses the electromagnetic interference (EMI) filter to filter the electromagnetic interference signals and thus to keep the equipment running in a stable manner.
Protecting Unit
This unit is used to prevent the equipment from overcurrent and lightning.
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PIU
O I
POWER
PIU
PWR CLK IN
PWS
Indicators
A power supply indicator (POWER) is present on the front panel of the board and is green when lit.. For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are three power interfaces on the front panel of the PIU. Table 13-6 lists the type and usage of the interfaces. Table 13-6 Interfaces on the front panel of the PIU Interface PWR ClK IN ClK OUT Interface Type Power input interface SMB SMB Usage Inputs the 48 V power supply. 75-ohm clock input interface (SMB) 75-ohm clock output interface (SMB)
Mechanical Specifications
The mechanical specifications of the PIU are as follows:
l l
Board dimensions (mm): 108 (H) x 110 (D) x 41.5 (W) Weight (kg): 1.3
Power Consumption
In the normal temperature (25), the maximum power consumption of the PIU is 1.5 W.
Input Voltage
The input voltage of the PIU ranges from 38.4 V to 72 V.
Fuse Tube
The main loop fuse of the PIU is 250 V-10 A-0.006 ohm.
13.3 PIUA
This section describes the PIUA, a power interface unit, in terms of the version, function, principle, front panel, configuration and specifications. The OptiX OSN 1500A supports the PIUA and the OptiX OSN 1500B does not. 13.3.1 Version Description The functional version of the PIUA is R1. 13.3.2 Function and Feature The PIUA is used to access the power supply, and to provide the lightning protection and filtering. 13.3.3 Working Principle and Signal Flow The PIUA consists of the power interface unit, protecting unit, filter unit, power supply detecting unit, fan power supply unit and external power supply interface unit. 13.3.4 Front Panel On the front panel of the PIUA, there are indicators and power interfaces. 13.3.5 Valid Slots The PIUA can be housed in any of slots 111 in the subrack. 13.3.6 Technical Specifications The technical specifications of the PIUA cover the dimensions, weight, power consumption, input voltage and fuse tube.
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Power detection
LED indication
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Protection Unit
This unit is used to prevent the equipment from overcurrent and lightning.
Filter Unit
The filter unit uses the electromagnetic interference (EMI) filter to filter the electromagnetic interference signals and thus to keep the equipment running in a stable manner.
PIUA
POWER
PIUA
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Indicators
A power supply indicator (POWER) is present on the front panel of the board and is green when lit.. For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the PIUA, there are two interfaces and one switch. Table 13-8 lists the type and usage of the interfaces and switch. Table 13-8 Interfaces and switch on the front panel of the PIUA Interface PWR PWS Interface Type Inputs the 48 V power supply. Output interface for the 50 W power supply Switch Usage Inputs the 48 V power supply. Outputs the 50 W power supply for the COA or HUB.
Power switch
Turn the switch to position 1 or ON to supply power to the equipment. Turn the switch to position 0 or OFF to shut the power supply to the equipment.
Mechanical Specifications
The mechanical specifications of the PIUA are as follows:
l l
Board dimensions (mm): 111.8 (H) x 220 (D) x 25.4 (W) Weight (kg): 1.5
Power Consumption
In the normal temperature (25), the maximum power consumption of the PIUA is 3 W.
Input Voltage
The input voltage of the PIUA ranges from 38.4 V to 72 V.
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Fuse tube
The main loop fuse of the PIU is 250 V-10 A-0.006 ohm.
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14
About This Chapter
14.1 Fiber Jumper The following section describes the types of fiber jumpers and connectors.
Cables
This chapter describes the cables used for the equipment. The cables include the fiber jumpers, power cables, alarm cables, management cables, signal cables and clock cables.
14.2 Power Cables and Grounding Cables The power cables and grounding cables include the cabinet power cable, equipment supply cable, and UPM power cable. 14.3 Alarm Cable The alarm cables for the equipment include the alarm input/output cable, cabinet indicator cable, alarm concatenation cable and alarm input/output cable. 14.4 Management Cable The management cable includes the serial port cable, ordinary phone wire, COA concatenating cable and network cable. 14.5 Signal Cable The signal cable includes the E1/E3 signal cable, framed E1 signal cable and N x 64 kbit/s signal cable. The OptiX OSN 1500A supports only the E1/E3 signal cable. 14.6 Clock Cable The clock cable includes the clock cable and clock transfer cable.
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Select the fiber connector and the fiber length according to the on-site survey.
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CAUTION
When selecting the fiber connector, make sure that the single-longitudinal mode or multilongitudinal mode optical transmitting module is connected to the single-mode fiber.
14.1.2 Connector
The OptiX OSN equipment can use various types of connectors. The four types of fiber connectors are listed as follows:
l
Interfaces on the front panel of boards are mostly the LC/PC optical interfaces. See Figure 14-1. The N2OU08 and 61COA provide the SC/PC optical interfaces. The "IN" interface on the externally-installed case-shaped 62COA uses the LSH/APC connector. See Figure 14-4. The ODF at the client side uses the FC/PC or SC/PC optical interface. Figure 14-3 and Figure 14-2 show the corresponding FC/PC and SC/PC optical connectors.
l l
Table 14-2 lists the description of the four optical connectors. Table 14-2 Types of connectors Internal Fiber Connector LC/PC LSH/APC FC/PC SC/PC Description Plug-in square fiber connector/protruding polished Connector with dust-proof cover/protruding polished (8 degrees) Round fiber connector/protruding polished Square fiber connector/protruding polished
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The axial operation instead of rotation is required to insert or remove the LC/PC optical interface. Align the head of the fiber jumper with the optical interface with proper strength to insert the fiber jumper into the LC/PC connector. To remove the LC/PC fiber jumper, first press the clip, and then push fiber connector inward slightly, and pull out the connector.
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Structure
Figure 14-5 shows the structure of the 48 V cabinet power cable/BGND power grounding cable. Figure 14-6 and Figure 14-7 show the structure of the PGND protection grounding cable.
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Figure 14-5 Cabinet 48 V power cable and BGND power grounding cable
1 2
3
1. Cord end terminal 2. Bare connector-OT type 3. Cable tie
Pin Assignment
None
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Technical Specifications
Item 48 V cabinet power cable Connector 2 Connector 1 Cable type Cabinet BGND power grounding cable Connector 2 Connector 1 Cable type Cabinet PGND protection grounding cable Connector 1 Connector 3 Description Bare crimping terminal-OT type-16 mm2-M8-tin platingbare ring terminal Single cord end terminal-16 mm2-length 24 mm-inserted 12 mm deep-80A-green Power cable-450 V/750 V-16 mm2-round and bllue-85A Bare crimping terminal-OT type-16 mm2-M8-tin platingbare ring terminal Single cord end terminal-16 mm2-length 24 mm-inserted 12 mm deep-80A-green Power cable-450 V/750 V-16 mm2-round and black-85A Bare crimping terminal-OT type-25mm2-M8-tin platingbare ring terminal Bare crimping connector-JG2-25 mm2-M6-95A-tin plating, or bare crimping connector-JG2-25 mm2-M8-95Atin plating, or bare crimping terminal-OT type-25 mm2-M8tin plating-bare ring terminal Power cable-450 V/750 V-25 mm2-yellow and green-85 A CM 10 m, 20 m, 30 m
Structure
Figure 14-8 shows the structure of the equipment 48 V/60 V power cable. Figure 14-9 shows the structure of the PGND grounding cable.
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A3 A2 A1
4. Heat-shrink tube
Pin Assignment
For details on the pin assignment, refer to Table 14-3. Table 14-3 Equipment 48 V/60 V power cable Cable connector A1 A3 Corresponding cable W1 W2 Core color Blue (48 V/60 V power) Black (power ground)
Technical Specifications
Item Cable connector Equipment 48 V/60 V power cable Cable connector-D type-3PIN-female PGND grounding cable Bare crimping connector-OT-6 mm2M4-tin plating-pre-insulated ring terminal-1210AWG bare crimping connector-OT-6 mm2-M8-tin platinginsulated ring terminal-1210AWG
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Equipment 48 V/60 V power cable Wire-300 V-16AWGblack (the core is blue and black)-13A 2 CM Blue or black 15 m, 30 m
Structure
Figure 14-10 shows the power cable that is used to connect the UPM to the OptiX OSN 1500. Figure 14-10 Structure of the UPM power cable
A A1 A2 A3 B 1 2
X1
X2
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Structure
Figure 14-11 shows the structure of the alarm input/output cable.
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2. Main tag
Pin Assignment
Table 14-6 lists the pin assignment of the alarm input/output cable. Table 14-6 Pin assignment of the alarm input/output cable Connect or X1 X1.1 X1.2 X1.3 X1.6 X1.4 X1.5 X1.7 X1.8 Color Blue White Orange White Green White Brown White Twisted pair Twisted pair Twisted pair Relation Twisted pair Alarm Output Positive for critical and major alarms Negative for critical and major alarms Positive for minor and warning alarms Negative for minor and warning alarms Positive for alarm signal output 1 Negative for alarm signal output 1 Positive for alarm signal output 2 Negative for alarm signal output 2 Alarm Input SW_INPUT 1+ SW_INPUT 1 SW_INPUT 2+ SW_INPUT 2 SW_INPUT 3+ SW_INPUT 3 SW_INPUT 4+ SW_INPUT 4
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Technical Specifications
Item Connector X1 Cable type Description Network interface connector-8PIN-8 bit-shielded-crystal plug Twisted pair cable-120 ohms-SEYPVPV-0.5 mm-24AWG-8 coresPANTONE 430U Twisted pair cable-10015 ohms-shielded enhanced type 5 CAT5E SFTP-24AWG-8 core-PANTONE445U Number of cores Fireproof class Core diameter Length 8 CM 0.5 mm 10 m, 20 m, 30 m
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Structure
Figure 14-12 shows the structure of the OAM serial port cable (DB25 connector). Figure 14-12 Structure of the OAM serial port cable
Pin Assignment
Table 14-7 lists the pin assignment of the alarm input/output cable. Table 14-7 Pin assignment of the OAM serial port cable Connector X1 X1.2 X1.3 X1.6 X1.4 X1.5 Connector X2 X2.20 X2.2 X2.3 X2.7 Relation Single Single Single Twisted pair Description Data terminal ready (DTR) Transmit data (TD) Receive data (RD) Signaling ground (SG)
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Technical Specifications
Item Connector X1 Connector X2 Type Number of cores Fireproof class Length Description Network interface connector-8PIN-8 bit-shielded-crystal plug Cable connector-D type-25PIN-male or cable connector-D type-9PINmale Twisted pair cable-120 ohms-SEYPVPV-0.5 mm-24AWG-8 corePANTONE 430U 8 CM 5000 mm
Transparently transmits the environment detecting data signals. Manages the external device such as the COA.
Structure
Figure 14-13 shows the structure of the Serial 14/F1/F&f serial port cable. Figure 14-13 Structure of the Serial 14/F1/F&f serial port cable
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Pin Assignment
Table 14-8 lists the pin assignment of the Serial 14/F1/F&f cable. Table 14-8 Pin assignment of the Serial 14/F1/F&f serial port cable Connector X1 X1.1 X1.2 X1.3 X1.6 X1.4 X1.8 X1.5 Connector X2 X2.8 X2.9 X2.6 X2.7 X2.3 X2.2 X2.5 Single Twisted pair Twisted pair Relation Twisted pair Description RS422RX+ RS422RX RS422TX+ RS422TX RS232RX RS232TX SG
Technical Specifications
Item Connector X1 Connector X2 Cable type Number of cores Fireproof class Length Description Network interface connector-8PIN-8 bit-shielded-crystal plug Cable connector-D type-9 PIN-male 1. Twisted pair-120 ohms-SEYPVPV-0.5 mm-24AWG-8 core-PANTONE 430U 2. Twisted pair-100 ohms-SEYVP-0.48 mm-26AWG-8 core-black 8 CM 15 m for cable type 1 and 3 m for cable type 2
Structure
Figure 14-14 shows the structure of the RS232/RS422 serial port cable.
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2. Main tag
Pin Assignment
Table 14-9 lists the pin assignment of the RS232/RS422 serial port cable. Table 14-9 Pin assignment of the RS232/RS422 serial port cable Connector X1 X1.3 X1.6 X1.1 X1.2 X1.5 X1.4 X1.8 Connector X2 X2.1 X2.2 X2.3 X2.6 X2.5 X2.8 X2.4 Single Twisted pair Twisted pair Relation Twisted pair Description RX+ RX TX+ TX SG 232RX 232TX
Technical Specifications
Item Connector X1/X2 Cable type Number of cores Fireproof class Length Description Network interface connector-8PIN-8 bit-shielded-crystal plug Twisted pair cable-120 ohms-SEYPVPV-0.5 mm-24AWG-8 corePANTONE 430U 8 CM 15 m
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Structure
Figure 14-15 shows the structure of the ordinary telephone wire. Figure 14-15 Structure of the ordinary telephone wire
2. Main tag
Pin Assignment
Table 14-10 lists the pin assignment of the ordinary telephone wire. Table 14-10 Pin assignment of the ordinary telephone wire Connector X1 X1.1 X1.2 X1.3 X1.4 X1.5 X1.6 Connector X2 X2.1 X2.2 X2.3 X2.4 X2.5 X2.6 Description No connected No connected TIP RING No connected No connected
Technical Specifications
Item Connector X1/X2 Cable type Number of cores Fireproof class
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Description Network interface connector-6PIN-26 to 28AWG Power cable-150 V-UL20251-0.08 mm2-28AWG-black-1A-2-core telephone wire 2 CM
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Item Length
Description 15 m
Structure
Figure 14-16 shows the structure of the COA concatenating cable. Figure 14-16 Structure of the COA concatenating cable
2. Tag
Pin Assignment
Table 14-11 lists the pin assignment of the COA concatenating cable. Table 14-11 Pin assignment of the COA concatenating cable Connector X1 3 2 5 Connector X2 2 3 5 Grounding Remarks One pair
Technical Specifications
Item Connector X1/X2
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Description Twisted pair-100 ohms-UL2464-0.32 mm-28AWG-2P-Huawei gray Two pairs CM 0.6 m, 2.5 m
Structure
Figure 14-17 shows the structure of the straight through cable. Figure 14-17 Structure of the straight through cable
2. Tag 1
3. Main tag
4. Tag 2
Pin Assignment
Table 14-12 lists the pin assignment of the straight through cable. Table 14-12 Pin assignment of the straight through cable Connector X1 X1.1 X1.2 X1.3 X1.6
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Twisted pair
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Twisted pair
Technical Specifications
Item Connector X1/X2 Cable type Number of cores Fireproof class Length Description Network interface connector-crystal plug-8PIN-8bit-shielded-24 to 26AWG-CAT 6/used with SFTP network cable Communication cable-10015 ohms-shielded enhance type 5CAT5E-SFTP 24AWG-8 cores-PANTONE 445U 8 CM 5 m, 10 m, 20 m, 30 m
Structure
Figure 14-18 shows the structure of the crossover cable. Figure 14-18 Structure of the crossover cable
2. Tag 1
3. Main tag
4. Network cable
5. Tag 2
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Pin Assignment
Table 14-13 lists the pin assignment of the crossover cable. Table 14-13 Pin assignment of the crossover cable Connector X1 X1.6 X1.3 X1.1 X1.2 X1.4 X1.5 X1.7 X1.8 Connector X2 X2.2 X2.1 X2.3 X2.6 X2.4 X2.5 X2.7 X2.8 Color Orange White or orange White or green Green Blue White or blue White or brown Brown Twisted pair Twisted pair Twisted pair Relation Twisted pair
Technical Specifications
Item Connector X1/X2 Cable type Number of cores Fireproof class Length Description Network interface connector-crystal plug-8PIN-8bit-shielded-24 to 26AWG-CAT 6/used with SFTP network cable Communication cable-1005 ohms-CAT5E-SFTP 24AWG-8 coresPANTONE 445U 8 CM 5 m, 30 m
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The 120-ohm 8 x E1 cable is used to input and output E1 signals. 14.5.4 120-ohm 16 x E1 Cable The 120-ohm 8 x E1 cable is used to input and output E1 signals. 14.5.5 E3/T3/STM-1 Cable The E3/T3/STM-1 cable is used to input and output E3/T3/STM-1 signals. Use the SMB connector at one end to connect the cable to the E3/T3/STM-1 interface board. Use a connector to connect the other end to the DDF. The connector should be made according to the on-site requirements. 14.5.6 Framed E1 Cable The framed E1 cable is connected to the DB44 connector of the DM12 to access 8 x framed E1 signals. 14.5.7 N x 64 kbit/s Cables The N x 64 kbit/s cable is connected to the DB28 connector of the DM12 to access one channel of N x 64 kbit/s services.
Structure
Figure 14-19 shows the structure of the 75-ohm 8 x E1 cable. Figure 14-19 Structure of the 75-ohm 8 x E1 cable
Pin Assignment
Table 14-14 lists the pin assignment of the 75-ohm 8 x E1 cable.
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Table 14-14 Pin assignment of the 75-ohm 8 x E1 cable Conne ctor 38 23 37 22 36 21 35 20 15 30 14 29 13 28 12 27 Shell Cable W1 Core Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip External braid shield layer 8 T4 6 T3 4 T2 2 T1 7 R4 5 R3 3 R2 No. 1 R1 34 19 33 18 32 17 31 16 11 26 10 25 9 24 8 7 Shell Remarks Connector Cable W2 Core Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip External braid shield layer 8 T8 6 T7 4 T6 2 T5 7 R8 5 R7 3 R6 No. 1 Remark s R5
Technical Specifications
Item Connector X Cable type Fireproof class Number of cores Cover diameterinsulation diameterconductor diameter Length Description Cable connector-D type-44 PIN-male Coaxial cable-SYFVZP-75-1-1x8(A)-75 ohm-9.65 mm-1.2 mm-0.252 mm-Huawei white CM 8 x E1 9.65 mm-1.2 mm-0.252 mm
3 m, 10 m, 15 m, 20 m, 25 m, 30 m, 40 m
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CAUTION
The pin assignment table for the E1 cable is placed in the same packing case with the cable. Do not discard it before installation.
Structure
Figure 14-20 shows the structure of the 75-ohm 16 x E1 cable. Figure 14-20 Structure of the 75-ohm 16 x E1 cable
Main tag
1. Cable connector
2. Terminal
Pin Assignment
Table 14-15 lists the pin assignment of the 75-ohm 16 x E1 cable. Table 14-15 Pin assignment of the 75-ohm 16 x E1 cable Connec tor X a1 a2 a3 a4 a6
14-24
Remar ks R1
Remark s R9
T1
a12 a13
T9
R2
a15
R10
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Connec tor X a7 a8 a9 b1 b2 b3 b4 b6 b7 b8 b9 c1 c2 c3 c4 c6 c7 c8 a9 d1 d2 d3 d4 d6 d7 d8 d9
Cable W Core Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring 16 15 14 13 12 11 10 9 8 7 6 5 4 No.
Remar ks
Cable W Core Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring 32 31 30 29 28 27 26 25 24 23 22 21 20 No.
Remark s
T2
a17 a18
T10
R3
b10 b11
R11
T3
b12 b13
T11
R4
b15 b16
R12
T4
b17 b18
T12
R5
c10 c11
R13
T5
c12 c13
T13
R6
c15 c16
R14
T6
c17 c18
T14
R7
d10 d11
R15
T7
d12 d13
T15
R8
d15 d16
R16
T8
d17 d18
T16
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Technical Specifications
Item Connector X Cable type W Fireproof class Number of cores Cover diameterinsulation diameterconductor diameter Length Description 2mmHM conductor connector-4 x 18PIN-28 to 30AWG-crimp Coaxial cable-SYFVZP-75-1-1x32(A)-75 ohms-18 mm-1.2 mm-0.254 mm-Huawei gray CM 16 x E1 18mm-1.2 mm-0.254mm
10 m, 15 m, 20 m, 25 m, 30 m
CAUTION
The pin assignment table for the E1 cable is placed in the same packing case with the cable. Do not discard it before installation.
Structure
Figure 14-21 shows the structure of the 120-ohm 8 x E1 cable.
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Pin Assignment
Table 14-16 lists the pin assignment of the 120-ohm 8 x E1 cable. Table 14-16 Pin assignment of the 120-ohm E1 cable Connecto r 15 30 14 29 13 28 12 27 11 26 10 25 9 Cable W1 Core Blue White Orang e White Green White Brow n White Grey White Blue Red Orang e Twisted pair Twisted pair Twisted pair T5 Twisted pair Twisted pair T3 No. Twisted pair Twisted pair Remar ks Tx1 Connecto r 38 23 T2 37 22 36 21 T4 35 20 34 19 T6 33 18 T7 32 Cable W2 Core Blue White Orang e White Green White Brown White Grey White Blue Red Orang e Twisted pair Twisted pair Twisted pair R5 Twisted pair Twisted pair R3 No. Twisted pair Twisted pair Remar ks Rx1
R2
R4
R6
R7
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Connecto r 24 8 7 Shell
Remar ks
Connecto r 17
Remar ks
T8
31 16 Shell
R8
Technical Specifications
Item Connector X Cable type Number of cores Inner conductor diameter Fireproof class Length Description Cable connector-D type-44PIN-male Communication cable-120 ohms-SEYPVPV-0.5 mm-24AWG-16 core-PANTONE 430U 16 0.5 mm CM 10 m, 15 m, 20 m, 30 m, 40 m
Structure
Figure 14-22 shows the structure of the 120-ohm 16 x E1 cable.
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X 2
W1
1. Cable connector
2. Terminal
3. Main tag
Pin Assignment
Table 14-17 lists the pin assignment of the 120-ohm 16 x E1 cable. Table 14-17 Pin assignment of the 120-ohm 16 x E1 cable Conne ctor X a1 a2 a6 a7 b1 b2 b6 b7 c1 c2 c6 c7 d1 d2 d6 d7 a10 a11
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Cable W1 Core Blue White Orange White Green White Brown White Grey White Blue Red Orange Red Green Red Brown Red No. Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair
Remark s Rx1
Connect or X a3 a4
Cable W2 Core Blue White Orange White Green White Brown White Grey White Blue Red Orange Red Green Red Brown Red No. Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair
Remarks
Tx1
Rx2
a8 a9
Tx2
Rx3
b3 b4
Tx3
Rx4
b8 b9
Tx4
Rx5
c3 c4
Tx5
Rx6
c8 c9
Tx6
Rx7
d3 d4
Tx7
Rx8
d8 d9
Tx8
Rx9
a12 a13
Tx9
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Conne ctor X a15 a16 b10 b11 b15 b16 c10 c11 c15 c16 d10 d11 d15 d16 a5
Cable W1 Core Grey Red Blue Black Orange Black Green Black Brown Black Grey Black Blue Yellow Shell No. Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair
Remark s Rx10
Cable W2 Core Grey Red Blue Black Orange Black Green Black Brown Black Grey Black Blue Yellow Shell No. Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair Twiste d pair
Remarks
Tx10
Rx11
b12 b13
Tx11
Rx12
b17 b18
Tx12
Rx13
c12 c13
Tx13
Rx14
c17 c18
Tx14
Rx15
d12 d13
Tx15
Rx16
Tx16
Technical Specifications
Item Connector X Cable type W1/W2 Number of cores Inner conductor diameter Fireproof class Length Description 2mmHM conductor connector-4 x 18PIN-24 to 26AWG-crimp Nominal twisted pair cable-120 ohms-SEYPVPV-0.5 mm-24AWG-32 core-PANTONE 430U 32 0.5 mm
CM 10 m, 15 m, 20 m, 25 m, 30 m
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Structure
Figure 14-23 shows the structure of the E3/T3/STM-1 cable. Figure 14-23 Structure of the E3/T3/STM-1 cable
1. Coaxial connector-SMB
2. Main tag
3. Coaxial cable
Pin Assignment
None
Technical Specifications
Item Connector Cable I Description Coaxial connector-SMB-75 ohms-straight and female Coaxial cable-75 ohms-3.9 mm-2.1 mm-0.34 mm-shielded Cover diameter 3.9 mm-insulation diameter 2.1 mm-conductor diameter 0.34 mm Length: 10 m, 15 m, 20 m, 30 m Cable II Coaxial cable-75 ohms-4.4 mm-2.4 mm-0.4 mm-shielded-gray Cover diameter 4.4 mm-insulation diameter 2.4 mm-conductor diameter 0.4 mm Length: 15 m, 20 m, 25 m, 30 m, 40 m Cable III Coaxial cable-75 ohms-6.7 mm-3.8 mm-0.61 mm-shielded-gray Cover diameter 6.7 mm-insulation diameter 3.8 mm-conductor diameter 0.61 mm Length: 15 m, 20 m, 25 m, 30 m, 130 m Cable IV Coaxial cable-75 ohms-5.80 mm-3.71 mm-0.643 mm-black Cover diameter 5.80 mm-insulation diameter 3.71 mm-conductor diameter 0.643 mm
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Item
Description Length: 30 cm
Fireproof class
CM
See the section that describes the 75-ohm 8 x E1 cable for details on the structure, pin assignment and technical specifications of the 75-ohm framed E1 cable. See the section that describes the 120-ohm 8 x E1 cable for details on the structure, pin assignment and technical specifications of the 120-ohm framed E1 cable.
Signal TXD+ TXD TXC+ TXC NC GND MODE0 MODE1 MODE2 MODE_DCE DCD+
Description Transmits data. Transmits data. The DCE provides the transmitting clock to the DTE. The DCE provides the transmitting clock to the DTE. Circuit_GND Identifies the cable type. Identifies the cable type. Identifies the cable type. Identifies the DCE/DTE cable type. Detects the carrier.
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Pin 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Signal DCD RTS+ RTS TXCE+ TXCE RXC+ RXC RXD+ RXD GND LL CTS+ CTS DSR+ DSR DTR+ DTR
Description Detects the carrier. Requests for transmission. Requests for transmission. Transmitting data clock for DCE and loopback clock for DTE. Transmitting data clock for DCE and loopback clock for DTE. Receives clock. Receives clock. Receives data. Receives data. Shield_GND Loopback control signals. Prepares for transmission. Prepares for transmission. Prepares the DCE. Prepares the DCE. Prepares the DTE. Prepares the DTE.
According to the protocols for the N x 64 kbit/s signals, the N x 64 kbit/s cables are classified into the following ten types.
l l l l l l l l l l
V.35 DCE cable V.35 DTE cable V.24 DCE cable V.24 DTE cable X.21 DCE cable X.21 DTE cable RS449 DCE cable RS449 DTE cable RS530 DCE cable RS530 DTE cable
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Pos.28 A W B
Pos.1
C A E K P U Y CC HH MM D J N T X BB FF LL B F L R V Z DD JJ NN
X1
X2
M S W AA EE KK
2. Main tag
Table 14-19 lists the pin assignment of the V.35 DCE cable. Table 14-19 Pin assignment of the V.35 DCE cable Connector X1 19 20 1 2 15 16 3 4 17 18 11 22 23 13 25
14-34
Connector X2 P S R T V X Y AA U W F J C D H
Twisted pair
Twisted pair
Twisted pair
Twisted pair
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Connector X1 27 21 6+7+8
Connector X2 E B A
The technical specifications of the V.35 DCE cable are as follows. Item Connector X1 Connector X2 Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solder-spacing 0.8 mm-28 to 30AWG, exclusively used for OEM Cable connector-V35 plug-34PIN-injection molding shell-tube, exclusively used for OEM Cable connector-V35 DCE plug-34PIN-female-cable crimping-core, exclusively used for OEM Cable type Number of cores Core diameter Length Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 corePANTONE 296U-exclusively used by OEM 5 pairs and 8 cores 0.32 mm 3m
1
Pos.28 A
Pos.1
X1
X2
A B C D E F H J L N K M R T P S V X U W Z BB Y AA DD FF CC EE JJ LL HH KK NN MM
Table 14-20 lists the pin assignment of the V.35 DTE cable.
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Table 14-20 Pin assignment of the V.35 DTE cable Connector X1 1 2 19 20 17 18 3 4 15 16 11 22 13 23 27 25 21 6+10+7+8 Connector X2 P S R T V X Y AA U W F J C D H E B A Short circuiting 6, 7, 8 and 10 Twisted pair Twisted pair Twisted pair Twisted pair Relation Twisted pair
The technical specifications of the V.35 DTE cable are as follows. Item Connector X1 Connector X2 Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solderspacing 0.8 mm-28 to 30AWG, exlusively used for OEM Cable connector-V35 plug-34PIN-injection molding shell-tube, exclusively used for OEM Cable connector-V35 DTE plug-34PIN-male-cable crimping-core, exclusively used for OEM Cable type Number of cores
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Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 corePANTONE 296U-exclusively used by OEM 5 pairs and 8 cores
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Description 0.32 mm 3m
1
Pos.25
3
Pos.1
Pos.28 Pos.1
X2
X1
2. Main tag
Table 14-21 lists the pin assignment of the V.24 DCE cable. Table 14-21 Pin assignment of the V.24 DCE cable Connector X1 19 1 23 13 25 27 11 22 3 17 15 21
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Connector X2 2 3 4 5 20 6 8 18 15 24 17 1
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Single
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Connector X1 6+7
Connector X2 7
The technical specifications of the V.24 DCE cable are as follows. Table 14-22 Technical specifications of the V.24 DCE cable Item Connector X1 Connector X2 Cable type Number of cores Core diameter Length Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solderspacing 0.8 mm-28 to 30AWG, exlusively used for OEM Cable connector-D type-25PIN-female-cable solder Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 corePANTONE 296U-exclusively used by OEM 5 pairs and 8 cores 0.32 mm 3m
B-B
2 3
Pos.28 Pos.25
X2
X1
2. Main tag
Table 14-23 lists the pin assignment of the V.24 DTE cable. Table 14-23 Pin assignment of the V.24 DTE cable Connector X1 1
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Connector X2 2
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Connector X1 19 13 23 27 25 11 22 3 15 17 21 6+10+7
Connector X2 3 4 5 20 6 8 18 15 24 17 1 7
Relation
Twisted pair
Twisted pair
Twisted pair
Twisted pair
The technical specifications of the V.24 DTE cable are as follows. Table 14-24 Technical specifications of the V.24 DTE cable Item Connector X1 Connector X2 Cable type Number of cores Core diameter Length Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solderspacing 0.8 mm-28 to 30AWG, exlusively used for OEM Cable connector-D type-25PIN-male-cable solder Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 corePANTONE 296U-exclusively used by OEM 5 pairs and 8 cores 0.32 mm 3m
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B-B
2 3
Pos.1
W
A
Pos.1
Pos.28
X2
X1
2. Main tag
Table 14-25 lists the pin assignment of the X.21 DCE cable. Table 14-25 Pin assignment of the X.21 DCE cable Connector X1 13 14 23 24 19 20 1 2 15 16 21 6+9 Connector X2 5 12 3 10 2 9 4 11 6 13 1 8 Short circuiting 6 and 9 Twisted pair Twisted pair Twisted pair Twisted pair Relation Twisted pair
The technical specifications of the X.21 DCE cable are as follows. Table 14-26 Technical specifications of the X.21 DCE cable Item Connector X1 Connector X2
14-40
Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solderspacing 0.8 mm-28 to 30AWG, exlusively used for OEM Cable connector-D type-15PIN-female-cable solder
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Description Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 corePANTONE 296U-exclusively used by OEM 5 pairs and 8 cores 0.32 mm 3m
B-B
2 3
Pos.1
W
A
Pos.15
Pos.28
X2
X1
2. Main tag
Table 14-27 lists the pin assignment of the X.21 DTE cable. Table 14-27 Pin assignment of the X.21 DTE cable Connector X1 13 14 23 24 19 20 1 2 15
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Connector X2 3 10 5 12 4 11 2 9 6
Twisted pair
Twisted pair
Pair
Twisted pair
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Connector X1 16 17 18 21 6+10+9
Connector X2 13 6 13 1 8
Relation
Twisted pair
The technical specifications of the X.21 DTE cable are as follows. Table 14-28 Technical specifications of the X.12 DTE cable Item Connector X1 Connector X2 Cable type Number of cores Core diameter Length Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solderspacing 0.8 mm-28 to 30AWG, exlusively used for OEM Cable connector-D type-15PIN-male-cable solder Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 corePANTONE 296U-exclusively used by OEM 5 pairs and 8 cores 0.32 mm 3m
B-B
2 3
Pos.1
W
A
Pos.15
Pos.28
X2
X1
2. Main tag
Table 14-29 lists the pin assignment of the RS449 DCE cable.
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Table 14-29 Pin assignment of the RS449 DCE cable Connector X1 27 28 25 26 13 14 23 24 11 12 19 20 1 2 15 16 17 18 3 4 22 21 6+8 Connector X2 11 29 12 30 9 27 7 25 13 31 4 22 6 24 8 26 17 35 5 23 10 1 19 Short circuiting 6 and 8 Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Relation Twisted pair
The technical specifications of the RS449 DCE cable are as follows. Table 14-30 Specifications of the RS449 DCE cable Item Connector X1 Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solder-spacing 0.8 mm-28 to 30AWG, exlusively used for OEM
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Description Cable connector-D type-37PIN-female-cable solder-exclusively used for OEM Twisted pair-100 ohms-communication cable-0.32 mm-28AWG-26 core-PANTONE 296U-exclusively used for OEM 26 0.32 mm 3m
B-B
2 W 3
Pos.37
Pos.1
X1 X2
Pos.1
2. Main tag
Table 14-31 lists the pin assignment of the RS449 DTE cable. Table 14-31 Pin assignment of the RS449 DTE cable Connector X1 27 28 25 26 13 14 23 24
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Connector X2 12 30 11 29 7 25 9 27
Twisted pair
Twisted pair
Twisted pair
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Connector X1 11 12 19 20 1 2 15 16 17 18 3 4 22 21 6+8+10
Connector X2 13 31 6 24 4 22 17 35 8 26 5 23 10 1 19
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
The technical specifications of the RS449 DTE cable are as follows. Table 14-32 Specifications of the RS449 DTE cable Item Connector X1 Connector X2 Cable type Number of cores Core diameter Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solderspacing 0.8 mm-28 to 30AWG, exlusively used for OEM Cable connector-D type-SUB plug-37PIN-straight male-cable solder-2 row, standard installation hole, exclusively used for OEM Twisted pair-100 ohms-communication cable-0.32 mm-28AWG-26 corePANTONE 296U-exclusively used for OEM 26 0.32 mm
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B-B
1 2 3
Pos.1 A
X1
Pos.1
Pos.28
X2
2. Main tag
Table 14-33 lists the pin assignment of the RS530 DCE cable. Table 14-33 Pin assignment of the RS530 DCE cable Connector X1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
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Connector X2 22 6 23 20 19 4 18 1 14 2 11 24 9 17 13 5 10
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
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Connector X1 11 4 3 2 1 6+7+9
Connector X2 8 12 15 16 3 7
Relation
Twisted pair
Twisted pair
The technical specifications of the RS530 DCE cable are as follows. Table 14-34 Specifications of the RS530 DCE cable Item Connector X1 Connector X2 Cable type Number of cores Core diameter Length Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solderspacing 0.8 mm-28 to 30AWG, exlusively used for OEM Cable connector-D type-25PIN-female-cable solder Twisted pair-100 ohms-communication cable-0.32 mm-28AWG-26 corePANTONE 296U-exclusively used for OEM 26 0.32 mm 3m
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B-B
2 3
X1
Pos.25
Pos.28
X2
2. Main tag
Table 14-35 lists the pin assignment of the RS530 DTE cable. Table 14-35 Pin assignment of the RS530 DTE cable Connector X1 27 28 25 26 13 14 23 24 11 12 19 20 1 2 15 16 17 18 3 4
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Connector X2 20 23 6 22 4 19 5 13 8 10 3 16 2 14 24 11 17 9 15 12
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
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Connector X1 22 21 6+7+9+10
Connector X2 18 1 7
The technical specifications of the RS530 DTE cable are as follows. Table 14-36 Specifications of the RS530 DTE cable Item Connector X1 Connector X2 Cable type Number of cores Core diameter Length Description Cable connector-D type dual-edge tube-28PIN-straight male-cable solderspacing 0.8 mm-28 to 30AWG, exlusively used for OEM Cable connector-D type-25PIN-male-cable solder Twisted pair-100 ohms-communication cable-0.32 mm-28AWG-26 corePANTONE 296U-exclusively used for OEM 26 0.32 mm 3m
14 Cables
external clock interface of the OptiX OSN equipment. Use a connector to connect the other end to the external clock equipment. The connector should be made according to the on-site requirements.
Structure
Figure 14-34 and Figure 14-35 show the structure of the 75-ohm clock cable and the 120-ohm clock cable respectively. Figure 14-34 Structure of the 75-ohm clock cable
1. Coaxial connector-SMB
2. Tag
X1
Pin Assignment
Table 14-37 lists the pin assignment of the 120-ohm clock cable. Table 14-37 Pin assignment of the 120-ohm clock cable X1 X1.1 X1.2 X1.3 X1.6 X1.4 X1.5
14-50
Remark R1
R2
T1
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X1 X1.7 X1.8
W Brown White
Remark T2
Technical Specifications
Item 75 ohms clock cable Connector Cable Model Diameter Length 120 ohms clock cable Connector X1 Cable Model Conductor diameter Length Description Coaxial connector-SMB-75 ohms-straight and female Coaxial cable-75 ohms-3.9 mm-2.1mm-0.34 mm-shielded cover diameter 3.9 mm-insulation diameter 2.1 mm-conductor diameter 0.34 mm 10 m, 15 m, 20 m, 30 m Network interface cable-8PIN-8bit-shieldedcrystal model connector Twisted pair-120ohms-SEYVP-24AWG-4 pairs- Pantone 430U 0.5 mm/24AWG 10 m, 20 m, 30 m
Structure
Figure 14-36 and Figure 14-37 show the structure of the one-channel clock transfer cable and two-channel clock transfer cable respectively. Figure 14-36 Structure of the one-channel clock transfer cable (75 ohms to 120 ohms)
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Figure 14-37 Structure of the two-channel clock transfer cable (75 ohms to 120 ohms)
2. Tag 1:"1#" 3. Tag 2:"2#" 4. Main tag 6. Tag 3:"1#" 7. Tag 4:"2#"
Pin Assignment
Table 14-38 lists the pin assignment of the two-channel clock transfer cable (75 ohms to 120 ohms). Table 14-38 Pin assignment of the two-channel clock transfer cable (75 ohms to 120 ohms) Connector X1 75-ohm Cable Core Shielding layer X2 Core Shielding layer Color Blue White Blue White W4 120-ohm Cable W3
Technical Specifications
Item One channel Description Connector: coaxial connector-SMB-75 ohms-straight and female 75 ohms cable type: coaxial cable-75 ohms-3.9 mm-2.1 mm-0.34 mm-shielded 75 ohms Cover diameter 3.9 mm-insulation diameter 2.1 mm-conductor diameter 0.34 mm 120 ohms cable type: twisted pair-120 ohms-SEYPVPV-0.4 mm-26AWG-2 pairs-Pantone 430U Inner conductor diameter: 0.4 mm/26AWG Length: 30 m Two channels Connector X1/X2: coaxial connector-SMB-75 ohms-straight and female 75 ohms cable type: coaxial cable-75 ohms-3.9 mm-2.1 mm-0.34 mm-shielded
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Item
Description 75 ohms cable: cover diameter 3.9 mm-insulation diameter 2.1 mm-conductor diameter 0.34 mm 120 ohms cable type: twisted pair-120 ohms-SEYPVPV-0.4 mm-26AWG-2 pairs-Pantone 430U Inner conductor diameter of the 120-ohm cable: 0.4 mm/26AWG Length: 30 m
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A-1
A-2
Circularly lit for 100 ms and unlit for 100 ms (green) Circularly lit for 300 ms and unlit for 300 ms (green) Lit (red)
Unlit
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A-3
The clock is working in the free-run mode and the system clock priority list is not set. By default, the system clock priority list contains only the internal source. The clock is working in the tracing mode and tracing the clock source rather than the internal source in the priority list.
Lit (red)
The system clock priority list is set. Except the internal clock source, all clock sources are lost. The clock is working in the hold-over or free-run mode.
Ethernet Indicator
Indicator Connection status indicator (LINK), which is green when lit. Status Description Lit Unlit Flashing Unlit Indication The network cable is successfully connected to the equipment. The network cable is not connected to the equipment. The data is being transmitted or received. No data is being transmitted or received.
Data receiving and transmitting indicator (ACT), which is orange when lit.
A-4
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A-5
Status Description Lit (red) Flash thrice every other second (red) Flash twice every other second (red) Flash once every other second (red)
Indication The self-check of the memory fails. Critical alarms are generated. Major alarms are generated. Minor alarms are generated.
A-6
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B Labels
Labels
This chapter describes various labels for the OptiX OSN equipment, including the safety labels, optical module labels, and cable labels. B.1 Safety Label Many safety labels are stuck on the equipment. This section describes the suggestions and locations of these safety labels. B.2 Optical Module Labels Optical module labels are used to recognize different types of optical modules. Optical module label is stuck to the optical module. B.3 Engineering Labels The engineering labels should be made according to the the local engineering specifications or Huawei engineering specifications.
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B-1
B Labels
LASER RADIATION
! ATTENTION
CLEAN PERIODICALLY
APD
Receiver MAX:-9dBm
B-2
Issue 02 (2007-03-29)
B Labels
Label
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
MADE IN CHINA
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
N14036
MADE IN CHINA
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
N14036
MADE IN CHINA
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
N14036
MADE IN CHINA
/QUALIFICATION CARD
HUAWEI
MADE IN CHINA
Issue 02 (2007-03-29)
B-3
B Labels
/QUALIFICATION CARD
HUAWEI
MADE IN CHINA
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
N14036
MADE IN CHINA
ATTENTION
CLEAN PERIODICALLY
/QUALIFICATION CARD
HUAWEI
MADE IN CHINA
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
N14036
MADE IN CHINA
ATTENTION
CLEAN PERIODICALLY
B-4
Issue 02 (2007-03-29)
B Labels
APD
Receiver MAX:-9dBm
BA2
LASER RADIATION
DO NOT VIEW DIRECTLY WITH OPTICAL INSTRUMENTS CLASS 1M LASER PRODUCT
As shown in Table B-2, different types of optical module have different codes. Table B-2 Optical module code and type mapping table Optical Module Code 34060288 Optical Type Optical transceiver-ESFP (internal and external alignment)-1310 nmSTM-16-3 dBm-10 dBm-21 dBm-LC-2 km
Issue 02 (2007-03-29)
B-5
B Labels
Optical Module Code 34060278 34060289 34060279 34060277 34060280 34060284 34060285 34060276 34060281 34060282 34060299 34060286 34060219 34060298 34060274 34060325
Optical Type Optical transceiver-ESFP (internal and external alignment)-1310STM-16-0 dBm-5 dBm-21 dBm-LC-15 km Optical transceiver-ESFP (internal and external alignment)-1310 nmSTM-16-3 dBm-2 dBm-30 dBm-LC-40 km Optical transceiver-ESFP (internal and external alignment)-1550STM-16-3 dBm-2 dBm-30 dBm-LC-80 km Optical transceiver-ESFP (internal and external alignment)-1310 nmSTM-4-8 dBm-15 dBm-31 dBm-LC-15 km Optical transceiver-ESFP (internal and external alignment)-1310 nmSTM-4-2 dBm-3 dBm-30 dBm-LC-40 km Optical transceiver-ESFP (internal and external alignment)-1550 nmSTM-4-2 dBm-3 dBm-30 dBm-LC-80km Optical transceiver-ESFP (internal and external alignment)-1550 nmSTM-4-2 dBm-3 dBm--36 dBm-LC-100km Optical transceiver-ESFP (internal and external alignment)-1310 nmSTM-1-8 dBm-15 dBm-31 dBm-LC-15 km Optical transceiver-ESFP (internal and external alignment)-1310 nmSTM1-0 dBm-5 dBm-37 dBm-LC-40 km Optical transceiver-ESFP (internal and external alignment)-1550STM-1-0 dBm-5 dBm-37 dBm-LC-80 km Optical transceiver-ESFP (internal and external alignment)-1310 nmSTM-1-8 dBm-15 dBm-31 dBm-LC (private)-15 km Optical transceiver-ESFP (internal and external alignment)-850 nm-2.125G multirate-2.5 dBm-9.5 dBm-17 dBm-LC-0.5 km Optical transceiver-ESFP (internal and external alignment)-1310 nm-1.25 Gbit/s-3 dBm-9.5 dBm-20 dBm-LC-10 km Optical transceiver-ESFP (internal and external alignment)-1310 nm-1.25 Gbit/s-3 dBm-4.5 dBm-22.5 dBm-LC-40 km Optical transceiver-ESFP (internal and external alignment)-1550 nm-1.25 Gbit/s-5 dBm-2 dBm-23 dBm-LC-80 km Optical transceiver-ESFP (internal and external alignment)-850 nm-2.125 G multirate-2.5 dBm-9.5dBm-17 dBm-LC (private)multimode-0.5 km Optical transceiver-SFP-850 nm-1.25 Gbit/s-0 dBm-9.5 dBm-17 dBm-LC-0.55 km Optical transceiver-SFP-1310 nm-1.25 Gbit/s-3 dBm-9 dBm-20 dBm-LC-10 km
34060049 34060050
B-6
Issue 02 (2007-03-29)
B Labels
Optical Type Optical transceiver-SFP-1310 nm-1.25 Gbit/s-5 dBm-2 dBm-23 dBmLC-40 km Optical transceiver-SFP-1550 nm-1.25 Gbit/s-2 dBm-4 dBm-22 dBmLC-70 km Optical transceiver-SFP-1310 nm-STM-1-14 dBm-19 dBm-30 dBmLC (TX disable)-2 km Optical transceiver-SFP-1310 nm-STM-1-8 dBm-15 dBm-28 dBmLC-15 km Optical transceiver-SFP-1310 nm-STM-1-0 dBm-5 dBm-34 dBmLC-40 km
Suggestion (1) On the loaded cabinet side, the label marked "A01/B08-48V2" on the cable indicates that the cable is 48V2 DC power supply, which is from the eighth connecter on the second row of the 48V bus bar in the cabinet on Row A, and Column 1 in the equipment room. (2) On the distribution unit side, the label marked "B03--48V2" indicates that the cable is 48V2 DC power supply, which is from the loaded cabinet on Row B, Column 03 in the equipment room. For PGND and BGND, it is only necessary to give the row and column of the power distribution unit, instead of the specific serial number of the terminal block on the copper bar.
-48V2
-48V2
(1)
(2)
(1) Indicates the label on the loaded cabinet side, which carries the information about the position of the cable on the power distribution unit. (2) Indicates the label on the distribution unit side, which carries the information about the position of the cable on the loaded cabinet side.
Issue 02 (2007-03-29)
B-7
B Labels
Illustration
Suggestion The external alarm cables are connected to the first subscriber cabinet of each row (used for power distribution). Engineering labels posted on the first cabinet of each row should indicate which equipment is using the access terminal. Engineering labels are not needed on the equipment side unless there are special requirements. The label marked "A01" indicates that the alarm cable connects the first cabinet and the cabinet on Row A, Column 01 in the equipment room.
"A01-03-06-05" indicates that on the local end of the Ethernet cable is connected to Ethernet Port 05, Slot 6, Frame 03 of the cabinet on Row A, Column 01 in the equipment room. "B02-03-12" indicates that the other end of the Ethernet cable is connected to Ethernet Port 12, Frame 03 of the cabinet on Row B, Column 02 in the equipment room. No slot number is specified.
"A01-01-05-05-R" indicates that the local end of the fiber jumper is connected with Optical Receiving Interface 05 on Slot 5, Frame 01 in the cabinet on Row A, Column 01 in the equipment room. "G01-01-01-01-T" indicates that the opposite end of the fiber jumper is connected with optical transmitting interface 01 on Slot 01, Frame 01 in the cabinet on Row G, Column 01 in the equipment room. "ODF-G01-01-01-R" indicates that the local end of the fiber jumper is connected to the optical receiving terminal on Row 01, Column 01 of the ODF in Row G Column 01 in the equipment room. "A01-01-05-05-R" indicates that the other end of the fiber jumper is connected to optical receiving interface 5 on Slot 05, frame 01 in the cabinet on Row A, Column 01 in the equipment room.
B-8
Issue 02 (2007-03-29)
B Labels
Label Labels for trunk cables that connect the equipme nt to the ODF
Illustration
Suggestion "A01-03-01-01-R" indicates that local end of the trunk cable connects with the receiving terminal of Trunk Cable 01 in Slot 01, Frame 03 of the cabinet on Row A, Column 01 in the equipment room. "DDF-G01-01-01-AR" indicates that the opposite end of the trunk cable connects the receiving terminal of Direction A (connected to optical network equipment) on Row 01, Column 01 of the DDF on Row G and Column 01 in the equipment room. "A01-03-01-01" indicates that the local end of the subscriber cable connects with Terminal 01 on Slot 1, Frame 03 of the cabinet on Row A, Column 01 in the equipment room. "MDF-G01-01-01" indicates that the opposite end of the cable connects with the terminal on Row 01, Column 01 of the MDF on Row G, Column 01 in the equipment room.
Issue 02 (2007-03-29)
TO:
B-9
SDH Processing Boards N1SLT1 N1SLQ1 N1SLQ1A N2SLQ1 R1SLQ1 N1SL1, N2SL1 N1SL1A R1SL1 N1SF16 N1SL16, N2SL16 N3SL16 N1SEP1 15 15 17 15 12 14 17 10 26 20 22 17 1.2 1.0 1.0 1.0 0.54 1.0 1.0 0.5 1.1 1.1 1.1 1.0 N1SLQ4 N1SLQ4A N2SLQ4 N1SLD4 N1SLD4A N2SLD4 R1SLD4 N1SL4, N2SL4 N1SL4A R1SL4 N1SL16A, N2SL16A N3SL16A 16 17 16 15 17 15 11 15 17 10 20 17 1.0 1.0 1.0 1.0 1.0 1.0 0.5 1.0 1.0 0.5 1.1 0.9
Issue 02 (2007-03-29)
C-1
Board
Board
Power Consumption (W) 0 (before the TPS switching); 3 (after the TPS switching) 3 0 (before the TPS switching); 5 (after the TPS switching) 0 (before the TPS switching); 2 (after the TPS switching) 0 (before the TPS switching); 9 (after the TPS switching) 0 (before the TPS switching); 2 (after the TPS switching) 0 (before the TPS switching); 6 (after the TPS switching) 0
N1EU08
N1ETS8
N1MU04 N1OU08
2 6
0.4 0.4
N1TSB4 N1TSB8
0.3 0.3
N2OU08
0.4
N1C34S
0.3
N1EU04
0.4
N1D12S
0.4
R1L75S
0.3
N1D34S
0.4
R1L12S
0.2
N1D75S
0.4
N1DM12
0.5
N1D12B
0.3
N1ETF8
0.4
Data Processing Boards N1EGS4 N3EGS4 N2EGS4A N2EGR2 N2EGS2 N1EGT2 N2EMR0 N1EMS4 70 70 53 40 43 29 50 65 (without an interface board); 75 (with an interface board) 14 1.1 1.1 1.1 1.1 1.0 0.9 1.2 1.1 N1EFF8 N1EFS0 N2EFS0 N4EFS0 N1EFS4 N2EFS4 N1ADQ1 N1ADL4 6 35 35 35 30 30 41 41 0.4 1.0 1.0 1.0 1.0 1.0 1.0 0.9
R1EFT4
0.5
N1MST4
26
0.9
C-2
Issue 02 (2007-03-29)
Board
Board
N1EFT8 N1EFT8A
N1IDL4 N1IDQ1
Cross-connect and System Control Boards Q2CXL16 , Q2CXL4, Q2CXL1 40 1.1 R1CXLQ 4, R1CXLQ 1, R1CXLD 4, R1CXLD 1, R1CXLL1 6, R1CXLL4 , R1CXLL1 50 1.0
46
1.2
Other Boards N1LWX N1MR2B N1MR2C TN11MR 2 TN11MR 4 N1BA2 N1BPA N2BPA PIU, PIUA 30 0 0 0.2 0.2 20 20 11 2 1.1 1.0 1.0 0.9 0.9 1.0 1.0 1.2 1.3 TN11CM R2 TN11CM R4 N1FIB TN11OB U1 R1FAN AUX R1AMU EOW 0.2 0.2 0 16 20 19 8 10 0.8 0.9 0.4 1.3 1.0 1.0 0.5 0.4 -
Issue 02 (2007-03-29)
C-3
D
Product OptiX OSN 7500 Y N Y Y Y Y Y Y Y Y Y Y N Y Y Y N1SL64 N2SL64 T2SL64 T2SL64A N1SF64 N1SLD64 N1SL16 N2SL16 N3SL16 N1SL16A N2SL16A N3SL16A N1SLD16 N1SLQ16 N2SLQ16 N1SF16
Issue 02 (2007-03-29)
This chapter describes the version compatibility for each board. Table D-1 lists the board versions that are compatible with the OptiX OSN products. Table D-1 Board versions that are compatible with the OptiX OSN products OptiX OSN 3500 Y Y N N Y Y Y Y Y Y Y Y Y Y Y Y OptiX OSN 3500T Y Y N N Y Y Y Y Y Y Y Y Y Y Y Y OptiX OSN 2500 N N N N N N Y Y Y Y Y Y N N N Y OptiX OSN 2500 REG Y Y N N Y N N Y Y N N Y N N N Y OptiX OSN 1500A N N N N N N Y Y Y Y Y Y N N N Y OptiX OSN 1500B N N N N N N Y Y Y Y Y Y N N N Y
D-1
Product
N1SL4 N2SL4 N1SL4A R1SL4 N1SLQ4 N2SLQ4 N1SLQ4A N1SLD4 N2SLD4 N1SLD4A R1SLD4 N1SLT1 N1SLQ1 N2SLQ1 N1SLQ1A R1SLQ1 N1SL1 N2SL1 N1SL1A R1SL1 N1SLH1 N1SEP1 N2SLO1 R1PL1 R1PD1 R2PD1 N1PQ1 N2PQ1
D-2
Issue 02 (2007-03-29)
Product
N1PQM N1PL3 N2PL3 N1PL3A N2PL3A N1PD3 N2PD3 N2PQ3 N1DX1 N1DXA N1SPQ4 N2SPQ4 R1EFT4 N1EFT8 N1EFT8A N1EGT2 N1EFS0 N2EFS0 N4EFS0 N1EFS4 N2EFS4 N2EGS2 N1EMS4 N1EGS4 N2EGR2 N2EMR0 N1EAS2 N1ADL4
Issue 02 (2007-03-29)
D-3
Product
N1ADQ1 N1IDL4 N1IDQ1 N1MST4 N1EU08 N1OU08 N2OU08 N1D75S N1MU04 N1D34S N1C34S N1EU04 N1D12S N1D12B R1L12S R1L75S N1EFF8 N1ETF8 N1ETS8 N1DM12 N1TSB4 N1TSB8 Q2CXL1 Q3CXL1 Q2CXL4 Q3CXL4 Q2CXL16 Q3CXL16
D-4
Issue 02 (2007-03-29)
Product
T1GXCSA N1GXCSA T1EXCSA N1EXCSA T2UXCSA N1UXCSA N1UXCSB T1SXCSA T2SXCSA N1SXCSA N1SXCSB T1IXCSA N1IXCSA N1IXCSB N1XCE N1GSCC N2GSCC N3GSCC N4GSCC CRG T1EOW R1EOW T1AUX N1AUX R1AUX R2AUX R1AMU Q1SAP
Issue 02 (2007-03-29)
D-5
Product
Q2SAP Q1SEI N1FAN R1FAN N1FANA TN11CMR 2 TN11CMR 4 TN11MR2 TN11MR4 N1MR2A N1MR2B N1MR2C N1LWX TN11OBU1 N1FIB N1BA2 N1BPA N2BPA 61COA 62COA N1COA N1DCU N2DCU UPM T1PIU N1PIU Q1PIU
D-6
Issue 02 (2007-03-29)
Product
R1PIU R1PIUA
Issue 02 (2007-03-29)
D-7
E Board Loopbacks
E
Board Q2SL1 Q2SL4 Q2SL16 N1SL64 N2SL64 T2SL64 T2SL64A N1SF64 N1SLD64 N1SL16 N2SL16 N3SL16 N1SL16A N2SL16A N3SL16A N1SLD16 Port Inloop Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported.
Board Loopbacks
The SDH, PDH, data processing board for the OptiX OSN equipment support various types of loopbacks. In the case of the SDH boards for the OptiX OSN equipment, Table E-1 lists the capability of supporting the loopbacks. Table E-1 Loopbacks of the SDH boards for the OptiX OSN equipment Port Outloop VC-4 Inloop Supported. Supported. Supported. Supported. Not supported. Not supported. Not supported. Supported. Supported. Supported. Not supported. Supported. Supported. Not supported. Supported. Supported. VC-4 Outloop Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Supported. Supported. Not supported. Not supported. Supported. Not supported. Not supported. Supported. Supported.
Issue 02 (2007-03-29)
E-1
E Board Loopbacks
Board N1SLQ16 N2SLQ16 N1SF16 N1SL4 N1SL4A N2SL4 R1SL4 N1SLQ4 N1SLQ4A N2SLQ4 N1SLD4 N1SL4DA N2SLD4 R1SLD4 N1SLT1 N1SLQ1 N1SLQ1A N2SLQ1 R1SLQ1 N1SL1 N1SL1A N2SL1 R1SL1 N1SLH1 N1SEP1 N2SLO1
Port Inloop Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported.
Port Outloop Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported.
VC-4 Inloop Supported. Not supported. Supported. Supported. Supported. Not supported. Supported. Supported. Supported. Not supported. Supported. Supported. Not supported. Supported. Supported. Supported. Supported. Not supported. Supported. Supported. Supported. Not supported. Supported. Supported. Supported. Not supported.
VC-4 Outloop Supported. Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Not supported. Not supported.
In the case of the SDH boards for the OptiX OSN equipment, Table E-1 lists the capability of inserting the AUAIS to port.
E-2
Issue 02 (2007-03-29)
E Board Loopbacks
Table E-2 the capability of inserting the AUAIS to port Board insert the AUAIS to port (Port Inloop) Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Supported. Supported. Not supported. Not supported. Supported. Not supported. Not supported. Supported. Supported. Supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. insert the AUAIS to port (Port Outloop) Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. insert the AUAIS to port (VC-4 Inloop) Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Supported. Supported. Not supported. Not supported. Supported. Not supported. Not supported. Supported. Supported. Supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. insert the AUAIS to port(VC-4 Outloop) Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Supported. Supported. Not supported. Not supported. Supported. Not supported. Not supported. Supported. Supported. Supported. Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Supported. Not supported. Not supported.
Q2SL1 Q2SL4 Q2SL16 N1SL64 N2SL64 T2SL64 T2SL64A N1SF64 N1SLD64 N1SL16 N2SL16 N3SL16 N1SL16A N2SL16A N3SL16A N1SLD16 N1SLQ16 N2SLQ16 N1SF16 N1SL4 N1SL4A N2SL4 R1SL4 N1SLQ4 N1SLQ4A N2SLQ4 N1SLD4
Issue 02 (2007-03-29)
E-3
E Board Loopbacks
Board
insert the AUAIS to port (Port Inloop) Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported.
insert the AUAIS to port (Port Outloop) Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported.
insert the AUAIS to port (VC-4 Inloop) Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported.
insert the AUAIS to port(VC-4 Outloop) Supported. Not supported. Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Supported. Not supported. Not supported. Not supported. Not supported. Not supported.
N1SL4DA N2SLD4 R1SLD4 N1SLT1 N1SLQ1 N1SLQ1A N2SLQ1 R1SLQ1 N1SL1 N1SL1A N2SL1 R1SL1 N1SLH1 N1SEP1 N2SLO1
In the case of the PDH boards for the OptiX OSN equipment, Table E-3 lists the capability of supporting the loopbacks. Table E-3 Loopbacks of the PDH boards for the OptiX OSN equipment Board R1PL1 R1PD1 N1PQ1 N1PQM N1PD3 N1PL3 N2PQ3 N2SPQ4 Port Inloop Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Port Outloop Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported.
E-4
Issue 02 (2007-03-29)
E Board Loopbacks
In the case of the Ethernet boards for the OptiX OSN equipment, Table E-4 lists the capability of supporting the loopbacks. Table E-4 Loopbacks of the Ethernet boards for the OptiX OSN equipment Board MAC Layer Outloop Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. MAC Layer Inloop Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Not supported. Not supported. Not supported. Supported. Supported. Supported. Not supported. PHY Layer Outloop Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. PHY Layer Inloop Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. Supported. VC-4 Inloop, VC-4 Outloop Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. VC-3 Inloop, VC-3 Outloop Supported. Supported. Supported. Supported. Supported. Not supported. Supported. Supported. Supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported. Not supported.
N1EFS 4 N2EFS 4 N1EFS 0 N2EFS 0 N4EFS 0 N1EGT 2 N1EFT 8 N1EFT 8A R1EFT 4 N1EMS 4 N1EGS 4 N3EGS 4 N2EGR 2 N1EAS 2 N2EMR 0 N1MST 4
Issue 02 (2007-03-29)
E-5
E Board Loopbacks
In the case of the ATM/IMA boards for the OptiX OSN equipment, Table E-5 lists the capability of supporting the loopbacks. Table E-5 Loopbacks of the ATM/IMA boards for the OptiX OSN equipment Board N1ADL4 N1ADQ1 N1IDL4 N1IDQ1 External Port Outloop Not supported. Not supported. Not supported. Not supported. External Port Inloop Supported. Supported. Supported. Supported. Internal Port Outloop Supported. Supported. Supported. Supported. Internal Port Inloop Supported. Supported. Supported. Supported.
E-6
Issue 02 (2007-03-29)
The T2000 can be used to configure various parameters for SDH boards, PDH boards, data processing boards, and cross-connect and timing boards. F.1 SDH Processing Boards The parameters that can be configured for the SDH processing boards include the J0 byte, J1 byte and C2 byte. F.2 PDH Processing Board The parameters that can be set to the PDH processing boards include the J1 byte, C2 byte, J2 byte , V5 byte and tributary loopback. F.3 Data Processing Board The parameters that should be set for data processing boards include SDH parameters, Ethernet parameters and ATM parameters. F.4 Cross-Connect and Timing Unit The clock parameters should be set on the cross-connect and timing unit.
Issue 02 (2007-03-29)
F-1
J0 Byte
J0 is the section trace byte, the J0 are transmitted in a successive manner. Hence, the receive end learns that it is in the continuous connection with the specified transmit end. The value of J1 is "" by default.
J1 Byte
The J1 byte is the path tracing byte. The transmit end uses the J1 byte to transmit the higher order access point identifiers in a successive manner. Hence, the receive end learns that it is in the continuous connection with the specified transmit end in this channel. When the receive end detects the J1 mismatch, the corresponding VC-4 channel generates an HP_TIM alarm. Set the J1 byte as " HuaWei SBS
NOTE
" for the SL01 and as "" for all other boards.
". One space is present before "HuaWei SBS" and five behind.
C2 Byte
The C2 byte is the signal label byte, which is used to indicate the multiplexing structure of the VC frames and the payload property. The received C2 should be the same as the transmitted C2. If C2 mismatch occurs, the corresponding VC-4 channel generates the HP_SLM alarm. Table F-1 lists the mapping relation between the service type and setting of the C2. Table F-1 Mapping relation between the service type and setting of the C2 Input Service Type TUG structure 34M/45M asynchronously mapped into a C-3 140M asynchronously mapped into a C-4 Unequipped C2 Byte (in Hex) 02 04 12 00
J1 Byte
The J1 byte is the path tracing byte. The transmit end transmits the higher order access point identifiers in a successive manner. Hence, the receive end learns that it is in the continuous connection with the specified transmit end. When the receive end detects the J1 mismatch, the corresponding VC-4 channel generates an HP_TIM alarm. By default, the J1 byte is set to "".
NOTE
C2 Byte
The C2 byte is the signal label byte, which is used to indicate the multiplexing structure of the VC frames and the payload property. The received C2 should be the same as the transmitted C2. If C2 mismatch occurs, the corresponding VC-4 channel generates the HP_SLM alarm. Table F-2 lists the mapping relation between the service type and setting of the C2. Table F-2 Mapping relation between the service type and setting of the C2 Input Service Type TUG structure 34M/45M asynchronously mapped into a C-3 140M asynchronously mapped into a C-4 Unequipped C2 Byte (in Hex) 02 04 12 00
J2 Byte
The J2 is a VC-12 channel tracing byte. The transmit end uses the J2 byte to transmit the lower order access point identifiers in a successive manner. Hence, the receive end learns that it is in the continuous connection to the specified transmit end in this channel.
V5 Byte
The V5 is a channel status and signal identification byte. This byte is used to detect bit error and indicate remote faults or defect in lower order channel. The LP_REI and LP_RFI alarms are generated accordingly. Table F-3 lists the mapping relation between the service type and setting of the V5. Table F-3 Mapping relation between the service type and setting of the V5 Input Service Type Asynchronization
Issue 02 (2007-03-29)
Equipping Indication
When a service channel just carries the service and does not process the service, select Unequipped or Supervisory-Unequipped. When a service channel carries the service and also processes the service, select EquippedUnspecific Payload.
Tributary Loopback
The tributary loopback function is used to locate faults in the service channels. The tributary loopback is also a diagnosis function. When the tributary loopback is performed, related services are interrupted.
Select E1 or T1 for E1/T1 processing boards according to the actual service type in the channel. Select E3 or T3 for E3/T3 processing boards according to the actual service type in the channel.
Set the timing scheme of the DDN channels 1012 and 1416 to the DCE internal scheme, DCE slave scheme or DTE external scheme. Set the timing scheme of the DDN channels 9 and 13 to the DCE internal scheme, DCE slave scheme, DTE external scheme, DTE internal scheme, DTE slave scheme or DCE external scheme. By default, the timing scheme is the DCE internal scheme for channels 9 and 13 is the DCE internal scheme.
F.3.1 SDH Parameters The SDH parameters that should be set for data processing boards include the J1 byte, C2 byte, J2 byte and V5 byte. F.3.2 Ethernet Parameters The Ethernet parameters that should be set for the Ethernet boards include the working mode and LCAS state. F.3.3 ATM Parameter The ATM parameters that the ATM boards should be set include port type and flow type.
J1 Byte
The J1 byte is the path tracing byte. The transmit end transmits the J1 byte in a successive manner. Hence, the receive end learns that it is in the continuous connection to the specified transmit end in this path. When detecting the J1 mismatch, the receive end generates the LP_TIM_VC3 alarm in the VC-3 path and the HP_TIM in the VC-4 path. If the J1 byte is of the default value, "", these alarms are not reported.
NOTE
l l
For the N1EFS4 and MST4, the J1 byte is " HuaWei SBS " by default. For other boards, the J1 byte is "". For the EMS4 and EGS4, set the J1 byte as " HuaWei SBS ".
C2 Byte
The C2 byte is the signal label byte, which is used to indicate the multiplexing structure of the VC frames and the payload property. The received C2 should be the same as the transmitted C2. In case of the C2 mismatch, the LP_SLM alarm is generated in the VC-3 path and the HP_SLM alarm is generated in the VC-4 path.
J2 Byte
The J2 is a VC-12 path tracing byte. The transmit end uses the J2 byte to transmit the lower order access point identifiers in a successive manner. Hence, the receive end learns that it is in the continuous connection to the specified transmit end in this path. In case of the J2 mismatch, the LP_TIM_VC12 alarm is generated in the VC-12 path. If the J1 byte is of the default value, "", these alarms are not reported.
V5 Byte
The V5 is a path status and signal identification byte. This byte is used to detect bit error and indicate remote faults or defect in lower order path. The LP_REI and LP_RFI alarms are generated accordingly.
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When detecting the V5 mismatch, the receive end generates the LP_SLM_VC12 in the VC-12 path. Table F-4 lists the mapping relation between the service type and setting of the V5. Table F-4 Mapping relation between the service type and setting of the V5 Input Service Type Asynchronization Byte synchronization HDLC/PPP mapping Unequipped or Supervisory-Unequipped V5 Byte (in Hex) 02 04 0A 00
Working Mode
Generally, the interconnected equipment should work in the same fixed working mode. If the working modes at both ends mismatch, packets may be lost or the rate becomes less. In case of large volume of data, services may be even interrupted. For EAS2, set the working mode 10G full-duplex. For EGT2, EGS2 and EGS4, set the working mode to auto-negotiation or 1000M full-duplex. For the EFT8 and EFT8A, set the working mode to auto-negotiation or 10/100M full-duplex. For the EFS4 and EFS0, set the working mode to auto-negotiation, 10M half-duplex, 10M fullduplex, 100M half full-duplex or 100M full-duplex. For the GE ports of the EMS4, EMR0 and EGR2, set the working mode to auto-negotiation or 1000M full-duplex. For the FE ports, set the working mode to auto-negotiation, 10M half-duplex, 10M full-duplex, 100M half full-duplex or 100M full-duplex.
LCAS State
Enable or disable the LCAS.
Mapping Protocol
The mapping protocols of the interconnected equipment should be the same. For the EGT2, EFT8, EFT8A, EFF8 and ETF8, set the mapping protocol to HDLC, LAPS and GFP-F. By default, the mapping protocol is GFP-F.
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Choose the GFP-F mapping protocol for the EGS2, EFS4, EFS0 and EAS2. For the EMR0 and EGR2, set the mapping protocol to LAPS and GFP. By default, the mapping protocol is GFP-F. Choose the GFP-T mapping protocol for the MST4.
TAG Flag
The TAG flag is used to identify the type of packets. The TAG flag can be set to TAG Aware, Access and Hybrid. 1. 2. When the TAG flag is set as the TAG Aware for a port, the port transparently transmits the packets with a TAG and discards the packets without a TAG. When the TAG flag is set as Access for a port, the port adds a TAG to the received packets that does not contain any TAG according to the VLAN ID of the port, and discards the packets that contain a TAG. When the TAG flag is set as Hybrid for a port, the port can process the packets with a TAG or without any TAG. In this case, the port adds a TAG to the received packets that does not contain any TAG according to the VLAN ID of the port.
3.
VLAN ID
Set the default VLAN ID of the local port.
Port Type
For the boards that support the MPLS function, set the port type to P or PE. Provider edge (PE) indicates the edge port of the service provider and provider (P) indicates the core network port of the service provider. When configuring the EVPL and EVPLAN services, set this parameter. Set the external port to PE and the internal port to P.
Port Attribute
For boards that support the QinQ function, set the port attribute to UNI, NNI, U-NNI, S-Aware or C-Aware.
Port Type
The port types include NNI and UNI (default).
Flow Type
The flow type should meet the requirements of the port.
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Service Type
There are four service types, CBR, rt-VBR, nrt-VBR, and UBR.
Set the following parameters when the external clock is configured and the SSM is enabled.
l l l l l
Reference clock source Reference clock source level Building integrated timing supply (BITS) type S1 byte Threshold for selecting the clock in case of the switching protection
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G
This document defines the following terms: 1 1:N protection 1+1 protection 100Base-TX
Glossary
A 1:N protection architecture has N normal traffic signals, N working SNCs/trails and one protection SNC/trail. It may have one extra traffic signal. A 1+1 protection architecture has one normal traffic signal, one working SNC/trail, one protection SNC/trail and a permanent bridge. Physical Layer specification for a 100 Mbit/s CSMA/CD local area network over two pairs of Category 5 unshielded twisted-pair (UTP) or shielded twisted-pair (STP) wire. Physical Layer specification for a 10 Mb/s CSMA/CD local area network over two pairs of twisted-pair telephone wire. A cabinet which is 19 inches in width and 600mm in depth, compliant with the standards of the IEC297.
A Add/Drop Multiplexer ADM Administrator A multiplexer capable of extracting and inserting lower-rate signals from a higher-rate multiplexed signal without completely demultiplexing the signal. add/drop multiplexer. see add/drop multiplexer. A user who has authority to access all the Management Domains of the EML Core product. He has access to the whole network and to all the management functionalities. Alarm Indication Signal. A signal sent downstream in a digital network if an upstream failure has been detected and persists for a certain time. The cable which is used to transmit alarm signals.
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Alarm AMI
A visible or an audible indication to notify the person concerned that a failure or an emergency has occurred. See also Event. Alternate Mark Inversion. The line-coding format in transmission systems where successive ones (marks) are alternatively inverted (sent with polarity opposite that of the preceding mark). Avalanche Photodiode. A semiconductor photodetector with integral detection and amplification stages. Electrons generated at a p/n junction are accelerated in a region where they free an avalanche of other electrons. APDs can detect faint signals but require higher voltages than other semiconductor electronics. A network where transmission system payloads are not synchronized and each network terminal runs on its own clock. Asynchronous Transfer Mode. A transfer mode in which the information is organized into cells. It is asynchronous in the sense that the recurrence of cells containing information from an individual user is not necessarily periodic. It is a protocol within the OSI layer 1. An ATM cell consists of a 5 octet header followed by 48 octets of data. Reduction of signal magnitude or signal loss, usually expressed in decibels. A passive component that attenuates an electrical or optical signal. Property of an object. administrative unit. see administrative unit The rate/work mode of the communication party set as self-negotiation is specified through negotiation according to the transmission rate of the opposite party.
APD
Asynchronous ATM
B Back up Backplane Bandwidth A method to copy the important data into a backing storage in case that the original is damaged or corrupted. A PCB circuit board in the subrack, which is connected with all the boards in position. Information-carrying capacity of a communication channel. Analog bandwidth is the range of signal frequencies that can be transmitted by a communication channel or network. Building Integrated Timing Supply. A building timing supply that minimises the number of synchronization links entering an office. Sometimes referred to as a synchronization supply unit.
BITS
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A function that enables a board supporting several board IDs. Generally, a board of an old version is used to the NE also of an old version, which does not support the board of a new version. When a board of a new version is used to replace a board of an old version, the former should work with the ID of the board of the old version. The board of a new version works on the NE of a new version with the ID of the board of new version. In this way, the board of the new version has several board IDs. The action of transmitting identical traffic (SPE contents) on both the working and protection channels. The act of sending a frame addressed to all stations on the network
Bridge Broadcast
C Cable tie CBR The tape used to bind the cables. Constant Bit Rate. The Constant Bit Rate service category is used by connections that request a static amount of bandwidth that is continuously available during the connection lifetime. This amount of bandwidth is characterized by a peak cell Rate (PCR) value. Cell Delay Variation Tolerance. Information sent in the forward and backward direction to determine the upper bound of the tolerance admitted for the time interval between cells pertaining to a given cell flow. The backward CDVT values included in the IAM and MOD shall be interpreted as maximum acceptable values for the cell flow in the backward direction. The center to center difference in frequency or wavelength between adjacent channels in a WDM device. The smallest subdivision of a circuit that provides a type of communication service; usually a path with only one direction. A communications path or network; usually a pair of channels providing bi-directional communication. A kind of terminal (PC or workstation) connected to a network that can send instructions to a server and get results through a user interface. See also server. This is the STS-3 line code. This is a two level non-return to zero code. A binary 1 is coded by either of the amplitude levels, +A or -A, for one full unit time interval (T) in such a way that the level alternates for successive binary ones. For a binary zero there is always a positive transition (-A to +A) at the mid point of the binary unit interval (T/2).
CDVT
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Configuration data
The data that configures the NE hardware for coordination between this NE and other NEs in the entire network, and for operation of specified services. Configuration data is the instruction file of NEs, and it is a key element to ensure that the network runs efficiently. The typical configuration data includes board configuration, clock configuration and protection relationship. To set the basic parameters of an operation object. A "transport entity" which consists of an associated pair of "unidirectional connections" capable of simultaneously transferring information in opposite directions between their respective inputs and outputs. The process of developing a model of the echo path which will be used in the echo estimator to produce the estimate of the circuit echo. In the context of message handling, a transmittal event in which an MTA transforms parts of a message content from one encoded information type to another, or alters a probe so it appears that the described messages were so modified. A technique for using overhead bits to detect transmission errors.
Configure Connection
Convergence Conversion
D DDF Dense Wavelength Division Multiplexing Drop Digital Distribution Frame. A frame which is used to transfer cables. The higher capacity version of WDM, which is a means of increasing the capacity of fiber-optic data transmission systems through the multiplexing of multiple wavelengths of light. Commercially available DWDM systems support the multiplexing of from 8 to 40 wavelengths of light. The port on a network element where the service to an end customer may be connected, e.g., a tributary card on a SONET ADM. For example, a drop for a DS1 customer service may be provided by a VT1.5 card terminating a VT1.5 trail. A description of a ring that has entry nodes that add traffic to the ring via the bridging function. Dense Wavelength Division Multiplexing. The technology utilizes the characteristics of broad bandwidth and low attenuation of single mode optical fiber, employs multiple wavelengths with specific frequency spacing as carriers, and allows multiple channels to transmit simultaneously in the same fiber.
Dual-Fed DWDM
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E13 ECC
A funciton used to multiplex E1 signals into E3 signals or to demultipex E3 signals into E1 signals. Embedded Control Channel. An ECC provides a logical operations channel between SDH NEs, utilizing a data communications channel (DCC) as its physical layer. Erbium-Doped Fiber Amplifier. The optical amplifier that its fiber doped with the rare earth element erbium, which can amplify at 1530 to 1610 nm when the optical amplifier is pumped by an external light source. A component at the two ends of the front panel of a board, which is used for inserting or removing the board. In 1000BASE-X, the process by which a MAC packet is enclosed within a PCS code-group stream Ethernet Private Line. An EPL service is a point-to-point interconnection between two UNIs without SDH bandwidth sharing.Transport bandwidth is never shared between different customers. Enterprise System Connection. A path protocol which connects the host with various control units in an storage system. It is a serial bit stream transmission protocol. The transmission rate is 200 Mbit/s. Electrostatic discharge jack. A hole in the cabinet or subrack, which connect the subrack or cabinet to the insertion of ESD wrist strap. Electrostatic Discharge. The phenomena the energy being produced by electrostatic resource discharge instantly. A data link level protocol comprising the OSI model's bottom two layers. It is a broadcast networking technology that can use several different physical media, including twisted pair cable and coaxial cable. Ethernet usually uses CSMA/CD. TCP/IP is commonly used with Ethernet networks. European Telecommunications Standards Institute Ethernet Virtual Private Line. An EVPL service is a service that is both a line service and a virtual private service. A graphic presentation formed by the superimposition of the waveforms of all possible pulse sequences.
EDFA
ESCON
F Fan tray assembly Fault A module which contains fans used for heat dissipation. A fault is the inability of a function to perform a required action. This does not include an inability due to preventive maintenance, lack of external resources, or planned actions.
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G Glossary
FC Fiber connector
Fiber Channel. A standard of data storage network for transmitting signals at 100 Mbit/s to 4.25Gbit/s over fiber or (at slow speeds) copper. A device mounted on the end of a fiber-optic cable, light source, receiver, or housing that mates to a similar device to couple light into and out of optical fibers. A connector joins two fiber ends, or one fiber end and a light source or detector. The fiber which is used to connect the subrack with the ODF. Fibre Connect. A new generation connection protocol which connects the host with various control units. It carries single byte command protocol through the physical path of fiber channel, and provides higher rate and better performance than ESCON. An aggregation of packets that have the same characteristics. On the T2000 or NE software, flow is a group of classification rules. On boards, it is a group of packets that have the same quality of service (QoS) operation. At present, two flows are supported: port flow and port + VLAN flow. Port flow is based on port ID and port + VLAN flow is based on port ID and VLAN ID. The two flows cannot coexist in the same port. A cyclic set of consecutive time slots in which the relative position of each time slot can be identified. An operating condition of a clock, the output signal of which is strongly influenced by the oscillating element and not controlled by servo phaselocking techniques. In this mode the clock has never had a network reference input, or the clock has lost external reference and has no access to stored data, that could be acquired from a previously connected external reference. Free-run begins when the clock output no longer reflects the influence of a connected external reference, or transition from it. Free-run terminates when the clock output has achieved lock to an external reference. Pertaining to both parties that can send and receive data at the same time on the communication link.
Flow
Full duplex
G Gain The ratio between the optical power from the input optical interface of the optical amplifier and the optical power from the output optical interface of the jumper fiber, which expressed in dB. Consolidating or segregating traffic for efficiency. A groove in the subrack, which ensures the correct connection of a board to the backplane.
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Half duplex
Pertaining to, both parties that only one party can send data, while the other party can only receive data on the communication link.
I IMA frame The IMA frame is used as the unit of control in the IMA protocol. It is a logical frame defined as M consecutive cells, numbered 0 to M-l, transmitted on each of the N links in an IMA group. Inverse Multiplexing for ATM. The ATM inverse multiplexing technique involves inverse multiplexing and de-multiplexing of ATM cells in a cyclical fashion among links grouped to form a higher bandwidth logical link whose rate is approximately the sum of the link rates. This is referred to as an IMA group. The area for the interface boards on the subrack. A nonreciprocal optical device intended to suppress backward reflections along an optical fiber transmission line while having minimum insertion loss in the forward direction.
IMA
J Jitter Short waveform variations caused by vibration, voltage fluctuations, control system instability, etc.
L Label Laser A mark on a cable, a subrack, or a cabinet for identification. The device that generates the directional light covering a narrow range of wavelengths. Laser light is more coherent than ordinary light. Semiconductor diode lasers are the used light source in fiber-optic system. A concept used to allow the transport network functionality to be described hierarchically as successive levels; each layer being solely concerned with the generation and transfer of its characteristic information. Link Capacity Adjustment Scheme. A solution features flexible bandwidth and dynamic adjustment. In addition, it provides a failure tolerance mechanism, which enhances the viability of virtual concatenations and enables the dynamic adjustment to bandwidth (nonservice affecting).
Layer
LCAS
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Link
A "topological component" that provides transport capacity between two endpoints in different subnetworks via a fixed (i.e., inflexible routing) relationship. The endpoints are "subnetwork termination point pools" for SONET, and link termination points for ATM. Multiple links may exist between a pair of subnetworks. A link also represents a set of "link connections". The fault of each path on the optical fiber can be located by setting loopback for each path of the line. There are three kinds of loopback modes: No loopback, Outloop, Inloop. The subrack close to the bottom of the cabinet when a cabinet contains several subracks.
Loopback
Lower subrack
M M13 MAC Mapping Mean launched power Mounting ear MPLS A function used to multiplex T1 signals into T3 signals or to demultiplex T3 signals into T1 signals. Media Access Control. The data link sublayer that is responsible for transferring data to and from the Physical Layer. A procedure by which tributaries are adapted into virtual containers at the boundary of an SDH network. The average power of a pseudo-random data sequence coupled into the fiber by the transmitter. A component on the side of a subrack, which is used to install the subrack in a cabinet. Multiprotocol Label Switching. Multi-protocol label switching. It is a standard routing and switching technology platform, capable of supporting various high level protocols and services. The data transmission over an MPLS network is independent of route calculating. MPLS, as a connection-oriented transmission technology, guarantees QoS effectively, supports various network level technologies, and is independent of the link layer. The MSP function provides capability for switching a signal between and including two MST functions, from a working to a protection channel. Transmission of a frame to stations specified by a group address. A function provides capability for switching a signal between and including two MST functions, from a working to a protection channel. To transmit two or more signals over a single channel. An equipment which combines a number of tributary channels onto a fewer number of aggregate bearer channels, the relationship between the tributary and aggregate channels being fixed.
MSP
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Multiplexing
A procedure by which multiple lower order path layer signals are adapted into a higher order path or the multiple higher order path layer signals are adapted into a multiplex section.
N NNI Noise figure Non-revertive Network Node Interface. NNI identifies the interface between the ATM network nodes. Compare SDH NNI. The specification to scale the random signal in the system presenting in addition to any wanted signal. In non-revertive mode, when a protection switch occurs, the working service will be switched to the protection service and the status will remain after it returns normal. Non Return to Zero. A digital code in which the signal level is low for a 0 bit and high for a 1 bit and dose not return to 0 between successive 1 bits.
NRZ
O OADM Optical Add/Drop Multiplexer. A device that can be used to add the optical signals of various wavelengths to one channel and drop the optical signals of various wavelengths from one channel. Optical Distribution Frame. A frame which is used to transfer and spool fibers. Optical Network Element. A stand-alone physical entity in an optical transmission network that supports at least network element functions. A process that add the optical signals of various wavelengths to one channel and drop the optical signals of various wavelengths from one channel. A device or subsystem in which optical signals can be amplified by means of stimulated emission taking place in an suitable active medium. It is used to amplify the optical signal of the optical transmission system. A component normally attached to an optical cable or piece of apparatus for the purpose of providing frequent optical interconnection/ disconnection of optical fibers or cables. A device to allow two or more corresponding optical transmitting units to be connected. Optical Terminal Multiplexer. A device that multiplex or demultiplex optical signals into a transmission link or into the client side. Optical Transponder Unit. A device that access service signals compliant with standards at the client side and convert them into standard DWDM or CWDM wavelengths.
Optical connector
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The ranger of optical energy level of output signals. Extra bits in a digital stream used to carry information besides traffic signals. Orderwire, for example, would be considered overhead information.
P Packing case Paired Slots A case which is used for packing the board or subrack. Two slots of which the overheads can be passed through by using the bus on the backplane. When the SCC unit is faulty or offline, the overheads can be passed through between the paired slots by using the directly connected overhead bus. When two SDH boards form an MSP ring, the boards need to be inserted in paired slots so that the K bytes can be passed through. The action of transmitting by a node exactly what is received by that node for any given direction of transmission. A pass-through can be unidirectional or bidirectional. For BLSRs, a pass-through refers to the K1 and the K2 bytes and the protection channels. Three types of passthrough are used in BLSRs: K byte pass through, unidirectional full pass-through, and bidirectional full pass-through. The working principle of path protection: When the system works in path protection mode, the PDH path uses the dual-fed and signal selection mode. Through the tributary unit and cross-connect unit, the tributary signal is sent simultaneously to the east and west lines. Meanwhile, the cross-connect matrix sends the signal dually sent from the opposite end to the tributary board through the active and standby buses, and the hardware of the tributary board automatically and selectively receive the signal from the two groups of buses automatically according to the AIS number of the lower order path. A logical connection between the point at which a standard frame format for the signal at the given rate is assembled, and the point at which the standard frame format for the signal is disassembled. Peak Cell Rate. An upper limit on the rate at which cells can be submitted on an ATM connection. Plesiochronous Digital Hierarchy. PDH is the digital networking hierarchy that was used before the advent of Sonet/SDH. Photodiode. A semiconductor detector with an intrinsic (i) region separating the p- and n-doped regions. It has fast linear response and is used in fiber-optic receivers. A network with nodes timed by separate clock sources with almost the same timing.
Pass-Through
Path protection
Path
Plesiochronous
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Pointer
An indicator whose value defines the frame offset of a virtual container with respect to the frame reference of the transport entity on which it is supported. A direct current power distribution unit at the upper part of a cabinet, which supplies power for the subracks in the cabinet. When there are cross-connections between a line board and a tributary/ data board, many alarms are raised on the tributary/data board if alarms are raised on the line board. These alarms are all reported to the T2000. Such a large number of alarms can disturb the troubleshooting and affect the problem solution efficiency. Therefore, the inter-board alarm suppression function is used to solve this problem. Both communication parties are connected permanently. A generic term for an action. A generic term for a collection of actions. An area for the processing boards on the subrack. The process of making available various telecommunications resources (such as switching systems and transport facilities) for telecommunication services. Provisioning includes forecasting the demand for services, determining the additions or changes to the network that will be needed, determining where and when they will be needed, and installing all the necessary network elements to provide such services.
R Receiver overload Receiver sensitivity Reference clock Receiver overload is the maximum acceptable value of the received average power at point R to achieve a 1 x 10-10 BER. Receiver sensitivity is defined as the minimum acceptable value of average received power at point R to achieve a 1 x 10-10 BER. A clock of very high stability and accuracy that may be completely autonomous and whose frequency serves as a basis of comparison for the frequency of other clocks. A device that performs regeneration. The process of receiving and reconstructing a digital signal so that the amplitudes, waveforms and timing of its signal elements are constrained within specified limits. In revertive switching, there is a working and protection line, board and so on. Services always revert back to the original working line or board if the switch requests are terminated; that is, when the working line or board has recovered from the fault or the external request is cleared.
REG Regeneration
Revertive switching
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RPR
Resilient Packet Ring. A metropolitan area network (MAN) technology supporting data transfer among stations interconnected in a dual-ring configuration. In the asynchronous transfer mode and there is no hand-shaking signal. It can communicate with RS232 and RS422 of other stations in pointto-point mode and the transmission is transparent. Its highest speed is 19.2 kbit/s.
RS232
S S1 byte SAN The byte defined in ITU-T to transmit the network synchronization status information. Storage Area Network. A dedicated high-speed data storage network which interconnects multiple independent storage systems with multiple servers through fiber path switch or other switch equipment. Synchronous Digital Hierarchy. A hierarchical set of digital transport structures, standardized for the transport of suitably adapted payloads over physical transmission networks. The portion of a SONET transmission facility, including terminating points, between (i) a terminal network element and a regenerator or (ii) two regenerators. A terminating point is the point after signal regeneration at which performance monitoring is (or may be) done. Parameters of an operation that can be selected by the user. signal fail.See signal fail. small form-factor pluggable.see small form-factor pluggable. The ratio of the largest peak of the total source spectrum to the second largest peak. The panel on the side of the cabinet. The cable which is used to transmit electrical signals, different from the power cable or fiber. A signal indicating the associated data has failed in the sense that a nearend defect condition (not being the degraded defect) is active. SubNetwork Connection Protection. A working subnetwork connection is replaced by a protection subnetwork connection if the working subnetwork connection fails, or if its performance falls below a required level. Subnetwork Connection Multi-protection. The source broadcasts services to multiple paths, and the sink determines which service to receive according to the service priority and then the service quality.
SDH
Section
Settings SF SFP Side mode suppression ratio Side panel Signal cable Signal fail SNCP
SNCMP
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SNCTP
Subnetwork Connection Tunnel Protection. It provides protection paths at the VC-4 level. When the working path is faulty, all services in the working path are switched to the protection path. The set of SONET lines between two adjacent nodes on a ring. Synchronization Status Message. ITU-T defines S1 byte to transmit the network synchronization status information. It uses the lower four bits of the multiplex section overhead S1 byte to indicate 16 types of synchronization quality grades. A network where transmission system payloads are synchronized to a master (network) clock and traced to a reference clock.
Span SSM
Synchronous
T T2000 The T2000 is a subnet management system (SNMS). In the telecommunication management network architecture, the T2000 is located between the NE level and network level, which can supports all NE level functions and part of the network level management functions. See also NM. Tandem Connection Monitor. In the SDH transport hierarchy, the TCM is located between the AU/TU management layer and HP/LP layer. It uses the N1/N2 byte of POH overhead to monitor the quality of the transport channels on a transmission section (TCM section). Tributary Protection Switching. A function provided by the equipment, is intended to protect N tributary processing boards through a standby tributary processing board. A discal component in the cabinet, which is used to place the chassis or other equipment. A fault location method. A fault can be located for each service path by performing loopback on each path of the tributary board. There are three types of loopback modes: Non-loopback, Outloop and Inloop. tributary unit group.see tributary unit group.
TCM
TPS
U Upload Upper subrack To report all or part of the configuration data of the NE to the T2000 and overwrite the configuration data saved in the NE layer on the T2000. The subrack close to the top of the cabinet when a cabinet contains several subracks.
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G Glossary
Virtual concatenation
The payload whose transmission bandwidth is bigger than VC4. Virtual concatenation combines multiple VC4 payloads (successive or nonsuccessive) to form a virtual large structure VC4-Xv in cascade mode for transmission. The transmission of the broadband cascaded payload is implemented via the virtual cascade, thus improving the SDH transmission payload bandwidth capability from VC4 to VC4-4C. Virtual local area network. A subset of the active topology of a Bridged Local Area Network. Associated with each VLAN is a VLAN Identifier (VID). Virtual Private Network. Enables IP service to be transmitted securely over a public TCP/IP network by encrypting all service from one network to another.
VLAN
VPN
W Wavelength Division Multiplexing A means of increasing the capacity of fiber-optic data transmission systems through the multiplexing of multiple wavelengths of light. WDM systems support the multiplexing of as many as four wavelengths.
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H
A ADM AMI APS ATM B BITS C CAR CBR CC CMI COA CPU CRC D DC DCC DCE DCU DDF DTR
Add/Drop Multiplexer Alternate Mark Inversion Automatic Protection Switching Asynchronous Transfer Mode
Committed Access Rate Constant Bit Rate Continuity Check Coded Mark Inversion Case-shaped Optical Amplifier Central Processing Unit Cyclic Redundancy Check
Direct Current Data Communication Channel Data Circuit-terminal Equipment Dispersion Compensation Unit Digital Distribution Frame Data Terminal Ready
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H-1
DVB-ASI DWDM E ECC EDFA EMC EMI EPL EPLAN ESCON ETS ETSI EVPL EVPLAN F FC FE FEC FICON FPGA G GE GFP H HDB3 HDLC I IEEE IS-IS ITU-T
Embedded Control Channel Erbium-Doped Fiber Amplifier Electromagnetic Compatibility Electro Magnetic Interference Ethernet Private Line Ethernet Private LAN Enterprise Systems Connection European Telecommunication Standards European Telecommunications Standards Institute Ethernet Virtual Private Line Ethernet Virtual Private LAN
Fiber Channel Fast Ethernet Forward Error Correction Fiber Connection Field Programmable Gate Array
High Density Bipolar of order 3 code High level Data Link Control
Institute of Electrical and Electronics Engineers Intermedia System-Intermedia System International Telecommunication Union - Telecommunication Standardization Sector
H-2
Issue 02 (2007-03-29)
L LAPS LB LCAS LCT M MPLS MSP MLM N NA NRZ O OAM OSPF P PA PDH PRBS R RAM RD RIP RSTP S SDH SG SLM SNCP SNCMP SNCTP Synchronous Digital Hierarchy Signaling Ground Single- Longitudinal Mode Sub-Network Connection Protection Subnetwork Connection Multi-protection Subnetwork Connection Tunnel Protection Random-access Memory Receive Data Routing Information Protocol Rapid Spanning Tree Protocol Power Amplifier Plesiochronous Digital Hierarchy Pseudo-Random Binary Sequence Operation Administration and Maintenance Open Shortest Path First Not available Non Return to Zero Multi-protocol Label Switch Multiplex Section Protection Multi-Longitudinal Mode Link Access Procedure-SDH LoopBack Link Capacity Adjustment Scheme Local Craft Terminal
Issue 02 (2007-03-29)
H-3
Variable Bit Rate Virtual Local Area Network Virtual Private Network
H-4
Issue 02 (2007-03-29)
Index
Index
A
ADL4 configuration reference, 7-119 feature code, 7-119 front panel, 7-117 function and feature, 7-114 principle and signal flow, 7-115 technical specifications, 7-120 valid slots, 7-119 version, 7-114 ADQ1 configuration reference, 7-126 feature code, 7-126 front panel, 7-124 function and feature, 7-121 principle and signal flow, 7-122 technical specifications, 7-127 valid slots, 7-126 version, 7-121 AMU front panel, 10-17 function and feature, 10-15 principle and signal flow, 10-15 technical specification, 10-20 valid slot, 10-20 version, 10-15 AUX front panel, 10-11 function and feature, 10-7 principle and signal flow, 10-7 technical specification, 10-14 valid slot, 10-14 version, 10-6 version, 12-2 board barcode, 4-3 classification Amplifier, 4-12 Auxiliary, 4-10 Compensation, 4-12 Control, 4-10 Data, 4-7 Interface, 4-9 PDH, 4-6 Power, 4-12 SDH, 4-4 Switching, 4-9 WDM, 4-11 loopbacks, E-1 version configuration, D-1 BPA board feature code, 12-15 Front Panel, 12-13 function and feature, 12-11 principle and signal flow, 12-12 technical specification, 12-15 valid slot, 12-15 version, 12-10
C
C34S front panel, 8-25 function and feature, 8-24 principle and signal flow, 8-24 technical specification, 8-26 valid slot, 8-26 version, 8-24 cabinet configuration, 2-2 DC PDU, 2-3 indicator, 2-3 technical specifications, 2-5 type, 2-2 Cabinet Configuration Other, 2-4 CMR2
Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd i-1
B
BA2 board feature code, 12-8 front panel, 12-5 function and feature, 12-2 principle and signal flow, 12-3 technical specification, 12-9 valid slot, 12-8
Issue 02 (2007-03-29)
Index
feature code, 11-7 front panel, 11-5 function and feature, 11-3 principle and signal flow, 11-4 technical specification, 11-8 valid slot, 11-7 version, 11-3 CMR4 board feature code, 11-13 front panel, 11-11 function and feature, 11-9 principle and signal flow, 11-10 technical specification, 11-14 valid slot, 11-13 version, 11-9 COA board feature code, 12-27 front panel, 12-22 function and feature, 12-18 installation position, 12-26 principle and signal flow, 12-20 technical specification, 12-27 version, 12-17 CXL jumper, 9-65, 9-79, 9-93, 9-107 CXL1 board configuration reference, 9-18 board feature code, 9-18 front panel, 9-14 function and feature, 9-4 jumper, 9-12 principle and signal flow, 9-7 technical specification, 9-19 valid slot, 9-18 version, 9-3 CXL16 board configuration reference, 9-54 board feature code, 9-54 front panel, 9-50 function and feature, 9-40 principle and signal flow, 9-43 technical specification, 9-55 valid slot, 9-54 version, 9-39 CXL4 board configuration reference, 9-36 board feature code, 9-36 front panel, 9-32 function and feature, 9-22 jumper, 9-30 principle and signal flow, 9-25 technical specification, 9-37 valid slot, 9-36 version, 9-21 CXLD1 board configuration reference, 9-111 board feature code, 9-110 front panel, 9-108
i-2
function and feature, 9-99 principle and signal flow, 9-102 technical specification, 9-111 valid slot, 9-110 version, 9-99 CXLD4 board configuration reference, 9-125 board feature code, 9-124 front panel, 9-122 function and feature, 9-113 jumper, 9-121 principle and signal flow, 9-116 technical specification, 9-125 valid slot, 9-124 version, 9-113 CXLL1 board configuration reference, 9-69 board feature code, 9-68 front panel, 9-66 function and feature, 9-57 principle and signal flow, 9-60 technical specification, 9-69 valid slot, 9-68 version, 9-57 CXLL16 board configuration reference, 9-97 board feature code, 9-96 front panel, 9-94 function and feature, 9-85 jumper, 9-48 principle and signal flow, 9-88 technical specification, 9-97 valid slot, 9-96 version, 9-85 CXLL4 board configuration reference, 9-83 board feature code, 9-82 front panel, 9-80 function and feature, 9-71 principle and signal flow, 9-74 technical specification, 9-83 valid slot, 9-82 version, 9-71 CXLQ1 board configuration reference, 9-139 board feature code, 9-138 front panel, 9-136 function and feature, 9-127 jumper, 9-135 principle and signal flow, 9-130 technical specification, 9-139 valid slot, 9-138 version, 9-127 CXLQ4 board configuration reference, 9-153 board feature code, 9-152 front panel, 9-150 function and feature, 9-141
Issue 02 (2007-03-29)
Index
jumper, 9-149 principle and signal flow, 9-144 technical specification, 9-153 valid slot, 9-152 version, 9-141
E
EFF8 front panel, 8-52 function and feature, 8-51 principle and signal flow, 8-51 technical specification, 8-54 valid slot, 8-53 version, 8-51 EFS0 configuration reference, 7-38 front panel, 7-36 function and feature, 7-31 principle and signal flow, 7-33 technical specifications, 7-38 TPS protection, 7-37 valid slots, 7-37 version, 7-30 EFS4 configuration reference, 7-46 front panel, 7-44 function and feature, 7-39 principle and signal flow, 7-41 technical specifications, 7-46 valid slots, 7-46 version, 7-39 EFT4 configuration reference, 7-8 front panel, 7-6 function and feature, 7-3 principle and signal flow, 7-4 technical specifications, 7-8 valid slots, 7-8 version, 7-3 EFT8 configuration reference, 7-15 front panel, 7-12 function and feature, 7-9 principle and signal flow, 7-11 technical specifications, 7-15 valid slots, 7-14 version, 7-9 EFT8A configuration reference, 7-22 front panel, 7-19 function and feature, 7-16 principle and signal flow, 7-17 technical specifications, 7-22 valid slots, 7-22 version, 7-16 EGR2 configuration reference, 7-100 feature code, 7-100 front panel, 7-99
i-3
D
D12B front panel, 8-6 function and feature, 8-6 principle and signal flow, 8-6 technical specification, 8-9 valid slot, 8-8 version, 8-6 D12S front panel, 8-10 function and feature, 8-9 principle and signal flow, 8-10 technical specification, 8-13 valid slot, 8-12 version, 8-9 D34S front panel, 8-21 function and feature, 8-20 principle and signal flow, 8-21 technical specification, 8-22 valid slot, 8-22 version, 8-20 D75S front panel, 8-17 function and feature, 8-16 principle and signal flow, 8-16 technical specification, 8-20 valid slot, 8-19 version, 8-16 DM12 front panel, 8-65 function and feature, 8-64 principle and signal flow, 8-65 technical specification, 8-68 valid slot, 8-68 version, 8-64 DX1 board configuration reference, 6-71 board feature code, 6-69 front panel, 6-68 function and feature, 6-66 principle and signal flow, 6-66 technical specification, 6-71 TPS Protection, 6-70 valid slot, 6-69 version, 6-66 DXA board configuration reference, 6-76 front panel, 6-74 function and feature, 6-73 principle and signal flow, 6-73
Issue 02 (2007-03-29)
Index
function and feature, 7-93 principle and signal Flow, 7-96 technical specifications, 7-101 valid slots, 7-100 version, 7-93 EGS2 configuration reference, 7-54 feature code, 7-54 front panel, 7-52 function and feature, 7-48 principle and signal flow, 7-50 technical specifications, 7-55 valid slots, 7-54 version, 7-47 EGS4 configuration reference, 7-80 feature code, 7-77 front panel, 7-75 function and feature, 7-70 principle and signal flow, 7-72 protection, 7-77, 7-89 technical specifications, 7-81 valid slots, 7-77 version, 7-69 EGS4A configuration reference, 7-91 feature code, 7-89 front panel, 7-87 function and feature, 7-82 principle and signal flow, 7-84 technical specifications, 7-92 valid slots, 7-89 version, 7-82 EGT2 configuration reference, 7-28 feature code, 7-28 front panel, 7-26 function and feature, 7-23 principle and signal flow, 7-24 technical specifications, 7-29 valid slots, 7-28 version, 7-23 EMR0 configuration reference, 7-112 feature code, 7-112 front panel, 7-108 function and feature, 7-103 principle and pignal Flow, 7-106 technical Specifications, 7-112 valid slots, 7-111 version, 7-102 EMS4 configuration reference, 7-67 feature code, 7-64 front panel, 7-62 function and feature, 7-56 principle and signal flow, 7-59 protection, 7-64
i-4
technical specifications, 7-68 valid slots, 7-63 version, 7-56 EOW front panel, 10-4 function and feature, 10-2 principle and signal flow, 10-3 technical specification, 10-6 valid slot, 10-6 version, 10-2 ETF8 front panel, 8-56 function and feature, 8-55 principle and signal flow, 8-56 technical specification, 8-59 valid slot, 8-58 version, 8-55 ETS8 front panel, 8-61 function and feature, 8-60 principle and signal flow, 8-60 technical specification, 8-63 valid slot, 8-63 version, 8-60 EU04 front panel, 8-28 function and feature, 8-27 principle and signal flow, 8-27 technical specification, 8-30 valid slot, 8-29 version, 8-27 EU08 front panel, 8-32 function and feature, 8-31 principle and signal flow, 8-31 technical specification, 8-33 valid slot, 8-33 version, 8-31
F
FAN front panel, 10-21 function and feature, 10-20 principle and signal flow, 10-21 technical specification, 10-22 valid slot, 10-22 version, 10-20 FIB front panel, 11-59 function and feature, 11-58 principle and signal flow, 11-59 technical specification, 11-61 valid slot, 11-60 version, 11-58
Issue 02 (2007-03-29)
Index
I
IDL4 board protection, 7-134 configuration reference, 7-134 feature code, 7-134 front panel, 7-132 function and feature, 7-128 principle and signal flow, 7-130 technical specifications, 7-135 valid slots, 7-134 version, 7-128 IDQ1 configuration reference, 7-142 feature code, 7-142 front panel, 7-140 function and feature, 7-136 principle, 7-138 protection, 7-142 signal flow, 7-138 technical specifications, 7-143 valid slots, 7-142 version, 7-136 indicators alarm, A-2 cabinet, A-2
M
MR2 board feature code, 11-19 front panel, 11-17 function and feature, 11-16 principle and signal flow, 11-16 technical specification, 11-20 valid slot, 11-19 version, 11-16 MR2A front panel, 11-24 function and feature, 11-21 principle and signal flow, 11-23 technical specification, 11-25 valid slot, 11-25 version, 11-21 MR2B front panel, 11-29 function and feature, 11-27 principle and signal flow, 11-28 technical specification, 11-30 valid slot, 11-30 version, 11-27 MR2C front panel, 11-34 function and feature, 11-32 principle and signal flow, 11-33 technical specification, 11-36 valid slot, 11-36 version, 11-32 MR4 board feature code, 11-40 front panel, 11-39 function and feature, 11-37 principle and signal flow, 11-38 technical specification, 11-41 valid slot, 11-40 version, 11-37 MST4 configuration reference, 7-150 feature code, 7-149 front panel, 7-148 function and feature, 7-144 principle and pignal Flow, 7-146 technical specifications, 7-150 valid slots, 7-149 version, 7-144 MU04 front panel, 8-40 function and feature, 8-39 principle and signal flow, 8-40 technical specification, 8-42 valid slot, 8-41 version, 8-39
L
L12S front panel, 8-4 function and feature, 8-3 principle and signal flow, 8-3 technical specification, 8-5 valid slot, 8-5 version, 8-3 L75S front panel, 8-14 function and feature, 8-13 principle and signal flow, 8-14 technical specification, 8-15 valid slot, 8-15 version, 8-13 Label description, B-2 Position, B-3 Safety Label, B-2 LWX board feature code, 11-48 front panel, 11-46 function and feature, 11-43 principle and signal flow, 11-44 technical specification, 11-48 valid slot, 11-48 version, 11-43
Issue 02 (2007-03-29)
i-5
Index
O
OBU1 feature code, 11-56 front panel, 11-54 function and feature, 11-52 principle and signal flow, 11-53 technical specification, 11-56 valid slot, 11-56 version, 11-52 OU08 front panel, 8-36 function and feature, 8-35 principle and signal flow, 8-35 technical specification, 8-38 valid slot, 8-38 version, 8-34
P
PD1 board configuration reference, 6-17 board feature code, 6-14 front panel, 6-13 function and feature, 6-9 principle and signal flow, 6-10 technical specification, 6-17 TPS protection, 6-15 valid slot, 6-13 version, 6-9 PD3 board configuration reference, 6-57 front panel, 6-54 function and feature, 6-51 principle and signal flow, 6-51 technical specification, 6-57 TPS protection, 6-55 valid slot, 6-55 version, 6-50 PIU front panel, 13-9 function and feature, 13-8 principle and signal flow, 13-8 technical specifications, 13-11 valid slot, 13-10 version, 13-8 PIUA front panel, 13-13 function and feature, 13-12 principle and signal flow, 13-12 technical specifications, 13-14 valid slot, 13-14 version, 13-11 PL1 board configuration reference, 6-7 board feature code, 6-7 front panel, 6-6
i-6
function and feature, 6-3 principle and signal flow, 6-4 technical specification, 6-8 valid slot, 6-7 version, 6-3 PL3 board configuration reference, 6-42 front panel, 6-39 function and feature, 6-36 principle and signal flow, 6-36 technical specification, 6-42 TPS protection, 6-40 valid slot, 6-40 version, 6-35 PL3A board configuration reference, 6-49 front panel, 6-47 function and feature, 6-44 principle and signal flow, 6-45 technical specification, 6-49 valid slot, 6-48 version, 6-43 power consumption and weight, C-1 PQ1 board configuration reference, 6-26 board feature code, 6-24 front panel, 6-22 function and feature, 6-19 principle and signal flow, 6-20 technical specification, 6-26 TPS protection, 6-24 valid slot, 6-23 version, 6-18 PQ3 board configuration reference, 6-64 front panel, 6-61 function and feature, 6-58 principle and signal flow, 6-59 technical specification, 6-65 TPS protection, 6-63 valid slot, 6-62 version, 6-58 PQM board configuration reference, 6-34 front panel, 6-31 function and feature, 6-27 principle and signal flow, 6-28 technical specification, 6-34 TPS protection, 6-32 valid slot, 6-32 version, 6-27
S
SEP1 configuration reference, 5-53 front panel, 5-50 function and feature, 5-46
Issue 02 (2007-03-29)
Index
principle and signal flow, 5-47 technical specifications, 5-54 TPS Protection, 5-52 valid slot, 5-52 version, 5-46 SF16 configuration reference, 5-118 front panel, 5-116 function and feature, 5-113 principle and signal flow, 5-114 technical specifications, 5-118 valid slots, 5-118 version, 5-113 SL1 board configuration reference, 5-9 board feature code, 5-9 front panel, 5-7 function and feature, 5-4 principle and signal flow, 5-5 technical specification, 5-9 valid slot, 5-8 version, 5-3 SL16 board feature code, 5-102 configuration reference, 5-102 front panel, 5-100 function and feature, 5-97 principle and signal flow, 5-98 technical specifications, 5-102 valid slot, 5-102 version, 5-96 SL16A board feature code, 5-110 configuration reference, 5-111 front panel, 5-109 function and feature, 5-105 principle and signal flow, 5-106 technical specifications, 5-111 valid slot, 5-110 version, 5-105 SL1A Board Configuration Reference, 5-15 Board Feature Code, 5-15 Front Panel, 5-14 Function and Feature, 5-11 Principle and Signal Flow, 5-12 Technical Specifications, 5-15 Valid Slots, 5-15 version, 5-11 SL4 board feature code, 5-60 configuration reference, 5-61 front panel, 5-58 function and feature, 5-55 principle and signal flow, 5-56 technical specifications, 5-61 valid slot, 5-60 version, 5-55
Issue 02 (2007-03-29)
SL4A Board Configuration Reference, 5-67 Board Feature Code, 5-67 Front Panel, 5-65 Function and Feature, 5-63 Principle and Signal Flow, 5-64 Technical Specifications, 5-67 Valid Slots, 5-67 Version Description, 5-63 SLD4 board feature code, 5-75 configuration reference, 5-75 front panel, 5-73 function and feature, 5-70 principle and signal flow, 5-71 technical specifications, 5-76 valid slots, 5-74 version, 5-69 SLD4A Board Configuration Reference, 5-81 Board Feature Code, 5-81 Front Panel, 5-79 Function and Feature, 5-78 Principle and Signal Flow, 5-78 Technical Specifications, 5-81 Valid Slots, 5-81 Version Description, 5-77 SLO1 board feature code, 5-37 configuration reference, 5-37 front panel, 5-35 function and feature, 5-32 principle and signal flow, 5-34 technical specifications, 5-38 valid slot, 5-37 version, 5-32 slot allocation, 3-4, 3-13 SLQ1 board configuration reference, 5-23 feature Code, 5-23 front panel, 5-21 function and feature, 5-18 principle and signal flow, 5-19 technical specification, 5-24 valid slot, 5-22 version, 5-17 SLQ1A Board Configuration Reference, 5-30 Board Feature Code, 5-30 Front Panel, 5-28 Function and Feature, 5-26 Principle and Signal Flow, 5-27 Technical Specifications, 5-30 Valid Slots, 5-30 Version Description, 5-26 SLQ4 board feature code, 5-88
i-7
Index
configuration reference, 5-89 front panel, 5-87 function and feature, 5-84 principle and signal flow, 5-85 technical specifications, 5-89 valid slot, 5-88 version, 5-83 SLQ4A Board Configuration Reference, 5-94 Board Feature Code, 5-94 Front Panel, 5-93 Function and Feature, 5-91 Principle and Signal Flow, 5-92 Technical Specifications, 5-95 Valid Slots, 5-94 Version Description, 5-90 SLT1 configuration reference, 5-44 front panel, 5-42 function and feature, 5-39 principle and signal flow, 5-40 technical specifications, 5-44 valid slot, 5-44 version, 5-39 SPQ4 board configuration reference, 6-85 front panel, 6-82 function and feature, 6-77 principle and signal flow, 6-78 technical specification, 6-85 TPS protection, 6-84 valid slot, 6-83 version, 6-77 Subrack Structure, 3-2 subrack capacity, 3-3 technical specifications, 3-24
U
UPM function and feature, 13-2 principle and signal flow, 13-4 rear panel, 13-4 technical specifications, 13-6 valid slot, 13-6
T
TSB4 Front Panel, 8-44 Function and Feature, 8-43 Principle, 8-43 Signal Flow, 8-43 Technical Specifications, 8-45 Valid Slots, 8-45 Version, 8-43 TSB8 front panel, 8-47 function and feature, 8-46 principle and signal flow, 8-46 technical specification, 8-50 valid slot, 8-48 version, 8-46
i-8
Issue 02 (2007-03-29)