Designing with the UCC28600 Quasi-Resonant Flyb

This worksheet is designed for use with Microsoft Excel 5.0 or later. Its use is intended to assist power supply des routine, day-to-day calculations.

Component values are calculated as ideal, not to nearest production values

Disclaimer
This product is designed as an aid for customers of Texas Instruments. No warranties, either express or implied, with respect to this software or its fitness for any particular purpose is claimed by Texas Instruments or the author. The software is licensed solely on an "as is" basis. The entire risk as to its quality and performance is with the customer.

-Resonant Flyback Converter

2005 Rev. 1.0

ntended to assist power supply designers in their

ents. No warranties, either express ar purpose is claimed by Texas s is" basis. The entire risk as to its

QR Design Tool Instructions

Be sure to Enable the Macros and to have a check in the AnalysisT oolPak box in the Add-Ins section of the Tools menu. Quasi-Resonant (QR) flyback converter design is an iterative process. This design tool reduces the hardware iterations by simulating the steady state operating maps that show the converter modes under different input and load conditions. Design adjustments can be explored in order to optimize the power system. Although the design spreadsheet is organized around a bridge rectifier bulk capacitor line rectifier, it can be used for fixed output Power Factor Corrector (PFC) or voltage follower PFC systems. Systems with PFC must allow the QR flyback stage to start-up under the low ac line condition. However, the steady state conduction losses to the QR flyback stage will only occur at the PFC bulk capacitor voltage levels. To use this tool, enter the voltages, power levels and converter estimates into the appropriate spaces of the QR Design Tool worksheet. This step also requires an initial selection of the power MOSFET and the output rectifier. Enter data in the cells with the BLUE text; the calculated values are in the cells with the RED text. The parameters for the UCC28600 are already included. The design tool will generate a recommended design that includes transformer parameters. Verify that the current and voltage stresses are compatible with the MOSFET and output rectifier that were initially selected. The recommended values in the design may not be practical due to integer transformer turns, standard values, etc. Yet the operation of the converter can be significantly altered by using the closest parameter. At this point, design the transformer using the magnetizing inductance and approximate turns ratio that was recommended by the QR Design Tool worksheet. The Magnetic Specification sheet can be printed and used as a guideline for the recommended transformer design. The next step is to see how the design performs using the QR Simulator worksheet. The QR Simulator will carry over the Converter Requirements, MOSFET Specifications, Diode Data and the UCC28600 Characteristics. The transformer information and the programming components, RS (current sense resistance), RPL (power limit programming), ROVP1 and ROVP2 (over-voltage programming resistors) must be entered by the user. The recommended values are shown beside the cells as a reminder for the ideal values. After entering the final values, examine the operating maps. They reveal the boundaries of the different modes of operation. The operating maps portray the power levels, peak switch currents, feed back voltages and switching frequencies for the full array of line voltages and loads that the converter would experience. These maps can be used to explore design alternatives, such as different current sense resistor values, different transformers, etc. For example, it might be desirable to change the power level where burst mode occurs in order to avoid audio noise at a common load operating point. The QR Simulator worksheet also shows rms currents, whether the converter is in power limit, the operational mode among other potentially useful data that can be used to optimize For PFC systems that have a fixed bulk voltage, estimate the PFC output voltage at the peak of its ripple. Calculate the equivalent ac voltage to achieve that maximum voltage level. Enter that ac voltage as the VAC(max) level. Enter the minimum operational ac line voltage as the VAC(min) level because the QR Flyback must power up correctly in order to start the PFC stage. For voltage follower PFC systems, estimate the PFC output voltage at the peak of its ripple during maximum line conditions. Calculate the equivalent ac voltage to achieve that maximum voltage level. Enter that ac voltage as the VAC(max) level. Enter the minimum ac line voltage as the VAC(min) level because the QR Flyback must power up correctly in order to start the PFC stage. In the least, converter must be designed to operate at safe temperatures under the steady state operating rms currents that occur at the minimum PFC voltage and at the maximum PFC voltage. The data tables in the QR Simulator worksheet can assist in finding the required values.

of the Tools menu.

UCC28600 Design Spreads

Design Synthesis - type in the blue data and the spreads

Converter Requirements
POUT(max) limit POUT, during soft start efficiency ratio PIN = VAC(min) 120 W 120 W 0.96 125.000 W 230 VAC VBULK(min_pk) = 325.269 RLOAD during SS = 4.800

VAC(max) **

264 VAC

VBULK(min_valley) =

260.215

VBULK(ripple), %pp VAC(max) shutdown margin %

20 %

VBULK(max_pk) =

373.352

10 %

VBULK(ov) =

410.688

fS(max),

value must be between 40kHz and 130kHz, default value should be 130kHz VOUT VOUT(ripple), max pp

130.0E+3

Hz, high line, max load

TS(min) =

7.692E-6

24 VDC 0.12 V

VOUT(shutdown)

28 V

Load step, Watts max dVOUT due to Load step

100 W 0.5 V

estimated fCO, Hz

3.0E+3 Hz

VBIAS at full load

19.4 V

Snubber overshoot % of reflected VOUT

50 %

MOSFET Specifications VDS(max) rating VDS derate % VDS(max) limit = COSS estimate, at VDS test V Co', F-sqrt(V) = CDS, stray CISS Qg Transformer Estimates Leakage to magnetizing inductance % 1.5 %mag Ind Leakage to magnetizing inductance ratio = 0.015 650 V 15 % 552.5 V 40.0E-12 F 2.00E-10 F 25.0E-12 F 1.6E-9 F 60E-9 C VDS test V 25

Diode Estimates VF 0.670 V

UCC28600 Parameters VFB, no load

4.87 V, = VREF in chip, @ no load

RFB VFB at Burst/FFM boundary ACS(FB) VCS(OS), CS offset volts VPL, power limit VPL - VCS(OS) VFB @ power limit VFB at FFM boundary fQR(max) clamp fQR(min) clamp IOVP(line) VOVP(on), ON state VOVP(load) IPL(CS)/IOVPon), current gain during OUT = ON state VCS at DCM/FFM IP/IP(max) at DCM/FFB boundary VCO gain, TS/VFB VCO offset, TS(VFB = 0) ISS(chg)

20.0E+3 W, internal to chip 1.4 V 2.5 Gain, VFB/VCS 0.4 V, typ value from data sheet 1.2 V, typical CS value during power limit 0.8 V, CS working range 3 V, VPL X ACS(FB) 2V 130.0E+3 Hz 40.0E+3 Hz 450.0E-6 A, Line OVP typical value in data sheet 0 V, typ VOVP OUT = HIGH 3.75 V, Load OVP typical value in data sheet 0.5 150 mA/300 mA 0.4 V, (VFB/ACS(FB)) - VCS(OS) 0.5 -28.8E-6 65.4E-6 V 6.00E-06 A, SS charge current

Resulting Converter Features VXFMR, reflect VDS1(OS) ZVS at VAC(min_valley)? ZVS at VAC(max_pk)? COSS @ VAC(min) CDS(total) @ VAC(min) COSS @ VAC(max) CDS(total) @ VAC(max) RLOAD, reflect to pri tON / sqrt(L) tLEAKAGE / sqrt(L) tOFF / sqrt(L) tVALLEY / sqrt(L) min NPRI / NSEC min NPRI / NBIAS 119.432 V 59.716 V FALSE FALSE 6.4E-12 F 31.4E-12 F 5.2E-12 F 30.2E-12 F 114.112 W 117.5E-6 s 1.0E-6 s 367.2E-6 s 17.3E-6 s 4.841 turns, N = VXFMR/(VOUT+VF) 5.989 turns, NBIAS = N*(VOUT/VBIAS)

max L at VAC(max) LLEAKAGE(max) Total L input 1+ROVP1/ROVP2 ROVP1 ROVP2

233.9E-6 H 3.5E-6 H 237.4E-6 H 6.180 152.4E+3 W 29.4E+3 W

Ideal Design Using MIN NPRI / NSEC and MAX L over VAC Ra
VBULK: the voltage across Trial: the step number the bulk for the coresponding capacitor, input voltage test iterations begin condition at the minimum valley voltage Trial 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VBULK V 260.215 265.872 271.529 277.186 282.843 288.500 294.156 299.813 305.470 311.127 316.784 322.441 328.098 333.754 339.411 345.068 350.725 356.382 362.039 367.696 373.352 VAC(equiv): the correspondin g AC input voltage that would result in VBULK VAC(equiv) V 184.000 188.000 192.000 196.000 200.000 204.000 208.000 212.000 216.000 220.000 224.000 228.000 232.000 236.000 240.000 244.000 248.000 252.000 256.000 260.000 264.000 ZVS ?: if TRUE, converter is zero voltage switching, if FALSE, converter is Valley switching ZVS ? FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE CDS, total: total drain to source capacitance

CDS, total F 37.8E-12 37.6E-12 37.5E-12 37.3E-12 37.2E-12 37.0E-12 36.9E-12 36.8E-12 36.7E-12 36.6E-12 36.5E-12 36.3E-12 36.2E-12 36.1E-12 36.0E-12 35.9E-12 35.8E-12 35.8E-12 35.7E-12 35.6E-12 35.5E-12

Summary of Maximum Load at Minim

At VAC(min) IP1 3.160 A

ICS1 At VAC(max) IP2 ICS2

143E-6 A 2.876 A 205E-6 A

RS and RPL Values to Achieve IP and ICS

RCS

0.210 W

VRcs, peak

0.663

RPL

960.18E+0 W

VRpl, min line

0.137

Snubber Components and Parameters, Primary-Side Voltage Clamping CSNUB TSNUB RSNUB1 RSNUB2 Output Capacitor COUT ESR, max IC(out), rms @ low line IC(out), rms @ high line 1.628E-9 F 169.02E-9 s 11.63E+3 W 46.423 W PRsnub1 2.019

2.78E-3 F 7.84E-3 W 5.165 A 4.694 A

Soft Start always no-load start? tSS, minimum CSS, minimum

FALSE 21.26E-3 s 63.77E-9 F

Summary of Ideal Converter Components

Xfmr

LPRI(terminal) LPRI(leakage) NPRI/NSEC IPRI(rms) IPRI(peak) ISEC(rms) @ low line ISEC(rms) @ high line

237.4E-6 H 3.5E-6 H 4.841 turns ratio 1.006 ARMS 3.160 APEAK 7.189 6.858 ARMS, for nonPFC design ARMS, for PFC design

MOSFET

VDS rating VDS stress ID(rms)

650 V 552.5 V 1.006 A 2.8E-3 F 7.8E-3 W 5.165 ARMS 4.694 ARMS

Output capacitor

COUT ESR, max rms current rating @ low line rms current rating @ high line VF IAVERAGE IRMS IPEAK PDISSIPATE VBLOCK

Output Diode

0.67 V 5.000 A 7.189 A 15.298 A 3.350 W 101.120 V 209.8E-3 W 0.319 W 960.2E+0 W

R current sense

RCS maximum power RPL CSNUB RSNUB1 PRsnub1 RSNUB2

R power limit R2CD snubber

1.6E-9 F 11.6E+3 W 2.019 W 46.423 W

OVP

ROVP1 ROVP2

152.4E+3 W 29.4E+3 W 63.8E-9 F 21.3E-3 s 51.6E-6 F 11.13 W 10.4E+6 W

Soft start

CSS tSS

Minimum VDD Capacitor Series resistor Start up resistor

CVDD RVDD RSU

CC28600 Design Spreadsheet

blue data and the spreadsheet responds with the calculated red data.
Comments on REQUIRED USER INPUTS:

ALL CELLS WITH BLUE TEXT MUST BE VERIFIED AND UPDATED BY THE USER FOR EACH DESIGN.
- POUT(max) limit is maximum output power of converter (enter, in W, into cell C10) W, VOUT2/POUT during SS - POUT during SS, default: use POUT(max) if design will start into full load (enter, in W, into cell C11) - efficiency ratio is the Expected converter efficiency (enter, in decimal form, in cell C12) V, VAC(min)2 - Resultant input power from User input (calculated by spreadsheet) - VAC(min) is the minimum AC line input voltage (enter, in VAC, in cell C14) - **For systems with a PFC front end, the VAC(max) value entered into cell C15 should be equivalent to the maximum regulated output voltage of the PFC stage divided by SQRT(2), as calculated by the USER, otherwise, for systems that DO NOT have a PFC input stage, enter the maximum AC line input voltage. (enter, in VAC, in cell C15) - VBULK(ripple), %pp is the ripple voltage on the input voltage (enter the percentage of peak to peak ripple voltage on the input bus in cell C16) - VAC(max) shutdown margin % is the User programmable Line Over Voltage Protection limit (enter the percentage of margin that the line voltage can exceed VAC(max) before initiating Line OVP, in cell C17) - For systems that wish to utilize the full range of the controller, most designs, enter 130E+3 (for the 130kHz max switching frequency of the UCC28600) into cell C18; for designs that do not wish to use the full range of modes, enter a value less than 130kHz but greater than 40kHz (default value entered into cell C18 should be 130E+3). Enter frequency, in Hertz, in cell C18. - VOUT is the regulated output voltage of the converter (enter, in Volts, in cell C19) - VOUT(ripple), max pp is the maximum peak to peak output ripple of the converter output, i.e. usually equal to 1% of the regulated output voltage (enter, in Volts, in cell C20) - VOUT(shutdown) is the User programmable Output Over Voltage Protection limit (enter, in Volts, the maximum output voltage that will initiate Load OVP in cell C21) - Load step is the maximum output load transient, in Watts, i.e. no-load to full load (enter, in Watts, in cell C22) - max dVOUT due to Load step is the maximum output voltage deviation due to a transient or load step (enter, in Volts, in cell C23)

V, minus ripple

V, VAC(max)2

V, plus ripple

- estimated fCO is the desired crossover frequency of the control loop, usually between 2kHz and 3kHz (enter, in Hertz such as 3.0E+3, in cell C24) - VBIAS is the output of the Aux winding of the Flyback Transformer, used to BIAS the UCC28600 and, if used, also the PFC controller. VBIAS must be equal to the maximum UVLO stop threshold of the UCC28600 (equal to 9.3V) or the maximum start up voltage of the PFC controller, whichever is greater. (enter, in Volts, in cell C25) - Snubber overshoot % of reflected VOUT is used to determine the snubber components. The percentage value entered in this cell will be used to determine the clamp voltage, taking into account the derated VDS of the switch, the maximum input voltage, and the reflected output voltage. Recommended 50% as default value. (enter, as a percentage, in cell C26)

The User selects a MOSFET for the design and inputs the FET's characteristics: - VDS(max) rating is the chosen FET's drain to Source maximum voltage rating (enter, as Volts, in cell C30) - VDS derate % is the User chosen derating (for safety margin) of the VDS voltage on the FET (enter, as a percentage, in cell C31) - Resultant maximum allowed voltage on switch due to User selected derating - COSS is the output capacitance of the chosen MOSFET as stated in the MOSFET data sheet (enter, in Farads, in cell C33). VDS test V is the defined voltage, found in the MOSFET data sheet, that the COSS specification is tested at (enter, in Volts, in cell F33). - CDS, stray is the estimated parasitic Drain to Source capacitance (enter, in Farads, in cell C35) ex.TO-220 tab to GND is about 25 pF - CISS is the input capacitance of the chosen MOSFET as stated in the MOSFET data sheet (enter, in Farads, in cell C36). - Qg is the total gate charge of the chosen MOSFET as stated in the MOSFET data sheet (enter, in Cou;ombs, in cell C37).

- Leakage to magnetizing inductance % is the desired magnetizing inductance of the Flyback transformer (enter, as a percent, in cell C39)

- VF is the forward voltage drop of the User-selected output rectifier as found in the rectifier data sheet (enter, as a voltage, in cell C43)

Internal IC parameters

- The parameters within the blue box are internal to the UCC28600 and are not User programmable.

Note: RS and RPL and the snubber follow simulation because the results are used in their calculation. - calculated allowable reflected output voltage - calculated Drain-Source overshoot voltage - TRUE only if VXFMR,reflect > VBULK(min_valley), FALSE = valley switching - TRUE only if VXFMR,reflect > VBULK(max_pk), FALSE = valley switching

- calaculated circuit capacitances

- calculated maximum load impedance based upon the reflected output voltage

- calculated timing segments normalized with respect to the primary inductance

- min NPRI / NSEC is the Minimum Turns Ratio for the Primary to Secondary Windings (this value is carried over to the Simulator page) - min NPRI / NBIAS is the Minimum Turns Ratio for the Primary to Bias (AUX) Windings (this value is inverted and carried over to the Simulator page)

- max L at VAC(max) is the Calculated Primary Inductance (this value is carried over to the Simulator page) - LLEAKAGE(max) is the Allowable Leakage Inductance (this value is carried over to the Simulator page)

- ROVP1 is the ideal value of the top resistor on the OVP pin (this value is adjusted for actual turns ratio and carried over to the Simulator page) - ROVP2 is the ideal value of the bottom resistor on the OVP pin (this value is adjusted for actual turns ratio and carried over to the Simulator page)

d MAX L over VAC Range @ MAX Load

IPEAK: calculated peak primary current at maximum load taking into account operating mode IPEAK A 3.160 3.140 3.121 3.103 3.085 3.068 3.052 3.036 3.021 3.007 2.993 2.979 2.966 2.954 2.941 2.930 2.918 2.907 2.897 2.886 2.876 TON: calculated on time at maximum load TS: calculated switching IPRI(rms): primary period at side rms current maximum load TDEMAG: time required for the inductor to demagnetize at maximum load ISEC(rms): secondary side rms current at maximum load

TON s 2.841E-6 2.763E-6 2.689E-6 2.619E-6 2.552E-6 2.488E-6 2.427E-6 2.369E-6 2.314E-6 2.261E-6 2.210E-6 2.162E-6 2.115E-6 2.070E-6 2.027E-6 1.986E-6 1.947E-6 1.908E-6 1.872E-6 1.836E-6 1.802E-6

TS s 9.344E-6 9.226E-6 9.114E-6 9.008E-6 8.906E-6 8.808E-6 8.715E-6 8.626E-6 8.541E-6 8.459E-6 8.381E-6 8.306E-6 8.233E-6 8.164E-6 8.097E-6 8.032E-6 7.970E-6 7.910E-6 7.852E-6 7.796E-6 7.742E-6

IPRI(rms) A, rms 1.006 0.992 0.979 0.966 0.953 0.941 0.930 0.919 0.908 0.897 0.887 0.877 0.868 0.859 0.850 0.841 0.833 0.825 0.817 0.809 0.801

TDEMAG s 6.190E-6 6.151E-6 6.113E-6 6.077E-6 6.043E-6 6.010E-6 5.978E-6 5.947E-6 5.918E-6 5.889E-6 5.862E-6 5.836E-6 5.810E-6 5.785E-6 5.762E-6 5.739E-6 5.716E-6 5.695E-6 5.674E-6 5.654E-6 5.634E-6

ISEC(rms) A, rms 7.19 7.17 7.14 7.12 7.10 7.08 7.06 7.05 7.03 7.01 7.00 6.98 6.96 6.95 6.94 6.92 6.91 6.90 6.88 6.87 6.86

y of Maximum Load at Minimum and Maximum Line

- IP1 is the peak primary current at low line, full load

- ICS1 is the power limit current that is sourceed at the CS pin at low line - IP2 is the peak primary current at high line, full load - ICS2 is the power limit current that is sourceed at the CS pin at high line

PRcs

0.319 W

- the ideal value of the Current Sense resistor (RCS), the peak voltage across it (VRcs, peak), and the power dissipated by it (PRcs). RCS is adjusted for actual turns ratio and carried over to the QR Simulator page where the User must select a standard value. - the ideal value of the Power Limit Resistor (RPL), the peak voltage across it at minimum line (VRpl, min line), and the peak voltage across it at maximum line (VRpl, max line). RPL is adjusted for actual turns ratio and carried over to the QR Simulator page where the User must select a standard value.

VRpl, max line

0.196 V

- CSNUB is the ideal value of the primary side snubber capacitor. Select a standard value close to this. - TSNUB is the period of the ringing frequency W - RSNUB1 is the ideal value of the snubber resistor that is in parallel to CSNUB, PRsnub1 is the power dissipation of RSNUB1. Select a standard value close to this. - RSNUB2 is the ideal value of the snubber resistor that is in series with CSNUB. Select a standard value close to this.

- COUT is the ideal value of the output capacitor. Select a standard value close to this. - Select a capacitor bank (COUT) with a total ESR less than this. - Select a capacitor bank (COUT) to handle IC(out),rms at low line. - Select a capacitor bank (COUT) to handle IC(out),rms at high line.

- tSS, minimum is the required soft start time - CSS, minimum is the rewquired capacitor fo SS. Select astandard value close to this.

- LPRI(terminal) is the required primary inductance. LPRI is carried over to the QR Simulator page where the User must select a standard value. - LPRI(leakage) is the maximum allowable leakage inductance. LPRI(leakage) is carried over to the QR Simulator page where the User must select a standard value. - NPRI/NSEC is the ideal primary to secondary turns ratio. NPRI/NSEC is carried over to the QR Simulator page where the User must enter the actual turns used. - IPRI(rms) is the primary rms current at low line, maximum load - IPRI(peak) is the peak primary current at low line, maximum load - ISEC(rms) @ low line is the maximum secondary side rms current at low line for designs without a PFC front end - ISEC(rms) @ high line is the maximum secondary side rms current at high line for designs with a PFC front end - VDS rating is the voltage rating on the User selected MOSFET - VDS stress is the resultant maximum allowed voltage on switch due to User selected derating - ID(rms) is the maximum primary rms current - COUT is the ideal value of the output capacitor. Select a standard value close to this. - ESR, max is the maximum allowable equivalent series resitance of the output capacitor bank - rms current rating at low line is the required rms ripple current rating for low line operation of designs that do not use a PFC front end - rms current rating at high line is the required rms ripple current rating for low line operation of designs that use a PFC front end - VF is the forward voltage drop of the selected diode - IAVERAGE is the average output current - IRMS is the RMS output current - IPEAK is the PEAK output current - PDISSIPATE is the calculated power dissipation of the output diode - VBLOCK is the required reverse voltage rating of the diode - RCS is the ideal value of the Current Sense resistor - maximum power is the calculated dissipated power across the current sense resistor - RPL is the ideal value of the power limit resistor - CSNUB is the ideal value of the primary side snubber capacitor. Select a standard value close to this. - RSNUB1 is the ideal value of the snubber resistor that is in parallel to CSNUB, Select a standard value close to this. - PRsnub1 is the power dissipation of RSNUB1. - RSNUB2 is the ideal value of the snubber resistor that is in series with CSNUB. Select a standard value close to this.

- ROVP1 is the ideal value of the top resistor on the OVP pin - ROVP2 is the ideal value of the bottom resistor on the OVP pin - CSS, minimum is the required capacitor fo SS. Select astandard value close to this. - tSS, minimum is the required soft start time - CVDD is the minimum required value for the bulk capacitor on VDD - RVDD is the series resistor from the Bias windings into VDD - RSU is the start up resistor from the bulk input into VDD

.
INPUTS:

BE VERIFIED AND ACH DESIGN.

nter, in W, into cell C10) into full load (enter, in W,

ter, in decimal form, in cell

eadsheet) AC, in cell C14)

e entered into cell C15 ut voltage of the PFC otherwise, for systems mum AC line input

e (enter the percentage of

e Line Over Voltage ne voltage can exceed

oller, most designs, enter he UCC28600) into cell modes, enter a value less ed into cell C18 should

ter, in Volts, in cell C19)

ripple of the converter tage (enter, in Volts, in cell

ltage Protection limit (enter, d OVP in cell C21)

ts, i.e. no-load to full load

ltage deviation due to a

control loop, usually in cell C24)

nsformer, used to BIAS the st be equal to the to 9.3V) or the maximum r. (enter, in Volts, in cell

ermine the snubber ll be used to determine the switch, the maximum input 50% as default value.

the FET's

mum voltage rating (enter,

rgin) of the VDS voltage on

ser selected derating as stated in the MOSFET e defined voltage, found in ted at (enter, in Volts, in

pacitance (enter, in F stated in the MOSFET

ated in the MOSFET data

magnetizing inductance of

ut rectifier as found in the

CC28600 and are not User

use the results are used in

alley switching

y switching

flected output voltage

he primary inductance

imary to Secondary e)

imary to Bias (AUX) imulator page)

nce (this value is carried

s value is carried over to

P pin (this value is adjusted ge)

OVP pin (this value is ulator page)

D: duty cycle

D 0.304 0.299 0.295 0.291 0.287 0.282 0.278 0.275 0.271 0.267 0.264 0.260 0.257 0.254 0.250 0.247 0.244 0.241 0.238 0.236 0.233

Current Sense resistor e across it (VRcs, peak), ed by it (PRcs). RCS is ns ratio and carried over to e where the User must e.

Power Limit Resistor e across it at minimum line he peak voltage across it at ax line). RPL is adjusted nd carried over to the QR the User must select a

standard value close to

UB,

PRsnub1 is the power a standard

NUB. Select

close to this.

close to this.

QR Simulator page where carried over to the QR

ed over to the QR

ne for designs without a

line for designs with a PFC

User selected derating

close to this. output capacitor bank for low line operation of

g for low line operation of

sense resistor

standard value close to Select a standard value

UB,

NUB. Select

a standard

lose to this.

UCC28600 Analysis Sp

Design Simulation - type in the blue data and

Note: The converter requirements and recommended component values have been carried over fr

TYPE IN STANDARD COMPONENT VALUES IN THE BLUE CELLS FOR MODE CHARTS
Converter Requirements:
POUT POUT, during soft start Efficiency ratio PIN VAC(min) VAC(max) VBULK(ripple), %pp VAC(max) shutdown margin % fS(max) VOUT VOUT(ripple), max pp VOUT, shut-down Load step, Watts max dVOUT due to load step estimated fCO, Hz VBIAS at full load Snubber overshoot % of reflected VOUT 120 W 120 W 0.96 125.000 W 230 VAC 264 VAC 20 % 10 % 130.0E+3 Hz 24 V 0.12 V 28 V 100 W 0.5 V 3.0E+3 Hz 19.4 V 50 % RLOAD during SS 4.800

VBULK(min_pk) VBULK(min_valley) VBULK(max_pk) VBULK(shutdown) TS(min)

325.269 260.215 373.352 410.688 7.69E-06

MOSFET Specifications:
VDS(max) rating VDS derate % VDS(max) limit COSS estimate, at VDS = 25 V Co', F-sqrt(V) CDS, stray 650 V 15 % 552.5 V 40.0E-12 F 200.0E-12 F 25.0E-12 F VDS test V 25 Actual derating % 21.003

Diode Data:
VF 0.670 V

Transformer Data

Actual Leakage to magnetizing inductance % (from magnetic manufacturer's drawing spec) Actual LM (from magnetic manufacturer's drawing spec). The recommended primary inductance is shown in cell E42, carried over from the QR Design page. LLEAKAGE Total L, primary

2.5 %

300.0E-6 H

Leakage to magnetizing inductance ratio Recommended LM carried over from QR Design page and shown for the User's convenience in cell E42

0.025

233.9E-6

7.5E-6 H 307.5E-6 H

Input the actual Primary to Secondary Turns Ratio, from the magnetic manufacturer's drawing spec, into cell B47. This value should very closely match the recommended turns ratio calculated on the QR Design Tool sheet and shown for the User's convenience in cell E47 of this sheet.

NPRI/NSEC (from magnetic manufacturer's drawing spec)

5.680 turns ratio

4.841

VXFMR, reflect

140.126 V

Recommended VXFMR, reflect

119.4

Input the actual Primary to Bias Turns Ratio, from the magnetic manufacturer's drawing spec, into cell B50. This value should very closely match the recommended turns ratio calculated on the QR Design Tool sheet and shown, for the User's convenience, in cell E50 of this sheet.

NPRI/NBIAS

4.000

5.989

Sense Resistors & Power Limit

Recommended values, carried over from the QR Design Tool page and adjusted for the actual turns ratio are shown in cells D54 through D57. The User must insert the closest standard value for each component in cells B54 through B57, iterating until the recommended values no longer selfadjust (usually 2-3 iterations are all that are needed)

RCS, current sense RPL, power limit ROVP1 ROVP2

0.350 1.40E+03 133.0E+3 29.4E+3

W W W W

0.229 6.08E+02 228.2E+3 23.1E+3

W W W W

UCC28600 Parameters VFB, no load RFB VFB at Burst/FFM boundary ACS(FB) VCS(OS), CS offset volts VPL, power limit VPL - VCS(OS) VFB @ power limit VFB at FFM boundary fQR(max) clamp fQR(min) clamp IOVP(line) VOVP(on), ON state VOVP(load) IPL(CS)/IOVPon), current gain during OUT = ON state VCS at DCM/FFM IP/IP(max) at DCM/FFB boundary VCO gain, TS/VFB VCO offset, TS(VFB = 0) ISS(chg)

4.87 V, = VREF in chip, @ no load 20.0E+3 1.4 2.5 0.4 1.2 0.8 3 2 130.0E+3 40.0E+3 450.0E-6 W, internal to chip V Gain, VFB/VCS V, typ value from data sheet V, typical CS value during power limit V, CS working range V, VPL X ACS(FB)

V Hz Hz A, Line OVP typical value in data sheet 0 V, typ VOVP OUT = HIGH

3.75 V, Load OVP typical value in data sheet 0.5 150 mA/300 mA 0.4 V, (VFB/ACS(FB)) - VCS(OS) 0.5 -28.8E-6 65.4E-6 V 6.00E-06 A, SS charge current

Operation Characteristics o
VBULK Trial Recommended with Turns ADJ 0 20 0 1 2 3 4 5 6 7 8 V 260.215 373.352 260.215 265.872 271.529 277.186 282.843 288.500 294.156 299.813 305.470 VAC, equiv. V 184.000 264.000 184.000 188.000 192.000 196.000 200.000 204.000 208.000 212.000 216.000 IP, actual A 2.848 2.565 2.848 2.828 2.809 2.791 2.773 2.756 2.740 2.724 2.709

Actual with Real Values

9 10 11 12 13 14 15 16 17 18 19 20 Min line Max line

311.127 316.784 322.441 328.098 333.754 339.411 345.068 350.725 356.382 362.039 367.696 373.352 260.215 373.352

220.000 224.000 228.000 232.000 236.000 240.000 244.000 248.000 252.000 256.000 260.000 264.000 184.000 264.000

2.695 2.681 2.668 2.655 2.642 2.630 2.618 2.607 2.596 2.585 2.575 2.565 2.848 2.565

Operation Characteristics of Design

VBULK(min) PLOAD/PRATED 1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0.01 260.215 V Pload W 120 114 108 102 96 90 84 78 72 66 60 54 48 42 36 30 24 18 12 6 1.2 PLINE W 125.000 118.750 112.500 106.250 100.000 93.750 87.500 81.250 75.000 68.750 62.500 56.250 50.000 43.750 37.500 31.250 25.000 18.750 12.500 6.250 1.250 Vac, equiv Mode QR QR QR QR QR DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM

Operation Characteristics of Design

VBULK(min) 373.3523805 V VAC, equiv

PLOAD/PRATED 1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0.01

Pload W 120 114 108 102 96 90 84 78 72 66 60 54 48 42 36 30 24 18 12 6 1.2

PLINE W 125.000 118.750 112.500 106.250 100.000 93.750 87.500 81.250 75.000 68.750 62.500 56.250 50.000 43.750 37.500 31.250 25.000 18.750 12.500 6.250 1.250

Mode QR QR DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM DCM FFB

Trial 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Actual Power Limit, as Programmed by Actual RPL, ROVP1 & ROVP2 V VBULK fS PIN(limit) V Hz W 260.215 209.1E+3 54.963 265.872 213.8E+3 54.379 271.529 218.6E+3 53.770 277.186 223.4E+3 53.137 282.843 228.4E+3 52.482 288.500 233.5E+3 51.804 294.156 238.8E+3 51.105 299.813 244.1E+3 50.386 305.470 249.6E+3 49.648 311.127 255.3E+3 48.890 316.784 261.1E+3 48.115 322.441 267.1E+3 47.323 328.098 273.2E+3 46.514 333.754 279.6E+3 45.689 339.411 286.1E+3 44.849 345.068 292.9E+3 43.994 350.725 299.8E+3 43.124 356.382 307.0E+3 42.241 362.039 314.5E+3 41.345 367.696 322.2E+3 40.436 373.352 330.3E+3 39.514

00 Analysis Spreadsheet

he blue data and it responds with the red data.

The USER MUST LUE CELLS FOR THE SIMULATOR TO GENERATE THE DESIGN SPECIFIC MODE CHARTS
Input Power vs Switching Frequency
140

ve been carried over from the QR Designer Tool page and are shown in RED.

W
120

V V V V s PIN - Input Power - W

100

80

60

40

20

0 0 20 40 60 80

fS - Switching Frequency - kHz

Input Low Line Input High Line Power Limit

Primary Current vs Switching Frequency

%
3.0

V
2.5

Primary Current - A

2.0

1.5

1.0

IP - Primary Current H

1.0

0.5

0.0 0 20 40 60 80 100

fS - Switching Frequency - kHz

Rated Power Input Low Line Input High Line

Feedback Voltage vs Switching Frequency

5.00 4.50

VFB - Feedback Voltage - V

Recommended NPRI/NSEC turns ratio

4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 20 40 60 80 100

Recommended NPRI/NBIAS turns ratio

fS - Switching Frequency - kHz

Rated Power Input Low Line Input High Line

In regards to the above Mode Plots: The green shaded region represents the Green Mode area of opera where the controller applies packets of 40kHz pulses to the MOSFET gate. The frequency shown is actua the average switching frequency of the 40kHz packets of pulses while in this region. Ideally, a design wi transition from Green mode into Frequency Foldback mode (FFM) at approximately 10% load. From FFM, increasing load, the converter will either operate in Discontinuous Mode (DCM) at which point the frequency be fixed at 130kHz, or transition directly into Quasi-Resonant mode (QR) where the frequency will decrea with increasing load. Due to the limitaions of this QR Simulator spreadsheet. the Mode plots do NOT accurately show the internal 40kHz clamp of Quasi-Resonant operation. As shown below, once the switch frequency hits the internal 40kHz minimum frequency clamp, the operating frequency will begin to increase increasing load, dependent upon line and load conditions.

where the controller applies packets of 40kHz pulses to the MOSFET gate. The frequency shown is actua the average switching frequency of the 40kHz packets of pulses while in this region. Ideally, a design wi transition from Green mode into Frequency Foldback mode (FFM) at approximately 10% load. From FFM, increasing load, the converter will either operate in Discontinuous Mode (DCM) at which point the frequency be fixed at 130kHz, or transition directly into Quasi-Resonant mode (QR) where the frequency will decrea with increasing load. Due to the limitaions of this QR Simulator spreadsheet. the Mode plots do NOT accurately show the internal 40kHz clamp of Quasi-Resonant operation. As shown below, once the switch frequency hits the internal 40kHz minimum frequency clamp, the operating frequency will begin to increase increasing load, dependent upon line and load conditions.

fsw

Switching Frequency

SS Mode (fixed fSW)

QR Mode (Valley f = Oscillator Switching) MAX Frequency (130 kHz)

DCM (maximum fs)

FFM (VS)

Green Mode This mode applies bursts of 40kHz soft-start pulses to the power MOSFET gate. The average fsw is shown in this operating mode. fGRMODE_MX (40 kHz)

fSS (40kHz)

fQR_MIN : internally limited to 40 kHz. Hysteretic transition into Burst Mode.

VFB

Feedback Voltage

POUT

Load Shown is slightly less than Over Current Threshold

Load Power
IC Off Softstart

VSTATUS

Regular Operation

Fixed Frequency

Frequency Foldback

Green Mode

Status, pulled up to VDD

Green Mode, PFC bias OFF

ation Characteristics of Design Using LM and LLEAK at Full Rated Power

TS, actual s 9.976E-6 8.094E-6 9.976E-6 9.837E-6 9.705E-6 9.579E-6 9.459E-6 9.344E-6 9.235E-6 9.130E-6 9.030E-6 TON, actual s 3.365E-6 2.113E-6 3.365E-6 3.271E-6 3.181E-6 3.096E-6 3.015E-6 2.938E-6 2.864E-6 2.794E-6 2.727E-6 fS, actual Hz 100.2E+3 123.6E+3 100.2E+3 101.7E+3 103.0E+3 104.4E+3 105.7E+3 107.0E+3 108.3E+3 109.5E+3 110.7E+3 Power Limit? FALSE FALSE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE VFB V 2.845 2.777 4.348 4.349 4.351 4.354 4.357 4.361 4.365 4.370 4.376

8.934E-6 8.842E-6 8.753E-6 8.668E-6 8.587E-6 8.508E-6 8.433E-6 8.360E-6 8.290E-6 8.222E-6 8.157E-6 8.094E-6 9.976E-6 8.094E-6

2.664E-6 2.603E-6 2.544E-6 2.488E-6 2.434E-6 2.383E-6 2.333E-6 2.286E-6 2.240E-6 2.196E-6 2.154E-6 2.113E-6 3.365E-6 2.113E-6

111.9E+3 113.1E+3 114.2E+3 115.4E+3 116.5E+3 117.5E+3 118.6E+3 119.6E+3 120.6E+3 121.6E+3 122.6E+3 123.6E+3 100.2E+3 123.6E+3

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

4.382 4.388 4.395 4.402 4.410 4.418 4.426 4.435 4.444 4.453 4.463 4.473 4.348 4.473

aracteristics of Design using LM and LLEAK at Low Line

184 V IP actual A 2.848 2.711 2.573 2.436 2.298 2.166 2.092 2.016 1.937 1.855 1.768 1.678 1.582 1.479 1.370 1.250 1.118 0.969 0.791 0.559 0.250 fS actual Hz 100.2E+3 105.1E+3 110.5E+3 116.5E+3 123.1E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 TON s 3.365E-6 3.203E-6 3.041E-6 2.878E-6 2.716E-6 2.559E-6 2.473E-6 2.383E-6 2.289E-6 2.192E-6 2.090E-6 1.982E-6 1.869E-6 1.748E-6 1.619E-6 1.478E-6 1.322E-6 1.145E-6 934.519E-9 660.805E-9 295.521E-9 VCS V 1.339 1.291 1.243 1.195 1.147 1.100 1.075 1.048 1.020 0.992 0.961 0.930 0.896 0.860 0.822 0.780 0.734 0.681 0.619 0.538 0.430 VFB V 4.348 4.228 4.108 3.987 3.867 3.751 3.687 3.620 3.551 3.479 3.403 3.324 3.240 3.151 3.054 2.950 2.835 2.703 2.548 2.345 2.075

aracteristics of Design Using LM and LLEAK at High Line

264 V

IP actual A 2.565 2.442 2.372 2.306 2.237 2.166 2.092 2.016 1.937 1.855 1.768 1.678 1.582 1.479 1.370 1.250 1.118 0.969 0.791 0.559 -0.261

fS actual Hz 123.6E+3 129.5E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 130.0E+3 119.6E+3

TON s 2.113E-6 2.012E-6 1.954E-6 1.899E-6 1.842E-6 1.784E-6 1.723E-6 1.661E-6 1.595E-6 1.528E-6 1.456E-6 1.382E-6 1.303E-6 1.219E-6 1.128E-6 1.030E-6 921.122E-9 797.715E-9 651.331E-9 460.561E-9 -214.737E-9

VCS V 1.389 1.346 1.322 1.298 1.274 1.249 1.224 1.197 1.169 1.140 1.110 1.078 1.045 1.009 0.971 0.929 0.883 0.830 0.768 0.687 0.400

VFB V 4.473 4.365 4.304 4.246 4.185 4.123 4.059 3.992 3.923 3.851 3.775 3.696 3.612 3.523 3.427 3.322 3.207 3.076 2.920 2.717 1.977

Actual RPL, ROVP1 & ROVP2 Values IPRI(rms) ARMS 0.429 0.419 0.409 0.399 0.389 0.379 0.370 0.360 0.351 0.342 0.333 0.324 0.315 0.307 0.298 0.290 0.282 0.273 0.265 0.257 0.249

ISEC(rms) ARMS 3.321 3.277 3.231 3.185 3.138 3.090 3.042 2.993 2.944 2.894 2.843 2.792 2.741 2.689 2.636 2.584 2.530 2.477 2.422 2.368 2.313

D.

The USER MUST ESIGN SPECIFIC

ing Frequency

100

120

140

Power Limit

hing Frequency

100

120

140

Power Limit

hing Frequency

100

120

140

kHz
Input High Line

represents the Green Mode area of operation SFET gate. The frequency shown is actually s while in this region. Ideally, a design will ) at approximately 10% load. From FFM, with Mode (DCM) at which point the frequency will ode (QR) where the frequency will decrease tor spreadsheet. the Mode plots do NOT eration. As shown below, once the switching operating frequency will begin to increase with nd load conditions.

fs, actual fs, actual (kHz) fs, actual (kHz) for (kHz) for for Rated P Input Low Line Map Input High map 1, 2, 3 1, 2, 3 Line Map 1, 2, 3

SFET gate. The frequency shown is actually s while in this region. Ideally, a design will ) at approximately 10% load. From FFM, with Mode (DCM) at which point the frequency will ode (QR) where the frequency will decrease tor spreadsheet. the Mode plots do NOT eration. As shown below, once the switching operating frequency will begin to increase with nd load conditions.

VS)

Green Mode This mode applies bursts of 40kHz soft-start pulses to the power MOSFET gate. The average fsw is shown in this operating mode. fGRMODE_MX (40 kHz)

100 102 103 104 106 107 108 110 111 112 113 114 115 116 118 119 120 121 122 123 124

100 105 111 116 123 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130

124 129 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 120

etic n into ode.

Foldback

Green Mode

Green Mode, PFC bias OFF

IPRI(rms) ARMS 0.955 0.757 0.955 0.941 0.928 0.916 0.904 0.892 0.881 0.870 0.860

ISEC(rms) ARMS 7.392 7.015 7.392 7.366 7.341 7.317 7.294 7.272 7.251 7.230 7.210 ZVS ? FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE CDS, total 3.792E-11 3.555E-11 3.792E-11 3.775E-11 3.760E-11 3.745E-11 3.730E-11 3.716E-11 3.703E-11 3.690E-11 3.678E-11

resonant leakage

resonant

time TL1=Tr / (2pi) f, reset, Hz 1.686E-08 1.633E-08 1.686E-08 1.683E-08 1.679E-08 1.676E-08 1.673E-08 1.670E-08 1.667E-08 1.664E-08 1.661E-08 1.474E+06 1.522E+06 1.474E+06 1.477E+06 1.480E+06 1.483E+06 1.486E+06 1.489E+06 1.491E+06 1.494E+06 1.497E+06

0.850 0.840 0.830 0.821 0.812 0.804 0.795 0.787 0.779 0.771 0.764 0.757 0.955 0.757

7.191 7.172 7.154 7.137 7.120 7.104 7.088 7.072 7.058 7.043 7.029 7.015 7.392 7.015

FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE

3.666E-11 3.654E-11 3.643E-11 3.632E-11 3.621E-11 3.611E-11 3.601E-11 3.591E-11 3.581E-11 3.572E-11 3.563E-11 3.555E-11 3.792E-11 3.555E-11

1.658E-08 1.655E-08 1.653E-08 1.650E-08 1.648E-08 1.646E-08 1.643E-08 1.641E-08 1.639E-08 1.637E-08 1.635E-08 1.633E-08 1.686E-08 1.633E-08

1.499E+06 1.501E+06 1.504E+06 1.506E+06 1.508E+06 1.510E+06 1.513E+06 1.515E+06 1.517E+06 1.519E+06 1.520E+06 1.522E+06 1.474E+06 1.522E+06

fs, actual (kHz) for Power Limit Map 1, 2

209 214 219 223 228 234 239 244 250 255 261 267 273 280 286 293 300 307 315 322 330

TR, dMAG(valley) residue dMAG(l) VV, valley VDS seconds 3.392E-07 3.284E-07 3.392E-07 3.385E-07 3.378E-07 3.371E-07 3.365E-07 3.358E-07 3.352E-07 3.346E-07 3.341E-07 Amps 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 Volts 1.201E+02 2.332E+02 1.201E+02 1.257E+02 1.314E+02 1.371E+02 1.427E+02 1.484E+02 1.540E+02 1.597E+02 1.653E+02 TZV 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 IP1 2.745E+00 2.454E+00 2.745E+00 2.724E+00 2.705E+00 2.686E+00 2.668E+00 2.651E+00 2.634E+00 2.618E+00 2.603E+00 TS1 9.267E-06 7.406E-06 9.267E-06 9.130E-06 8.999E-06 8.874E-06 8.755E-06 8.642E-06 8.534E-06 8.430E-06 8.331E-06 TL2 5.530E-09 7.438E-09 5.530E-09 5.626E-09 5.722E-09 5.818E-09 5.914E-09 6.010E-09 6.105E-09 6.201E-09 6.297E-09

3.335E-07 3.330E-07 3.325E-07 3.320E-07 3.315E-07 3.310E-07 3.306E-07 3.301E-07 3.297E-07 3.293E-07 3.288E-07 3.284E-07 3.392E-07 3.284E-07

0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00

1.710E+02 1.767E+02 1.823E+02 1.880E+02 1.936E+02 1.993E+02 2.049E+02 2.106E+02 2.163E+02 2.219E+02 2.276E+02 2.332E+02 1.201E+02 2.332E+02

0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00 0.000E+00

2.588E+00 2.573E+00 2.559E+00 2.546E+00 2.533E+00 2.521E+00 2.509E+00 2.497E+00 2.486E+00 2.475E+00 2.464E+00 2.454E+00 2.745E+00 2.454E+00

8.236E-06 8.145E-06 8.057E-06 7.974E-06 7.893E-06 7.815E-06 7.741E-06 7.669E-06 7.599E-06 7.532E-06 7.468E-06 7.406E-06 9.267E-06 7.406E-06

6.392E-09 6.488E-09 6.583E-09 6.678E-09 6.774E-09 6.869E-09 6.964E-09 7.059E-09 7.154E-09 7.249E-09 7.344E-09 7.438E-09 5.530E-09 7.438E-09

TE1 9.629E-06 7.758E-06 9.629E-06 9.491E-06 9.359E-06 9.234E-06 9.115E-06 9.001E-06 8.892E-06 8.788E-06 8.688E-06

IP2 2.923E+00 2.635E+00 2.923E+00 2.903E+00 2.883E+00 2.865E+00 2.847E+00 2.830E+00 2.813E+00 2.797E+00 2.782E+00

c -3.561E-07 -3.448E-07 -3.561E-07 -3.553E-07 -3.546E-07 -3.539E-07 -3.532E-07 -3.525E-07 -3.519E-07 -3.513E-07 -3.507E-07

d -1.518E-08 -1.825E-08 -1.518E-08 -1.533E-08 -1.548E-08 -1.563E-08 -1.578E-08 -1.593E-08 -1.608E-08 -1.623E-08 -1.639E-08

TD(mag)

D1, actual

1.230E-06 -3.376E-06 1.230E-06 -3.018E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 -3.376E-06 -3.351E-06 -3.327E-06 -3.304E-06 -3.282E-06 -3.260E-06 -3.240E-06 -3.220E-06 -3.201E-06

6.250E-06 3.373E-01 5.629E-06 2.610E-01 6.250E-06 6.206E-06 6.164E-06 6.124E-06 6.086E-06 6.049E-06 6.013E-06 5.979E-06 5.946E-06 3.373E-01 3.325E-01 3.278E-01 3.232E-01 3.187E-01 3.144E-01 3.102E-01 3.061E-01 3.021E-01

8.592E-06 8.501E-06 8.413E-06 8.329E-06 8.248E-06 8.170E-06 8.094E-06 8.022E-06 7.952E-06 7.885E-06 7.820E-06 7.758E-06 9.629E-06 7.758E-06

2.767E+00 2.753E+00 2.739E+00 2.726E+00 2.713E+00 2.701E+00 2.689E+00 2.677E+00 2.666E+00 2.655E+00 2.645E+00 2.635E+00 2.923E+00 2.635E+00

1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06 1.230E-06

-3.183E-06 -3.165E-06 -3.148E-06 -3.132E-06 -3.116E-06 -3.100E-06 -3.086E-06 -3.071E-06 -3.057E-06 -3.044E-06 -3.031E-06 -3.018E-06

-3.501E-07 -3.496E-07 -3.490E-07 -3.485E-07 -3.480E-07 -3.475E-07 -3.470E-07 -3.465E-07 -3.461E-07 -3.456E-07 -3.452E-07 -3.448E-07 -3.561E-07 -3.448E-07

-1.654E-08 -1.669E-08 -1.685E-08 -1.700E-08 -1.716E-08 -1.731E-08 -1.747E-08 -1.763E-08 -1.778E-08 -1.794E-08 -1.809E-08 -1.825E-08 -1.518E-08 -1.825E-08

5.914E-06 5.884E-06 5.854E-06 5.826E-06 5.798E-06 5.772E-06 5.746E-06 5.721E-06 5.697E-06 5.674E-06 5.651E-06 5.629E-06

2.982E-01 2.943E-01 2.906E-01 2.870E-01 2.835E-01 2.801E-01 2.767E-01 2.734E-01 2.702E-01 2.671E-01 2.640E-01 2.610E-01

1.230E-06 -3.376E-06 1.230E-06 -3.018E-06

6.250E-06 3.373E-01 5.629E-06 2.610E-01

ICS(pl) 1.426E-04 2.045E-04 2.446E-04 2.499E-04 2.552E-04 2.605E-04 2.658E-04 2.711E-04 2.765E-04 2.818E-04 2.871E-04

VCS(pk)

PIN

7.380E-01 1.250E+02 7.110E-01 1.250E+02 1.339E+00 1.340E+00 1.340E+00 1.341E+00 1.343E+00 1.344E+00 1.346E+00 1.348E+00 1.350E+00 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02

2.924E-04 2.977E-04 3.030E-04 3.084E-04 3.137E-04 3.190E-04 3.243E-04 3.296E-04 3.349E-04 3.403E-04 3.456E-04 3.509E-04 2.446E-04 3.509E-04

1.353E+00 1.355E+00 1.358E+00 1.361E+00 1.364E+00 1.367E+00 1.370E+00 1.374E+00 1.378E+00 1.381E+00 1.385E+00 1.389E+00 1.339E+00 1.389E+00

1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02 1.250E+02

Flyback Inductor Specification for the UCC28600 Greenmode Quasi-Resonant Converter

The flyback transformer plays a crucial role in the performance of the green mode controller. Considerations must be given to adequate coupling for the bias windings, minimizing leakage inductance, and minimizing audible noise. All of these criteria can easily be met with proper transformer design from the start.
GENERAL: Topology: Main Output Power: Anticipated Overall Efficiency of the Converter: Maximum Switching Frequency: Minimum Switching Frequency: INPUT: Minimum Input Voltage: Maximum Input Voltage: Peak PRIMARY Current: PRIMARY RMS Current: Duty Cycle at Minimum Input Voltage, Maximum Load: Duty Cycle at Maximum Input Voltage, Maximum Load: OUTPUTS: SECONDARY Output Voltage: SECONDARY Output Peak Current: SECONDARY RMS Current: BIAS Voltage: Approximate RMS BIAS Current: INDUCTANCE AND TURNS RATIO: Magnetizing Inductance: Maximum Leakage Inductance: PRIMARY to SECONDARY Turns Ratio (NPRI/NSEC): PRIMARY to BIAS Turns Ratio (NPRI/NBIAS): Isolation Requirement:

Quasi-Resonant Flyback with Bias Winding 120 W 0.96 130.0E+3 Hz Burst packets of 40kHz pulses at loads of 15% or less

260.22 373.35 3.16 1.01 0.30 0.23

V V A A

24 15.30 7.189 19.4 44.5E-3

V A A V A

233.9E-6 H 3.5E-6 H 4.841 5.989 1500 V

SPECIAL NOTES REGARDING THE FLYBACK TRANSFORMER: 1. The BIAS windings must be well coupled to the PRIMARY. Interleave BIAS ans SECONDARY windings between the primary for equal coupling. 2. Use bundled stranded wire. 3. Encase the windings in as much Ferrite as possible; a round post core is a must to help reduce leakage. 4. Do not use tape barriers. Use triple insulated wire on the SECONDARY to meet the isolation requirement while minimizing leakage inductance. 5. Must be potted or heavily varnished to reduce audible noise. Also, fill the gap with flexible epoxy to reduce audible noise. 6. Distribute the BIAS windings over the entire width of the bobbin. 7. Place the dot end of the PRIMARY winding as close to the core as possible to help shield the dv/dt noise. 8. Wind the SECONDARY so that the non-dot end is the outer most layer.

Insulation tape Primary Secondary, Triple insulated wire Bias Primary

Example of a recommended transformer design. Use multiple strand wire to distribute each of the coils across the layer.
For more information refer to: http://focus.ti.com/lit/an/slua418/slua418.pdf