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VLSI MINI PROJECT TITLES

S.No: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. Project title Asynchronous fifo controller ALU (32 operations) 32 bit Parallel CRC Real Time Clock Low power cache A simple DMA controller I2C communications protocol SPI communications protocol Frame assembler and transmitter of Ethernet transmitter Defer and backoff blocks of Ethernet transmitter. Multiple scheme arbiter. Key expansion in AES Byte substitution in AES Mix column in AES AES encryption. AES decryption. Uart transmitter Uart Receiver IEEE 754-2008 floating point multiplier Design of N*N matrix multiplication Design of Manchester encoder and decoder Implementation of DCT using Verilog HDL VLSI Design of DES (Data Encryption Standard) Algorithm Vending machine Reconfigurable barrel shifter Baud rate generator Use of timers in Traffic light controller 8 bit microprocessor RSA encryption algorithm MD5 based data integrity system. Booths multiplier Efficient on-chip Cross talk avoidance codec design Energy efficient spatial coding technique for low power applications Montgomery multipliers. Command generator for DDR controller Scheduler for DDR controller.

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VLSI MINI PROJECT TITLES

37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. Low power LFSR based pattern generator for BIST MISR based TRA for BIST Multiple scheme arbiter. FPGA implementation of low power parallel multiplier Design of N*N matrix multiplication Cost efficient SHA hardware accelerators Binary to seven segment decoder for multiplexed display DDR memory model implementation March C+ algorithm (with and without BDS) for MBIST Design of Content addressable memory. Fully configurable timer/counter for use in microcontroller. Vending machine Binary to bcd and bcd to binary converter Floating point ALU VHDL simulation projects VHDL implementation of FIR filter structures Design and Implementation of Asynchronous FIFO for Embedded application VHDL Implementation of I2C bus Controller VHDL Implementation of Golay Encoder & Decoder CORDIC algorithm for trigonometric function computation in VHDL. VHDL implementation of efficient source coding technique Simulation of digital down converter (DDC) in VHDL Network intrusion detection VHDL simulation of multi path fading model for broadband wireless networks VHDL simulation and synthesis of Xilinx FFT IP core for streaming type of signal processing

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10

F100 F101 F102 F103 F104 F105 F106 F107 F108

VHDL simulation and FPGA kit based projects FPGA Implementation of UART Controller FPGA implementation of VGA interface controller FPGA implementation of DPWM generation circuit Implementation of stepper motor controller with FPGA. Implementation of PS/2 Key board interface with FPGA. Implementation of low cost logic signal analyzer (LSA) on Spartan-3 FPGA. Study and FPGA implementation of fixed point adders and multipliers structures FPGA implementation of digital BFSK transmitter and receiver FPGA Implementation of 32-Bit Arithmetic Logic Unit(ALU) for ARM7 soft

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VLSI MINI PROJECT TITLES

F109 F110 F111 F112 F113 F114 F115 F116 F117 F118 F119 F120 F121 F122 F123 F124 F125 F126 F127 F128 F129 F130 processor FPGA implementation of Distributed Arithmetic based MAC unit FPGA Implementation of Cyclic Redundancy Check (CRC) generator Look up table based digital frequency synthesis for FPGA based applications Study and FPGA implementation various PN sequence generators for CDMA communication applications. FPGA implementation of encryption algorithm for internet applications. Porting Pico blaze 8 bit soft microcontroller on Spartan 3E FPGA for CSOC applications Porting Micro blaze 32 bit soft processor on Spartan 3E FPGA using hardware software codesign approach Implementing fast dual port RAM using block RAMs on Spartan FPGAs Realizing efficient multi clock domain circuits with digital clock managers (DCMs) of Spartan 3E FPGAs FPGA realization of Manchester encoder and decoder Implementing FIR digital filter for FPGA based DSP applications Implementing Cascade Integer Comb applications for software defined radio applications Realizing run time configurable FFT core using Xilinx modules on Spartan FPGA Magnitude computation of complex numbers using area efficient CORDIC algorithm FPGA implementation of Programmable and reconfigurable timer module for SOC applications Microwave oven controller built with low cost FPGAs Simulation, synthesis and FPGA verification of ALU for RISC processor for embedded soft-core applications Implementation of S-box (Kernel of AES algorithm) for real time on chip cryptography Implementation of SHA function for FPGA based cryptographic applications FPGA implementation of Programmable interrupt controller using VHDL Implementation of hardware Watchdog timer in Xilinx Spartan FPGA Implementation of real time on chip trace data compression and decompression algorithm

SVS 1 SVS 2 SVS3 SVS4

Design of a candy vending machine controller using Verilog HDL Design of a Escalator and Elevator using Verilog HDL Design of a Asynchronous FIFIO with gray counter using Verilog HDL Design of fire and smoke detector using Verilog HDL with Auto activation of sprinkler

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VLSI MINI PROJECT TITLES

SVS5 SVS6 SVS8 SVS9 SVS10 SVS11 SVS 12 SVS 13 SVS 14 SVS 16 SVS 17 SVS 18 SVS 20 SVS 21 SVS 22 SVS 23 SVS 24 SVS 25 Design and implantation of sequence Detector Design of 16 bit Arithmetic logic unit using Verilog HDL Design of Different real time adders using Verilog HDL Design of RAM with error detection using Verilog HDL Design of Automatic room controller using Verilog HDL Design of siso,sipo,piso,pipo using Verilog HDL Design of Digital code convertors using Verilog HDL Design of Digital clock using Verilog HDL Design of Electronic voting machine using Verilog HDL Design and implementation of spi using VHDL Design of Traffic light controller using VHDL Design of FIR filter using VHDL Design and implementation of ROM and RAM using VHDL Design of Round Robin arbiter using VHDL Design of Barrel shifter using VHDL Design of Delta to Sigma Convertor using VHDL Design of Digital Comparator using basic gates using VHDL Design and implementation of Content Addressable Memory using VHDL FPGA implementation of High performance Multiplier using Squarer Low power and Area Efficient carry select Adder

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