EE278 SAN JOSE STATE UNIVERSITY DEPARTMENT OF ELECTRICAL ENGINEERING

Fall 2012

Advanced Digital Design for DSP and Communications (Formerly FPGA DSP System Design)
GENERAL INFORMATION COURSE: EE278 Digital Design for DSP and Communications (formerly EE296S: FPGA DSP System Design) Lecture Mon, Wed, 4:30pm-5:45pm, ENG394

TAUGHT BY: Prof. Chang Choo, ENG253, 924-3980, chang.choo@sjsu.edu OBJECTIVES: This course provides an in-depth and state-of-the-art coverage on the design and VLSI/FPGA/ASIC-based implementation of high-performance DSP systems. After presenting FPGA architectures and design tools by Xilinx and Altera, several design examples on DSP, digital communications and video/imaging will be covered, including FFT, FIR filter, error detection/correction circuits, color space converter, and DCT. There will be 4 mini-projects, and a term project. PREREQUISITE: EE270 (or EE271), EE253 (or EE153) or equivalent. Knowledge of programming language (C, Matlab and/or Simulink), hardware description language (Verilog or VHDL), and basic DSP theory. TEXTBOOK: C.Y. Choo, FPGA DSP System Design, (Lecture slides & writing), September 2012 (To be available on 9/1 in Maple Press). C.Y. Choo (ed.), Reference Manual for FPGA System Design Using Altera DE Board, August 2011 (Draft 2.0). To Be Available on 8/28(Tue) in Maple Press. REFERENCES: Uwe Meyer-Baese, Digital Signal Processing with Field Programmable Gate Array, 2nd Ed., Springer-Verlag, New York, 2004 (ISBN 3-540-21119-5). 1st Ed. is fine too. On-line purchase through, e.g., amazon.com, suggested. The Verilog Golden Reference Guide, by Doulos, 1996. Won Yang, Yong Cho, Chang Choo, et al., MATLAB/Simulink for Digital Signal Processing, on-line purchase through amazon.com available.

WEB SITE:

Class information, notices, course materials, FAQs (selected course-related emails between students and Prof. Choo) will be posted on the web: http://www.engr.sjsu.edu/choo. In addition, all the changes on the tentative list of homework problems (see below), as well as solutions to homework, will be available on the web. Students are urged to visit the web site twice a week.

EVALUATION:

The weighting among exams, assignments, and laboratory will be: Mini-projects (4) Mini-project Quizzes (4) Midterm Exam Final Exam Final Project (Report, Presentation & Demo) 8% each 2% each 15% 20% 25%

EXAMS:

Endterm Final

October 10, Wednesday, in class

2:45pm-5pm, Tuesday, December 18

OFFICE HOURS:

The office hours are made available for questions about lectures and projects and for discussion of grades assigned. If you need a help of the instructor, see him right after class or during his office hours (see his website). Use of e-mail is strongly recommended for other times, although appointments may be made for mutually convenient times.

MINIPROJECTS: 1 DSP-MAC with rounding/saturation (due 9/17) 2 FIR filter design (due 10/8) 3 LMS adaptive FIR filter design (due 10/29) 4 Nios-II based embedded adaptive FIR design (due 11/19) TENTATIVE SCHEDULE:
Lecture 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Date 8/22/2012 8/27/2012 8/29/2012 9/5/2012 9/10/2012 9/12/2012 9/17/2012 9/19/2012 9/24/2012 9/26/2012 10/1/2012 10/3/2012 10/8/2012 10/10/2012 10/15/2012 10/17/2012 10/22/2012 10/24/2012 10/29/2012 10/31/2012 11/5/2012 11/7/2012 11/12/2012 Day Topic W Introduction M FPGA DSP System Design Flow W DSP Arithmetic I W DSP Arithmetic II M FIR Filter Design I W FIR Filter Design II M Design of FFT Circuit I W Design of FFT Circuit II M Design of DCT Circuit I W Design of DCT Circuit II M Embedded DSP System Design I W Embedded DSP System Design II M Embedded DSP System Design III W Midterm M FPGA Architecture I W FPGA Architecture II M Design of Multirate Filters W Adaptive FIR Filter I M Adaptive FIR Filter II W CMDA M Distributed Arithmetic W Image Processing Circuits I M Image Processing Circuits II

23 24 25 26

11/14/2012 11/19/2012 11/21/2012 11/26/2012 11/28/2012 12/3/2012 12/5/12

W M W M W M W

Error Detection and Correction Encryption & Decryption I Encryption & Decryption II Term Project Presentation & Demo Term Project Presentation & Demo Term Project Presentation & Demo Term Project Presentation & Demo

Related Websites
Altera DE1 Board opencore.org TI Applications Site

Comments
Altera DE1 Board Official Website

Lots of interesting verilog cores Excellent sources of app notes, tutorials, etc. on DSP apps.

(Last Updated 8/21/12)