Introduction to RS485

RS232, RS422, RS423 and RS485 are serial communication methods for computers and devices. RS232 is without doubt the best known interface, because this serial interface is implemented on almost all computers available today. But some of the other interfaces are certainly interesting because they can be used in situations where RS232 is not appropriate. We will concentrate on the RS485 interface here. RS232 is an interface to connect one DTE, data terminal equipment to one DCE, data communication equipment at a maximum speed of 20 kbps with a maximum cable length of 50 feet. This was sufficient in the old days where almost all computer equipment were connected using modems, but soon after people started to look for interfaces capable of one or more of the following:

Connect DTE's directly without the need of modems Connect several DTE's in a network structure Ability to communicate over longer distances Ability to communicate at faster communication rates

RS485 is the most versatile communication standard in the standard series defined by the EIA, as it performs well on all four points. That is why RS485 is currently a widely used communication interface in data acquisition and control applications where multiple nodes communicate with each other.

Differential signals with RS485: Longer distances and higher bit rates
One of the main problems with RS232 is the lack of immunity for noise on the signal lines. The transmitter and receiver compare the voltages of the data- and handshake lines with one common zero line. Shifts in the ground level can have disastrous effects. Therefore the trigger level of the RS232 interface is set relatively high at 3 Volt. Noise is easily picked up and limits both the maximum distance and communication speed. With RS485 on the contrary there is no such thing as a common zero as a signal reference. Several volts difference in the ground level of the RS485 transmitter and receiver does not cause any problems. The RS485 signals are floating and each signal is transmitted over a Sig+ line and a Sig- line. The RS485 receiver compares the voltage difference between both lines, instead of the absolute voltage level on a signal line. This works well and prevents the existence of ground loops, a common source of communication problems. The best results are achieved if the Sig+ and Sig- lines are twisted. The image below explains why.
Noise in straight and twisted pair cables

In the picture above, noise is generated by magnetic fields from the environment. The picture shows the magnetic field lines and the noise current in the RS485 data lines that is the result of that magnetic field. In the straight cable, all noise current is flowing in the same direction, practically generating a looping current just like in an ordinary transformer. When the cable is twisted, we see that in some parts of the signal lines the direction of the noise current is the oposite from the current in other parts of the cable. Because of this, the resulting noise current is many factors lower than with an ordinary straight cable. Shieldingwhich is a common method to prevent noise in RS232 linestries to keep hostile magnetic fields away from the signal lines. Twisted pairs in RS485 communication however adds immunity which is a much better way to fight noise. The magnetic fields are allowed to pass, but do no harm. If high noise immunity is needed, often a combination of twisting and shielding is used as for example in STP, shielded twisted pair and FTP, foiled twisted pair networking cables. Differential signals and twisting allows RS485 to communicate over much longer communication distances than achievable with RS232. With RS485 communication distances of 1200 m are possible. Differential signal lines also allow higher bit rates than possible with non-differential connections. Therefore RS485 can overcome the practical communication speed limit of RS232. Currently RS485 drivers are produced that can achieve a bit rate of 35 mbps.

Characteristics of RS485 compared to RS232, RS422 and RS423

Characteristics of RS232, RS422, RS423 and RS485

RS232 Differential Max number of drivers Max number of receivers no 1 1 half duplex full duplex point-to-point 15 m 20 kbs (1 kbs) 30 V/s

RS423 no 1 10 half duplex

RS422 yes 1 10 half duplex

RS485 yes 32 32 half duplex

Modes of operation Network topology Max distance (acc. standard) Max speed at 12 m Max speed at 1200 m Max slew rate

multidrop 1200 m 100 kbs 1 kbs adjustable

multidrop 1200 m 10 Mbs 100 kbs n/a

multipoint 1200 m 35 Mbs 100 kbs n/a

Receiver input resistance Driver load impedance Receiver input sensitivity Receiver input range Max driver output voltage Min driver output voltage (with load)

3..7 k 3..7 k 3 V 15 V 25 V 5 V

4 k 450 200 mV 12 V 6 V 3.6 V

4 k 100 200 mV 10 V 6 V 2.0 V

12 k 54 200 mV 7..12 V 7..12 V 1.5 V

What does all the information in this table tell us? First of all we see that the speed of the differential interfaces RS422 and RS485 is far superior to the single ended versions RS232 and RS423. We also see that there is a maximum slew rate defined for both RS232 and RS423. This has been done to avoid reflections of signals. The maximum slew rate also limits the maximum communication speed on the line. For both other interfacesRS422 and RS485the slew rate is indefinite. To avoid reflections on longer cables it is necessary to use appropriate termination resitors. We also see that the maximum allowed voltage levels for all interfaces are in the same range, but that the signal level is lower for the faster interfaces. Because of this RS485 and the others can be used in situations with a severe ground level shift of several volts, where at the same time high bit rates are possible because the transition between logical 0 and logical 1 is only a few hundred millivolts. Interesting is, that RS232 is the only interface capable of full duplex communication. This is, because on the other interfaces the communication channel is shared by multiple receivers andin the case of RS485by multiple senders. RS232 has a separate communication line for transmitting and receiving whichwith a well written protocolallows higher effective data rates at the same bit rate than the other interfaces. The request and acknowledge data needed in most protocols does not consume bandwidth on the primary data channel of RS232.

Network topology with RS485

Network topology is probably the reason why RS485 is now the favorite of the four mentioned interfaces in data acquisition and control applications. RS485 is the only of the interfaces capable of internetworking multiple transmitters and receivers in the same network. When using the default RS485 receivers with an input resistance of 12 k it is possible to connect 32 devices to the network. Currently available high-resistance RS485 inputs allow this number to be expanded to 256. RS485 repeaters are also available which make it possible to increase the number of nodes to several thousands, spanning multiple kilometers. And that with an interface which does not require intelligent network hardware: the implementation on the software side is not much more difficult than with RS232. It is the reason why RS485 is so popular with computers, PLCs, micro controllers and intelligent sensors in scientific and technical applications.
RS485 network topology

In the picture above, the general network topology of RS485 is shown. N nodes are connected in a multipoint RS485 network. For higher speeds and longer lines, the termination resistances are necessary on both ends of the line to eliminate reflections. Use 100 resistors on both ends. The RS485 network must be designed as one line with multiple drops, not as a star. Although total cable length maybe shorter in a star configuration, adequate termination is not possible anymore and signal quality may degrade significantly.

RS485 functionality
And now the most important question, how does RS485 function in practice? Default, all the senders on the RS485 bus are in tri-state with high impedance. In most higher level protocols, one of the nodes is defined as a master which sends queries or commands over the RS485 bus. All other nodes receive these data. Depending of the information in the sent data, zero or more nodes on the line respond to the master. In this situation, bandwidth can be used for almost 100%. There are other implementations of RS485 networks where every node can start a data session on its own. This is comparable with the way ethernet networks function. Because there is a chance of data collosion with this implementation, theory tells us that in this case only 37% of the bandwidth will be effectively used. With such an implementation of a RS485 network it is necessary that there is error detection implemented in the higher level protocol to detect the data corruption and resend the information at a later time. There is no need for the senders to explicity turn the RS485 driver on or off. RS485 drivers automatically return to their high impedance tri-state within a few microseconds after the data has been sent. Therefore it is not needed to have delays between the data packets on the RS485 bus. RS485 is used as the electrical layer for many well known interface standards, including Profibus and Modbus. Therefore RS485 will be in use for many years in the future.

Serial UART, an introduction

An UART, universal asynchronous receiver / transmitter is responsible for performing the main task in serial communications with computers. The device changes incomming parallel information to serial data which can be sent on a communication line. A second UART can be used to receive the information. The UART performs all the tasks, timing, parity checking, etc. needed for the communication. The only extra devices attached are line driver chips capable of transforming the TTL level signals to line voltages and vice versa. To use the UART in different environments, registers are accessible to set or review the communication parameters. Setable parameters are for example the communication speed, the type of parity check, and the way incomming information is signalled to the running software.

Serial UART types

Serial communication on PC compatibles started with the 8250 UART in the IBM XT. In the years after, new family members were introduced like the 8250A and 8250B revisions and the 16450. The last one was first implemented in the AT. The higher bus speed in this computer could not be reached by the 8250 series. The differences between these first UART series were rather minor. The most important property changed with each new release was the maximum allowed speed at the processor bus side. The 16450 was capable of handling a communication speed of 38.4 kbs without problems. The demand for higher speeds led to the development of newer series which would be able to release the main processor from some of its tasks. The main problem with the original series was the need to perform a software action for each single byte to transmit or receive. To overcome this problem, the 16550 was released which contained two on-board FIFO buffers, each capable of storing 16 bytes. One buffer for incomming, and one buffer for outgoing bytes. A marvellous idea, but it didn't work out that way. The 16550 chip contained a firmware bug which made it impossible to use the buffers. The 16550A which appeared soon after was the first UART which was able to use its FIFO buffers. This made it possible to increase maximum reliable communication speeds to 115.2 kbs. This speed was necessary to use effectively modems with onboard compression. A further enhancment introduced with the 16550 was the ablity to use DMA, direct memory access for the data transfer. Two pins were redefined for this purpose. DMA transfer is not used with most applications. Only special serial I/O boards with a high number of ports contain sometimes the necessary extra circuitry to make this feature work. The 16550A is the most common UART at this moment. Newer versions are under development, including the 16650 which contains two 32 byte FIFO's and on board support for software flow control. Texas Instruments is developing the 16750 which contains 64 byte FIFO's.

Registers
Eight I/O bytes are used for each UART to access its registers. The following table shows, where each register can be found. The base address used in the table is the lowest I/O port number assigned. The switch bit DLAB can be found in the line control register LCR as bit 7 at I/O address base + 3.

UART register to port conversion table

DLAB = 0 I/O port Read RBR receiver buffer IER interrupt enable IIR interrupt identification Write THR transmitter holding IER interrupt enable FCR FIFO control Read

DLAB = 1 Write

base

DLL divisor latch LSB

base + 1

DLM divisor latch MSB IIR interrupt identification FCR FIFO control

base + 2 base + 3 base + 4

LCR line control MCR modem control LSR line status MSR modem status factory test not used LSR line status MSR modem status factory test not used

base + 5

base + 6 base + 7
Available registers

SCR scratch

RBR, receiver buffer register THR, transmitter holding register IER, interrupt enable register IIR, interrupt identification register FCR, FIFO control register LCR, line control register MCR, modem control register LSR, line status register MSR, modem status register SCR, scratch register DLL, divisor latch LSB DLM, divisor latch MSB The communication between the processor and the UART is completely controlled by twelve registers. These registers can be read or written to check and change the behaviour of the communication device. Each register is eight bits wide. On a PC compatible, the registers are accessible in the I/O address area. The function of each register will be discussed here in detail.

RBR : Receiver buffer register (RO)

The RBR, receiver buffer register contains the byte received if no FIFO is used, or the oldest unread byte with FIFO's. If FIFO buffering is used, each new read action of the register will return the next byte, until no more bytes are present. Bit 0 in the LSR line status register can be used to check if all received bytes have been read. This bit wil change to zero if no more bytes are present.

THR : Transmitter holding register (WO)

The THR, transmitter holding register is used to buffer outgoing characters. If no FIFO buffering is used, only one character can be stored. Otherwise the amount of characters depends on the type of UART. Bit 5 in the LSR, line status register can be used to check if new information must be written to THR. The value 1 indicates that the register is empty. If FIFO buffering is used, more than one character can be written to the transmitter holding register when the bit signals an empty state. There is no indication of the amount of bytes currently present in the transmitter FIFO. The transmitter holding register is not used to transfer the data directly. The byte is first transferred to a shift register where the information is broken in single bits which are sent one by one.

IER : Interrupt enable register (R/W)

The smartest way to perform serial communications on a PC is using interrupt driven routines. In that configuration, it is not necessary to poll the registers of the UART periodically for state changes. The UART will signal each change by generating a processor interrupt. A software routine must be present to handle the interrupt and to check what state change was responsible for it. Interrupts are not generated, unless the UART is told to do so. This is done by setting bits in the IER, interrupt enable register. A bit value 1 indicates, that an interrupt may take place.
IER : Interrupt enable register

Bit 0 1 2 3 4 5 6 7

Description Received data available Transmitter holding register empty Receiver line status register change Modem status register change Sleep mode (16750 only) Low power mode (16750 only) reserved reserved

IIR : Interrupt identification register (RO)

An UART is capable of generating a processor interrupt when a state change on the communication device occurs. One interrupt signal is used to call attention. This means, that additional information is needed for the software before the necessary actions can be performed. The IIR, interrupt identification register is helpful in this situation. Its bits show the current state of the UART and which state change caused the interrupt to occur.
IIR : Interrupt identification register

Bit 0

Value 0

Description Interrupt pending

Reset by

1 Bit 3 0 0 0 0 1,2,3 4 1 Bit 2 0 0 1 1 1 0 0 5 Bit 7 0 1 6,7 1 1 Bit 6 0 0 1 Bit 1 0 1 0 1 0

No interrupt pending

Modem status change Transmitter holding register empty Received data available Line status change Character timeout (16550) Reserved Reserved (8250, 16450, 16550) 64 byte FIFO enabled (16750)

MSR read IIR read or THR write RBR read LSR read RBR read

No FIFO Unusable FIFO (16550 only) FIFO enabled

FCR : FIFO control register (WO)

The FCR, FIFO control register is present starting with the 16550 series. This register controls the behaviour of the FIFO's in the UART. If a logical value 1 is written to bits 1 or 2, the function attached is triggered. The other bits are used to select a specific FIFO mode.
FCR : FIFO control register

Bit

Value 0

Description Disable FIFO's Enable FIFO's Clear receive FIFO Clear transmit FIFO Select DMA mode 0 Select DMA mode 1 Reserved Reserved (8250, 16450, 16550) Enable 64 byte FIFO (16750)

1 0

1 0

1 0

3 4

1 0 0

5 6,7 Bit 7 0 0

1 Bit 6 0 1

Receive FIFO interrupt trigger level 1 byte 4 bytes

1 1

0 1

8 bytes 14 bytes

LCR : Line control register (R/W)

The LCR, line control register is used at initialisation to set the communication parameters. Parity and number of data bits can be changed for example. The register also controls the accessibility of the DLL and DLM registers. These registers are mapped to the same I/O port as the RBR, THR and IER registers. Because they are only accessed at initialisation when no communication occurs this register swapping has no influence on performance.
LCR : line control register

Bit Bit 1 0 0 1 0,1 1

Value Bit 0 0 1 0 1 0

Description Data word length 5 bits 6 bits 7 bits 8 bits 1 stop bit 1.5 stop bits (5 bits word) 2 stop bits (6, 7 or 8 bits word) Bit 3 0 1 1 1 1 No parity Odd parity Even parity High parity (stick) Low parity (stick) Break signal disabled Break signal enabled DLAB : RBR, THR and IER accessible DLAB : DLL and DLM accessible

2 Bit 5 x 0 0 1 3,4,5 1

1 Bit 4 x 0 1 0 1 0

1 0

7
Some remarks about parity:

The UART is capable of generating a trailing bit at the end of each dataword which can be used to check some data distortion. Because only one bit is used, the parity system is capable of detecting only an odd number of false bits. If an even number of bits has been flipped, the error will not be seen.

When even parity is selected, the UART assures that the number of high bit values in the sent or received data is always even. Odd parity setting does the opposite. Using stick parity has very little use. It sets the parity bit to always 1, or always 0. Common settings are:

8 data bits, one stop bit, no parity 7 data bits, one stop bit, even parity

MCR : Modem control register (R/W)

The MCR, modem control register is used to perform handshaking actions with the attached device. In the original UART series including the 16550, setting and resetting of the control signals must be done by software. The new 16750 is capable of handling flow control automatically, thereby reducing the load on the processor.
MCR : Modem control register

Bit 0 1 2 3 4 5 6 7

Description Data terminal ready Request to send Auxiliary output 1 Auxiliary output 2 Loopback mode Autoflow control (16750 only) Reserved Reserved

The two auxiliary outputs are user definable. Output 2 is sometimes used in circuitry which controls the interrupt process on a PC. Output 1 is normally not used, however on some I/O cards, it controls the selection of a second oscillator working at 4 MHz. This is mainly for MIDI purposes.

LSR : Line status register (RO)

The LSR, line status register shows the current state of communication. Errors are reflected in this register. The state of the receive and transmit buffers is also available.
LSR : Line status register

Bit 0 1 2 3

Description Data available Overrun error Parity error Framing error

4 5 6 7

Break signal received THR is empty THR is empty, and line is idle Errornous data in FIFO

Bit 5 and 6 both show the state of the transmitting cycle. The difference is, that bit 5 turns high as soon as the transmitter holding register is empty whereas bit 6 indicates that also the shift register which outputs the bits on the line is empty.

MSR : Modem status register (RO)

The MSR, modem status register contains information about the four incomming modem control lines on the device. The information is split in two nibbles. The four most siginificant bits contain information about the current state of the inputs where the least significant bits are used to indicate state changes. The four LSB's are reset, each time the register is read.
MSR : Modem status register

Bit 0 1 2 3 4 5 6 7

Description change in Clear to send change in Data set ready trailing edge Ring indicator change in Carrier detect Clear to send Data set ready Ring indicator Carrier detect

SCR : Scratch register (R/W)

The SCR, scratch register was not present on the 8250 and 8250B UART. It can be used to store one byte of information. In practice, it has only limited use. The only real use I know of is checking if the UART is a 8250/8250B, or a 8250A/16450 series. Because the 8250 series are only found in XT's even this use of the register is not commonly seen anymore.

DLL and DLM : Divisor latch registers (R/W)

For generating its timing information, each UART uses an oscillator generating a frequency of about 1.8432 MHz. This frequency is divided by 16 to generate the time base for communucation. Because of this division, the maximum allowed communication speed is 115200 bps. Modern UARTS like the 16550 are capable of handling higher input frequencies up to 24 MHz which makes it possible to communicate with a maximum speed of 1.5 Mbps. On PC's higher frequencies than the 1.8432 MHz are rarely seen because this would be software incompatible with the original XT configuration.

This 115200 bps communication speed is not suitable for all applications. To change the communication speed, the frequency can be further decreased by dividing it by a programmable value. For very slow communications, this value can go beyond 255. Therefore, the divisor is stored in two seperate bytes, the divisor latch registers DLL and DLM which contain the least, and most significant byte. For error free communication, it is necessary that both the transmitting and receiving UART use the same time base. Default values have been defined which are commonly used. The table shows the most common values with the appropriate settings of the divisor latch bytes. Note that these values only hold for a PC compatible system where a clock frequency of 1.8432 MHz is used.
DLL and DLM : Divisor latch registers

Speed (bps) 50 300 1,200 2,400 4,800 9,600 19,200 38,400 57,600 115,200

Divisor 2,304 384 96 48 24 12 6 3 2 1

DLL 0x00 0x80 0x60 0x30 0x18 0x0C 0x06 0x03 0x02 0x01

DLM 0x09 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

RS232 specifications, introduction

Communication as defined in the RS232 standard is an asynchronous serial communication method. The word serial means, that the information is sent one bit at a time. Asynchronous tells us that the information is not sent in predefined time slots. Data transfer can start at any given time and it is the task of the receiver to detect when a message starts and ends. Asynchronous communication has some advantages and disadvantages which are both discussed in the next paragraph.

RS232 bit streams

The RS232 standard describes a communication method where information is sent bit by bit on a physical channel. The information must be broken up in data words. The length of a data word is variable. On PC's a length between 5 and 8 bits can be selected. This length is the netto information length of each word. For proper transfer additional bits are added for synchronisation and error checking purposes. It is important, that the transmitter and receiver use the same number of bits. Otherwise, the data word may be misinterpreted, or not recognized at all.

With synchronous communication, a clock or trigger signal must be present which indicates the beginning of each transfer. The absence of a clock signal makes an asynchronous communication channel cheaper to operate. Less lines are necessary in the cable. A disadvantage is, that the receiver can start at the wrong moment receiving the information. Resynchronization is then needed which costs time. All data received in the resynchronization period is lost. Another disadvantage is that extra bits are needed in the data stream to indicate the start and end of useful information. These extra bits take up bandwidth. Data bits are sent with a predefined frequency, the baud rate. Both the transmitter and receiver must be programmed to use the same bit frequency. After the first bit is received, the receiver calculates at which moments the other data bits will be received. It will check the line voltage levels at those moments. With RS232, the line voltage level can have two states. The on state is also known as mark, the off state as space. No other line states are possible. When the line is idle, it is kept in the mark state.

Start bit
RS232 defines an asynchronous type of communication. This means, that sending of a data word can start on each moment. If starting at each moment is possible, this can pose some problems for the receiver to know which is the first bit to receive. To overcome this problem, each data word is started with an attention bit. This attention bit, also known as the start bit, is always identified by the space line level. Because the line is in mark state when idle, the start bit is easily recognized by the receiver.

Data bits
Directly following the start bit, the data bits are sent. A bit value 1 causes the line to go in mark state, the bit value 0 is represented by a space. The least significant bit is always the first bit sent.

Parity bit
For error detecting purposes, it is possible to add an extra bit to the data word automatically. The transmitter calculates the value of the bit depending on the information sent. The receiver performs the same calculation and checks if the actual parity bit value corresponds to the calculated value. This is further discussed in another paragraph.

Stop bits
Suppose that the receiver has missed the start bit because of noise on the transmission line. It started on the first following data bit with a space value. This causes garbled date to reach the receiver. A mechanism must be present to resynchronize the communication. To do this, framing is introduced. Framing means, that all the data bits and parity bit are contained in a frame of start and stop bits. The period of time lying between the start and stop bits is a constant defined by the baud rate and number of data and parity bits. The start bit has always space value, the stop bit always mark value. If the receiver detects a value other than mark when the stop bit should be present on the line, it knows that there is a synchronization failure. This causes a framing error condition in the receiving UART. The device then tries to resynchronize on new incomming bits.

For resynchronizing, the receiver scans the incomming data for valid start and stop bit pairs. This works, as long as there is enough variation in the bit patterns of the data words. If data value zero is sent repeatedly, resynchronization is not possible for example. The stop bit identifying the end of a data frame can have different lengths. Actually, it is not a real bit but a minimum period of time the line must be idle (mark state) at the end of each word. On PC's this period can have three lengths: the time equal to 1, 1.5 or 2 bits. 1.5 bits is only used with data words of 5 bits length and 2 only for longer words. A stop bit length of 1 bit is possible for all data word sizes.

RS232 physical properties

The RS232 standard describes a communication method capable of communicating in different environments. This has had its impact on the maximum allowable voltages etc. on the pins. In the original definition, the technical possibilities of that time were taken into account. The maximum baud rate defined for example is 20 kbps. With current devices like the 16550A UART, maximum speeds of 1.5 Mbps are allowed.

Voltages
The signal level of the RS232 pins can have two states. A high bit, or mark state is identified by a negative voltage and a low bit or space state uses a positive value. This might be a bit confusing, because in normal circumstances, high logical values are defined by high voltages also. The voltage limits are shown below.
RS232 voltage values

Level Space state (0) Mark state (1) Undefined

Transmitter capable (V) +5 ... +15 -5 ... -15 -

Receiver capable (V) +3 ... +25 -3 ... -25 -3 ... +3

More information about the voltage levels of RS232 and other serial interfaces can be found in the interface comparison table. The maximum voltage swing the computer can generate on its port can have influence on the maximum cable length and communication speed that is allowed. Also, if the voltage difference is small, data distortion will occur sooner. For example, my Toshiba laptop mark's voltage is -9.3 V, compared to -11.5 V on my desktop computer. The laptop has difficulties to communicate with Mitsubishi PLC's in industrial environments with high noise levels where the desktop computer has no data errors at all using the same cable. Thus, even far beyond the minimum voltage levels, 2 volts extra can make a huge difference in communication quality. Despite the high voltages present, it is not possible to destroy the serial port by short circuiting. Only applying external voltages with high currents may eventually burn out the driver chips. Still then, the UART won't be damaged in most cases.

Maximum cable lengths

Cable length is one of the most discussed items in RS232 world. The standard has a clear answer, the maximum cable length is 50 feet, or the cable length equal to a capacitance of 2500 pF. The latter rule is often forgotten. This means that using a cable with low capacitance allows you to span longer distances without going beyond the limitations of the standard. If for example UTP CAT-5 cable is used with a typical capacitance of 17 pF/ft, the maximum allowed cable length is 147 feet. The cable length mentioned in the standard allows maximum communication speed to occur. If speed is reduced by a factor 2 or 4, the maximum length increases dramatically. Texas Instruments has done some practical experiments years ago at different baud rates to test the maximum allowed cable lengths. Keep in mind, that the RS232 standard was originally developed for 20 kbps. By halving the maximum communication speed, the allowed cable length increases a factor ten!
RS232 cable length according to Texas Instruments

Baud rate 19200 9600 4800 2400

Maximum cable length (ft) 50 500 1000 3000

Error detection
One way of detecting errors is already discussed. It is the frame detection mechanism which is used to test if the incomming bits were properly surrounded by a start and stop bit pair. For further error checking, a parity bit can be used. The use of this bit is however not mandatory. If the existence of wrong bits is rare (when communicating with an internal modem for example) or if a higher level protocol is used for error detection and correction ( Z-modem, RAS, etc) communication speed can be increased by not using the parity feature present on the UART. Parity is a simple way to encode a data word to have a mechanism to detect an error in the information. The method used with serial communications adds one bit to each data word. The value of this bit depends on the value of the data word. It is necessary that both the transmitter and receiver use the same algorithm to calculate the value of the parity bit. Otherwise, the receiver may detect errors which are not present.

Even parity
Basically, the parity bit can be calculated in two ways. When even parity is used, the number of information bits sent will always contain an even number of logical 1's. If the number of high data bits is odd, a high value parity bit is added, otherwise a low bit will be used.

Odd parity
The odd parity system is quite similar to the even parity system, but in this situation, the number of high bits will always be odd.

Disadvantages of the parity system

The parity system using one bit for each data word is not capable of finding all errors. Only errors which cause an odd number of bits to flip will be detected. The second problem is, that there is no way to know which bit is false. If necessary, a higher level protocol is necessary to inform the sender that this information must be resent. Therefore, on noisy lines, often other detection systems are used to assure that the sent information is received correctly. These systems mostly do not operate on single data words, but on groups of words. Known coding systems are:

Hamming coding CRC16 cyclic redundancy check CCITT-16 cyclic redundancy check CRC-DNP cyclic redundancy check CRC32 cyclic redundancy check

Literature 1998 Application Note 83 published by Dallas Semiconductornow merged with Maxim Maximwhich describes in human readable language all aspects of the RS-232 interface. 2004 Application Report SLLA067A published by Texas Instruments about all kinds of practical physical aspects of currently available interface methods, including a line length vs. communication speed graph.

Selecting and Using RS-232, RS-422, and RS-485 Serial Data Standards
Abstract: Three common serial data standards, RS-232, RS-422, and RS-485, are described by specification and electrical interface. Cable termination techniques, use of multiple loads, daisy-chaining of RS-232, conversion of RS232 to RS-485, conversion of RS-485 to RS-232, and RS-232 port-powered RS-485 conversions are described.

Introduction
"The great thing about standards is there are so many to choose from." This statement was made at a recent conference on fiber optics, and it holds true for electrical-interface standards as well. As serial-data standards tend to evolve separately within particular industries, we thus have more standards than we should. Perhaps the most successful serial-data standard for PC and telecom applications is the RS-232. Similarly, the RS-485 and RS-422 are among the most successful standards for industrial applications. These standards are not directly compatible. For control and instrumentation applications, however, it is often necessary to communicate between the standards. This article discusses the different standards (electrical physical-layer specifications), explains how to convert from one standard to another standard, and demonstrates how to combine different standards within the same application.

RS-232 Electrical Specifications and a Typical Connection

The RS-232 link was initially intended to support modem and printer applications on IBM PCs, however, it now enables

a variety of peripherals to communicate with PCs. The RS-232 standard was defined as a single-ended standard for increasing serial-communication distances at low baud rates (<20kbps). Over the years the standard changed to accommodate faster drivers like the MAX3225E, which offers 1Mbps data-rate capability. For RS-232 compliance, a transceiver such as the MAX3225E must meet the electrical specifications listed in Table 1. A typical connection (Figure 1) shows the use of hardware handshaking to control the flow of data. Table 1. RS-232 Summary of Major Electrical Specifications Parameter Conditions Min Max Units Driver Output Voltage, Open Circuit Driver Output Voltage, Loaded Slew Rate Maximum Load Capacitance Receiver Input Resistance Receiver Input Threshold: Output = Mark (Logic 1) Output = Space (Logic 0) -3 3 V V 3 3k < RL < 7k 5 4 Driver Output Resistance, Power Off -2V < V < 2V 25 300 30 7 V/s k 2500 pF V 15 V

Figure 1. Typical RS-232 connection. A typical RS-232 signal (Figure 2, CH1) swings positive and negative. Note the relative location of the 0V trace markers on the left axis. Although the RS-232 data is inverted, an overall translation from TTL/CMOS to RS-232 and back to TTL/CMOS restores the data's original polarity. Typical RS-232 transmissions seldom exceed 100 feet for two reasons. Firstly, the difference between transmitted levels (5V) and receive levels (3V) allows only 2V of commonmode rejection. Secondly, the distributed capacitance of a longer cable can degrade slew rates by exceeding the maximum specified load (2500pF). Because the RS-232 was designed as a point-to-point rather than multidrop interface, its drivers are specified for single loads from 3k to 7k. Therefore, a daisy-chain scheme is typically implemented for multidrop interface applications (Figure 3).

Figure 2. An RS-232 receiver accepts the bipolar input signal (top trace, CH1) and outputs an inverted TTL/CMOS

signal (bottom trace, CH2).

Figure 3. Daisy-chaining allows multiple slave transceivers on a single RS-232 line.

Daisy-Chain Devices and Their Limitations

In a daisy-chain configuration, the RS-232 signal enters through one receiver and is looped through to a transmitter. This configuration is repeated for subsequent devices along the data transmission line. Cable breaks are a major problem with this technique. A break between slave 1 and slave 2 prevents all downstream devices from transmitting or receiving data. Other multidrop RS-232 techniques involve prebuffering or boosting the RS-232 output drive (enabling it to drive multiple 5k inputs in parallel). To eliminate the problems associated daisy-chain networks, Maxim developed the MAX3322E/MAX3323E, specifically designed to be configured in multidrop applications. These unique devices employ a logically switched input resistance of 5k . When a device is not selected, its input resistance remains in a high impedance state allowing communication to proceed with other devices along the shared bus. Another solution to the daisy-chain network problem is to convert the RS-232 Rx and Tx signals to RS-422 signals (see Table 2). RS-422 is a differential standard that allows transmission over much greater distances. The higher input resistance of RS-422 inputs, combined with their higher drive capability, allows a connection of up to ten nodes (Figure 4). Another RS-422 advantage is the separate transmit and receive paths for which no direction control is needed. Any necessary handshaking between devices can be performed with either software (XON/OFF handshaking) or hardware (a separate set of twisted pairs). The MAX3162 provides an economical way to translate between RS-232 and RS-422 signals. For more detail about this process, refer to the section below entitled RS-232/RS-485 Protocol Translators. Table 2. RS-422 Summary of Key Specifications Parameter Conditions Driver Output Voltage, Open Circuit Driver Output Voltage, Loaded Driver Output Resistance Driver Output Short-Circuit Current Driver Output Rise Time Driver Common-Mode Voltage Receiver Sensitivity Receiver Common-Mode Voltage Range Receiver Input Resistance Differential Receiver Voltage Operational Withstand RL = 100 A to B Per output to common RL = 100 RL = 100 VCM < 7V -7 4 10 12 2 -2 100 150 10 3 7

Min Max Units 10 V V mA % of bit width V V k V V

200 mV

Figure 4. A typical RS-422 system allows as many as ten slave transceivers on the differential transmission line.

Differences Between RS-485 and RS-422 and Their Use in Applications

RS-422 and RS-485 transceivers are often confused with each other; one is assumed to be a full-duplex version of the other. The electrical differences, however, in their common-mode ranges and receiver-input resistances make these standards suitable for different applications. As RS-485 meets all the RS-422 specifications ( Table 3), RS-485 drivers can be used in RS-422 applications. The opposite, however, is not true. The common-mode output range for RS-485 drivers is -7V to +12V, whereas the common-mode range for RS-422 drivers is only 3V. The minimum receiver-input resistance is 4k for RS-422 drivers and 12k for RS-485 drivers. Table 3. RS-485 Summary of Key Specifications Parameter Conditions Driver Output Voltage, Open Circuit Driver Output Voltage, Loaded Driver Output Short-Circuit Current Driver Output Rise Time Driver Common-Mode Voltage Receiver Sensitivity Receiver Common-Mode Voltage Range Receiver Input Resistance RL = 100 Per output to common RL = 54 CL = 50pF RL = 54 -7V < VCM < 12V -7 12

Min Max Units 1.5 6 -1.5 -6 1.5 5 -1.5 -5 V V V V

250 mA 30 3 12 % of bit width V V k

200 mV

To reduce wiring expense and achieve longer line lengths, RS-485 transceivers have become a popular standard for use in point-of-sale, industrial, and telecom applications. The wider common-mode range of RS-485 also enables longer line lengths and a higher input resistance per node, allowing more nodes to be connected to the bus ( Figure 5).

Figure 5. Compared with RS-422, the higher input impedance and wider common-mode range of an RS-485 connection enables longer line lengths. Differential RS-485 transmissions (Figure 6) produce opposing currents and magnetic fields along each segment (wire) of a twisted-pair cable, thus minimizing the emitted electromagnetic interference (EMI) by cross-canceling the opposing fields around each wire. For transmissions through a long cable or at high data rates, the cable appears as a transmission line and should be terminated with the cable's characteristic impedance. This aspect of the RS-485 connection causes confusion. Does the line need to be terminated, and if so, how should it be terminated? If the designer is not the end user, should these questions be left for the installer to resolve? For most RS-485 transceivers, the data sheet indicates a simple choice between no termination and a simple point-to-point termination when the cable acts as a transmission line (Figure 7). A termination resistor across the A-B terminals is harmless. By default, the transmission line should be terminated at the last transceiver on the line (bus).

Figure 6. The opposite polarity signals on an RS-485 line minimize EMI by cross-canceling each other's respective magnetic fields. The GND references on the above scope photo have been shifted (offset) to clearly show the inverted polarities of the RS-485 output signals.

Figure 7. The choice of termination resistors for a transmission line depends on the application.

Fail-Safe
Deciding whether you need a termination resistor or not is only part of the problem in implementing an RS-485 system. Normally, an RS-485 receiver output is "1" if A > B by +200mV or more, and "0" if B > A by 200mV or more. In a half-duplex RS-485 network, the master transceiver tri-states the bus after transmitting a message to the slaves. Then, with no signal driving the bus, the receiver's output state is undefined, as the difference between A and B tends towards 0V. If the receiver output, RO, is "0," the slaves interpret it as a new start bit and attempt to read the following byte. The result is a framing error because the stop bit never occurs. The bus goes unclaimed, and the network stalls. Unfortunately, different runs of chips can produce different output signals on RO for a 0V differential input. The prototype can work perfectly, however, certain nodes will fail in a later production run. To solve this problem, bias the bus as shown in Figure 7 under Multidrop/Fail-Safe Termination. Biasing the bus ensures that the receiver output remains "1" when the bus is tri-stated. Alternatively, you can use "true fail-safe" receivers like those of the MAX3080 (5V) and MAX3070 (3V) families. These devices ensure an RO output of "1" in response to a 0V differential input by changing the receiver's threshold to -50mV.

RS-232/RS-485 Protocol Translators

The MAX3162 is an unique device for it contains both RS-232 and RS-485 receivers and transmitters. This wide range of communication devices contained within a single IC enables an individual to convert bidirectionally between RS-232 and RS-485 signals. The circuit in Figure 8 illustrates the MAX3162 configured to bidirectionally convert RS-232 and RS-485 signals in a point-to-point application.

Figure 8. The MAX3162 converts bidirectionally between RS-232 and RS-485 signals in a point-to-point application. Figure 9 shows the MAX3162 configured as an RS-232/RS-485 multipoint protocol translator. The direction of translation is controlled through the RTS signal, R1IN. The single-ended RS-232 receiver-input signal is translated to a differential RS-485 transmitter output. Similarly, a differential RS-485 receiver-input signal is translated to a singleended RS-232 transmitter output. RS-232 data received on R2IN is transmitted as an RS-485 signal on Z and Y. RS485 signals received on A and B are transmitted as an RS-232 signal on T1OUT. The RTS line is a common means for controlling bus direction in circuits that convert from RS-232 to RS-485. This line on the RS-232 port controls whether the RS-485 transceiver acts as a transmitter or a receiver (Figure 9). Note that the system cannot be sure that a byte of data in the UART's transmit buffer has been transmitted unless the system monitors the RS-485 driver input, DI. That is, the system must either allow a fixed time delay or actively monitor the DI input before using the DE input to change the bus direction. Other direction-control techniques include using a microcontroller and driving the DE input with data while pulling the A-B lines apart (connecting a pull-up resistor from A to 5V and connecting a pull-down resistor from B to ground). The value of these resistors varies with cable capacitance, but is typically 1k.

Figure 9. The MAX3162 converts bidirectionally between RS-232 and RS-485 signals in a multipoint application.

Port-Powered Devices
Many converters from RS-232 to RS-485 are "port-powered converters" in which the RS-485 power is derived from the RS-232 RTS line (or sometimes a combination of the RTS and CTS (DTR) lines). Because the power available from an RS-232 port is limited, the RS-485 launch voltages are not achieved when using a port-powered converter with, for example, one hundred RS-485 terminations. The low receiver threshold (200mV), however, allows a fair margin for error. This technique is acceptable in systems with short line lengths and without termination resistors across the A-B terminals.

Hot-Swap
When circuit boards are inserted into a hot or powered backplane, differential disturbances to the data bus can lead to data errors. Upon initial circuit-board insertion, the data communication processor undergoes its own power-up sequence. During this period, the processor's logic-output drivers are high impedance and unable to drive the DE and active-low RE inputs of the MAX3060E/MAX3080E to a defined logic level. Leakage currents up to 10mA from the high-impedance state of the processor's logic drivers could cause standard CMOS enable inputs of a transceiver to drift to an incorrect logic level. Additionally, parasitic circuit board capacitance could cause coupling of VCC or GND to the enable inputs. Without the hot-swap capability, these factors could improperly enable a transceiver's driver or receiver. References

1.
2.

RS-422 and RS-485 Application Note, B&B Electronics (This is a great source of information on RS-232, RS485 and RS-422 standards and their practical realizations. http://www.bb-elec.com) Serial Port Complete, Jan Axelson (This definitive reference for serial ports includes considerable useful source code written in Visual Basic. http://www.lvr.com)