1.

LOGIC GATES
Date: AIM:To develop and implementlogic gates by using FPGA and CPLD devices.

APPARATUS:SOFTWARE REQUIREMENTS:Xilinx ISE Design Suite 10.1 Version HARDWARE REQUIREMENTS:1) Personal Computer. 2) Spartan 3E(XC3S100E). 3) Buses.

PROCEDURE:CREATING A SOURCE CODE:1) Click the new source button in the NEW PROJECT WIZARD. 2) Select VHDL/Verilog Module as the source type. 3) Type the file name as indicated below. Ex:- logicgates 4) Verify that add to project checkbox is selected. 5) Write the program, Verify the syntax & Errors by using Behavioral check. 6) Go for the project, right click, add new source in that WIZARD select Test Bench Waveform. 7) Select Unit under Test in the next WIZARD. 8) Give the corresponding user inputs. 9) Simulate the program. IMPLEMENTATION:1) Select Unit under Test as Top Level Module by using right click. 2) Double click on Synthesis.xst.

MODULE DESCRIPTION:. NOT Gate:A NOT gate has only one input and one output. It performs a basic logic function called inversion or complementation. In this logic function, when a HIGH level is applied to this gate as input, a LOW level will appear on its output. When a LOW level is applied to its input, a HIGH will appear on its output. Thus in the logic function, the output of this gate is the complement of the input. AND Gate:AND gate performs logic multiplication. The operation of this gate is such that the output is HIGH only when all of the inputs are HIGH. When any of the inputs are LOW, the output is LOW.
1

OR Gate:An OR gate has two or more inputs and one output. The operation of OR gate is such that a HIGH on the output is produced when any of the inputs are HIGH. The output is LOW only when all of the inputs are LOW. The NAND and NOR gates are very popular logic gates because they have a universal function, i.e., they can be used to construct an AND gate, an OR gate, a NOT gate or any combination of these functions. Hence NAND and NOR gates are known as universal gates. NAND Gate:The term NAND is a construction of NOT-AND and implies an AND function an inverted (NOT) output. The logical operation of this gate in such that a LOW output occurs only when all inputs are HIGH. When any of the inputs are LOW, the output will be HIGH. NOR Gate:The term NOR is a construction of NOT-OR and implies an OR function an inverted (NOT) output. The logical operation of this gate in such that a HIGH output occurs only when all inputs are LOW. When any of the inputs are HIGH, the output will be LOW. EXCLUSIVE-OR Gate:Exclusive-OR logic is a widely used function because of its special arithmetic properties. Hence it is also known as an arithmetic gate. The logical operation of this gate in such that the output is HIGH only when the two inputs are at opposite levels; in other words; the inputs must be different to get a HIGH output.

PROGRAMS:VHDL:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity logicgates is Port ( a,b : in STD_LOGIC; and_2,nand_2,or_2,nor_2,xor_2,xnor_2,not_1,buff_1 : out STD_LOGIC); end logicgates; architecture Behavioral of logicgates is begin process(a,b) begin if(a='1' and b='1')then and_2<='1'; nand_2<='0'; else and_2<='0'; nand_2<='1'; end if; if(a='0' and b='0')then or_2<='0'; nor_2<='1'; else 2

or_2<='1'; nor_2<='0'; end if; if(a=b)then xor_2<='0'; xnor_2<='1'; else xor_2<='1'; xnor_2<='0'; end if; if(a='1')then not_1<='0'; buff_1<='1'; else not_1<='1'; buff_1<='0'; end if; end process; end Behavioral;

VERILOG:module lggate( input a,b, output and_2,nand_2,or_2,nor_2,xor_2,xnor_2,not_1,buff_1); and (and_2,a,b); nand (nand_2,a,b); or (or_2,a,b); nor (nor_2,a,b); xor (xor_2,a,b); xnor (xnor_2,a,b); not (not_1,a); buf (buff_1,a); endmodule

TESTBENCH WAVE FORMS:

TRUTH TABLE:Inputs a b 0 0 0 1 1 0 1 1 And_2 0 0 0 1 Nand_2 1 1 1 0 Or_2 0 1 1 1 Outputs Nor_2 Xor_2 1 0 0 1 0 1 0 0 Xnor_2 1 0 0 1 Not_1 1 1 0 0 Buff_1 0 0 1 1

SYNTHESIS REPORT:* Synthesis Options Summary * ---- Source Parameters Input File Name : "algatesvhdl.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name Output Format Target Device ---- General Options Optimization Goal : Speed Optimization Effort :1 Library Search Order : algatesvhdl.lso Keep Hierarchy : NO Netlist Hierarchy : as_optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator :/ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 * HDL Compilation * Compiling vhdl file "D:/sandhya/algatesvhdl.vhd" in Library work. Entity <algatesvhdl> compiled. Entity <algatesvhdl> (Architecture <Behavioral>) compiled. Design Hierarchy Analysis * Analyzing hierarchy for entity <algatesvhdl> in library <work> (architecture <Behavioral>). HDL Analysis * Analyzing Entity <algatesvhdl> in library <work> (Architecture <Behavioral>). INFO:Xst:2679 - Register <not_2> in unit <algatesvhdl> has a constant value of 1 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register <buff_2> in unit <algatesvhdl> has a constant value of 0 during circuit operation. The register is replaced by logic. Entity <algatesvhdl> analyzed. Unit <algatesvhdl> generated. * * HDL Synthesis

: "algatesvhdl" : NGC : xc3s100e-4-tq144

---- Source Options Top Module Name : algatesvhdl Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 24 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES

Performing bidirectional port resolution... Synthesizing Unit <algatesvhdl>. Related source file "D:/sandhya/algatesvhdl.vhd". Found 1-bit xor2 for <xnor_2$xor0000> created at line 53. Unit <algatesvhdl> synthesized. HDL Synthesis Report

Keep Hierarchy Design Statistics # IOs

: NO

is signal

: 10

Macro Statistics # Xors :1 1-bit xor2 :1 Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx\10.1\ISE. Advanced HDL Synthesis Report Macro Statistics # Xors :1 1-bit xor2 :1 * Low Level Synthesis Optimizing unit <algatesvhdl> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block algatesvhdl, actual ratio is 0. Final Macro Processing ... Final Register Report Found no macro * Partition Report * Partition Implementation Status ------------------------------No Partitions were found in this design. * Final Report * Final Results RTL Top Level Output File Name : algatesvhdl.ngr Top Level Output File Name : algatesvhdl Output Format : NGC Optimization Goal : Speed

Cell Usage : # BELS :8 # GND :1 # LUT2 :6 # VCC :1 # IO Buffers : 10 # IBUF :2 # OBUF :8 Device utilization summary: Selected Device : 3s100etq144-4 Number of Slices: 3 out of 960 0% Number of 4 input LUTs: 6 out of 1920 0% Number of IOs: 10 Number of bonded IOBs: 10 out of 108 9% Partition Resource Summary: No Partitions were found in this design. TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-andROUTE. Clock Information: -----------------No clock signals found in this design Asynchronous Control Signals Information: ---------------------------------------No asynchronous control signals found in this design Timing Summary: --------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 6.458ns Timing Detail: -------------6

All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 12 / 6 Delay: 6.458ns (Levels of Logic = 3) Source: a (PAD) Destination: nor_2 (PAD) Data Path: a to nor_2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 6 1.218 0.844 a_IBUF (a_IBUF) LUT2:I0->O 1 0.704 0.420 or_2_and00001 (nor_2_OBUF)

OBUF:I->O 3.272 nor_2_OBUF (nor_2) ---------------------------------------Total 6.458ns (5.194ns logic, 1.264ns route) (80.4% logic, 19.6% route) Total REAL time to Xst completion: 4.00 secs Total CPU time to Xst completion: 4.69 secs Total memory usage is 148728 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 2 ( 0 filtered)

RTL SCHEMATIC:

OBSERVATION:This program concludes that If anyone the input is low, then the output of AND gate is low. If any one of the input is high, then the output of OR gate is high. If both inputs are different, then the output of EX-OR gate is high. The compliment of AND gate output is always equal to NAND gate. The compliment of OR gate output is always equal to NOR gate. The NOT gate output is compliment of that input. The compliment of EX-OR gate output is always equal to EX-NOR gate.

RESULT:Hence we developed and implemented logic gates by using FPGA and CPLD devices.

2. ADDERS 2a.HALF ADDER

Date: AIM:To develop and implement half adder by using FPGA and CPLD devices.

APPARATUS:SOFTWARE REQUIREMENTS:Xilinx ISE Design Suite 10.1 Version HARDWARE REQUIREMENTS:4) Personal Computer. 5) Spartan 3E(XC3S100E).
6) Buses.

SIMULATION PROCEDURE:CREATING A SOURCE CODE:10) Click the new source button in the NEW PROJECT WIZARD. 11) Select VHDL/Verilog Module as the source type. 12) Type the file name as indicated below. Ex:- halfadder 13) Verify that add to project checkbox is selected. 14) Write the program, Verify the syntax & Errors by using Behavioral check. 15) Go for the project, right click, add new source in that WIZARD select Test Bench Waveform. 16) Select Unit under Test in the next WIZARD. 17) Give the corresponding user inputs. 18) Simulate the program. IMPLEMENTATION:3) Select Unit under Test as Top Level Module by using right click. 4) Double click on Synthesis.xst.

MODULE DESCRIPTION:Logic circuits for digitally performing the arithmetic operations addition, subtraction, multiplication and division are known as Arithmetic Circuits. A logic circuit for the addition of two one-bit binary numbers is known as a Half Adder. The function of this circuit is to add two binary digits, producing a sum and a carry. The logical operation of Half adder is such that the carry output is a 1 only when both inputs are 1s; therefore carry output can be expressed as AND of the input variable. Carry => a.b The sum output is a 1 only if both input variables are not equal. Therefore the sum can be expressed as EX-OR of the input variables.

Sum => ab

PROGRAMES:VHDL:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HALFADDRVHDL is Port ( A,B : in STD_LOGIC; C,S : out STD_LOGIC); end HALFADDRVHDL; architecture Behavioral of HALFADDRVHDL is signal s1:std_logic_vector(0 to 1); begin s1<=a & b; process(s1) begin case s1 is when "00"=>s<='0';c<='0'; when "01"=>s<='1';c<='0'; when "10"=>s<='1';c<='0'; when "11"=>s<='0';c<='1'; when others =>s<='U';c<='U'; end case; end process; end Behavioral; VERILOG:module halfbeha (input a,b, output sum,carry); assign sum=a^b; assign carry=a&b; endmodule

TRUTH TABLE:
A 0 0 1 1 B 0 1 0 1 Sum 0 1 1 0 Carry 0 0 0 1

WAVE FORMS:-

SYNTHESIS REPORT:Synthesis Options Summary Source Parameters Input File Name : "HALFADDRVHDL.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "HALFADDRVHDL" Output Format : NGC Target Device : xc3s100e-4tq144 ---- Source Options Top Module Name : HALFADDRVHDL Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 24 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort :1 Library Search Order : HALFADDRVHDL.lso Keep Hierarchy : NO Netlist Hierarchy : as_optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator :/ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 * HDL Compilation Compiling vhdl file "D:/sandhya/HALFADDRVHDL.vhd" in Library work. Entity <HALFADDRVHDL> compiled. Entity <HALFADDRVHDL> (Architecture <Behavioral>) compiled. * Design Hierarchy Analysis * Analyzing hierarchy for entity <HALFADDRVHDL> in library <work> (architecture <Behavioral>). * HDL Analysis Analyzing Entity <HALFADDRVHDL> in library <work> (Architecture <Behavioral>).

INFO:Xst:1561 "D:/sandhya/HALFADDRVHDL.vhd" line 46: Mux is complete : default of case is discarded Entity <HALFADDRVHDL> analyzed. Unit <HALFADDRVHDL> generated. * HDL Synthesis Performing bidirectional port resolution... Synthesizing Unit <HALFADDRVHDL>. Related source file is "D:/sandhya/HALFADDRVHDL.vhd". Found 4x2-bit ROM for signal <s1$rom0000>. Summary: inferred 1 ROM(s). Unit <HALFADDRVHDL> synthesized. HDL Synthesis Report Macro Statistics # ROMs :1 4x2-bit ROM :1 * Advanced HDL Synthesis Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx\10.1\ISE. Advanced HDL Synthesis Report Macro Statistics # ROMs :1 4x2-bit ROM :1 * Low Level Synthesis Optimizing unit <HALFADDRVHDL> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block HALFADDRVHDL, actual ratio is 0. Final Macro Processing ... Final Register Report Found no macro * Partition Report Partition Implementation Status No Partitions were found in this design. * Final Report Final Results RTL Top Level Output File Name : HALFADDRVHDL.ngr

Top Level Output File Name : HALFADDRVHDL Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs

:4

Cell Usage : # BELS :2 # LUT2 :2 # IO Buffers :4 # IBUF :2 # OBUF :2 Device utilization summary: Selected Device : 3s100etq144-4 Number of Slices: 1 out of 960 0% Number of 4 input LUTs: 2 out of 1920 0% Number of IOs: 4 Number of bonded IOBs: 4 out of 108 3% Partition Resource Summary: No Partitions were found in this design. TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-andROUTE. Clock Information: No clock signals found in this design Asynchronous Control Signals Information: No asynchronous control signals found in this design Timing Summary: --------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found Maximum combinational path delay: 6.236ns Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 4 /2 Delay: 6.236ns (Levels of Logic = 3) Source: B (PAD) Destination: C (PAD) Data Path: B to C Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) IBUF:I->O 2 1.218 0.622 B_IBUF (B_IBUF) LUT2:I0->O 1 0.704 0.420 Mrom_s1_rom0000111 (Mrom_s1_rom00001)

OBUF:I->O 3.272 C_OBUF (C) ---------------------------------------Total 6.236ns (5.194ns logic, 1.042ns route) (83.3% logic, 16.7% route) Total REAL time to Xst completion: 3.00 secs Total CPU time to Xst completion: 2.92 secs Total memory usage is 148728 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 1 ( 0 filtere

SCHEMATIC DIAGRAMS:

OBSERVATION:This program concludes that If all the inputs are low, then the output of sum is low and the output of carry is low. If all the inputs are high, then the output of sum is low and the output of carry is high. If any one of the input is high, the output of sum is high and output of carry is low.

RESULT:Hence we developed and implemented half adder by using FPGA and CPLD devices.

2B. FULL ADDER

Exp.no.3 AIM: To develop and implement full adder using CPLD. APPARATUS: SOFTWARE: Xilinx ISE design suite version 10.0 HARDWARE:Spartan 3e Xc3s100e-4tq144 Busses. THEORY: It was said earlier that the circuit of the half adder can be extended to a full adder. This can be achieved thru two half adders. Basically, the full adder circuit is used to add three bits. It has three inputs, the three data bits. It has two outputs, the sum and the carry. The sum is the XOR of the three inputs and the carry is the cyclic AND of the inputs, two at a time. When compared to half adder, the delay with the full adder is carries more delay. The full adder is the basic of both the ripple carry adder and the carry look ahead adder. PROCEDURE: Click the new source in the new project wizard. Type the file name as indicated below eg: logic gates. Select the vhdl/verilog as source type. Write the program and verify the syntax and errors by using behavior check syntax. Go for the project, give right click, add new source in the wizard and select the test bench wave form, type the file name as eg: logicgateswave. Select the unit under test in the next wizard. Give the corresponding user inputs. Simulate the program and observe the inputs. Select the source as implementation and set the required program as top module. Then synthesize the program. View the synthesis report and observe the schematic diagrams. Date:

PROGRAM:
Vhdl program:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityfull_adder is Port ( a,b,c : in STD_LOGIC;

s,co : out STD_LOGIC); endfull_adder; architecture Behavioral of full_adder is signal s1:std_logic_vector(0 to 2); begin s1<= a & b & c; process(s1) begin case s1 is when "000"=>s<='0';co<='0'; when "001"=>s<='1';co<='0'; when "010"=>s<='1';co<='0'; when "011"=>s<='0';co<='1'; when "100"=>s<='1';co<='0'; when "101"=>s<='0';co<='1'; when "110"=>s<='0';co<='1'; when "111"=>s<='1';co<='1'; end case; end process; end Behavioral; Verilog program: modulefull_adder_veri( inputa,b,c, outputs,co ); wire w1,w2,w3; assign s = a ^ b ^ c; assign w1 = a & b; assign w2 = c & b; assign w3 = c & a; assign co = w1 | w2 | w3; endmodule

WAVEFORMS:
:

SYNTHESIS REPORT:
TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT Synthesis Options Summary ---- Source Parameters Input File Name : "full_adder.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name Output Format Target Device tq144 Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer (BUFG) : 24 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort :1 Library Search Order : full_adder.lso Keep Hierarchy : NO Netlist Hierarchy : as_optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator :/ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5

: "full_adder" : NGC : xc3s100e-4-

---- Source Options Top Module Name : full_adder Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES

8x2-bit ROM HDL Compilation Advanced HDL Synthesis Compiling vhdl file "E:/Xilinx_lab/lab_prog/full_adder.vhd" in Library work. Entity <full_adder> compiled. Entity <full_adder> (Architecture <Behavioral>) compiled. Design Hierarchy Analysis Analyzing hierarchy for entity <full_adder> in library <work> (architecture <Behavioral>). HDL Analysis Analyzing Entity <full_adder> in library <work> (Architecture <Behavioral>). INFO:Xst:1561 "E:/Xilinx_lab/lab_prog/full_adder.vhd" line 49: Mux is complete : default of case is discarded Entity <full_adder> analyzed. Unit <full_adder> generated.

:1

Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx\10.1\ISE. Advanced HDL Synthesis Report Macro Statistics # ROMs 8x2-bit ROM Low Level Synthesis Optimizing unit <full_adder>... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block full_adder, actual ratio is 0. Final Macro Processing... Final Register Report Found no macro

:1 :1

HDL Synthesis Performing bidirectional port resolution... Synthesizing Unit <full_adder>. Related source file is "E:/Xilinx_lab/lab_prog/full_adder.vhd". Found 8x2-bit ROM for signal <s1$rom0000>. Summary: inferred 1 ROM(s). Unit <full_adder> synthesized.

Partition Report Partition Implementation Status No Partitions were found in this design. Final Report Final Results RTL Top Level Output File Name : full_adder.ngr Top Level Output File Name : full_adder Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs :1

HDL Synthesis Report Macro Statistics # ROMs :5

Cell Usage: # BELS # LUT3 # IO Buffers # IBUF # OBUF

:2 :2 :5 :3 :2

Maximum combinational path delay: 6.236ns Timing Detail: All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 6 /2 Delay: 6.236ns (Levels of Logic = 3) Source: b (PAD) Destination: co (PAD) Data Path: b to co 5 5 out Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) IBUF:I->O 2 1.218 0.622 b_IBUF (b_IBUF) LUT3:I0->O 1 0.704 0.420 Mrom_s1_rom0000111 (Mrom_s1_rom00001) OBUF:I->O 3.272 co_OBUF (co) Total 6.236ns (5.194ns logic, 1.042ns route) (83.3% logic, 16.7% route) Total REAL time to Xst completion: 3.00 secs Total CPU time to Xst completion: 3.25 secs Total memory usage is 148148 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings: 0 ( 0 filtered) Number of infos : 1 ( 0 filtered)

Device utilization summary: Selected Device: 3s100etq144-4 Number of Slices: 960 0% Number of 4 input LUTs: of 1920 0% Number of IOs: Number of bonded IOBs: of 108 4% 1 out of 2 out

Partition Resource Summary: No Partitions were found in this design. TIMING REPORT Clock Information: No clock signals found in this design Asynchronous Control Signals Information: No asynchronous control signals found in this design Timing Summary: Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found

SCHEMATIC DIAGRAMS:

RESULT:
VHDL and Verilog program for full adder was developed and implemented.

2c.RIPPLE CARRY ADDER

Date: AIM:To develop and implement ripple carry adder by using FPGA and CPLD devices.

APPARATUS:SOFTWARE REQUIREMENTS:Xilinx ISE Design Suite 10.1 Version HARDWARE REQUIREMENTS:7) Personal Computer. 8) Spartan 3E(XC3S100E). 9) Buses.

SIMULATION PROCEDURE:CREATING A SOURCE CODE:19) Click the new source button in the NEW PROJECT WIZARD. 20) Select VHDL/Verilog Module as the source type. 21) Type the file name as indicated below. Ex:- rcabeha 22) Verify that add to project checkbox is selected. 23) Write the program, Verify the syntax & Errors by using Behavioral check. 24) Go for the project, right click, add new source in that WIZARD select Test Bench Waveform. 25) Select Unit under Test in the next WIZARD. 26) Give the corresponding user inputs. 27) Simulate the program. IMPLEMENTATION:5) Select Unit under Test as Top Level Module by using right click. 6) Double click on Synthesis.xst.

MODULE DESCRIPTION:A logical circuit using multiple full adders to add N-bit binary numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a Ripple Carry Adder, since each carry bit ripples to the next full adder. The first (and only the first) full adder may be replaced by a half adder. The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic.

ASCET(M.TECH) VLSI

Page 23

PROGRAMES:VHDL:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rca_beha is Port ( n1 : in STD_LOGIC_VECTOR (3 downto 0); n2 : in STD_LOGIC_VECTOR (3 downto 0); sum : out STD_LOGIC_VECTOR (3 downto 0); carry : out STD_LOGIC); end rca_beha; architecture Behavioral of rca_beha is signal c0,c1,c2,c3:STD_LOGIC; begin process(n1,n2,c0,c1,c2,c3) begin sum(0)<=n1(0) xor n2(0); c0<=n1(0) and n2(0); sum(1)<=n1(1) xor n2(1) xor c0; c1<=(n1(1) and n2(1))or(n2(1) and c0)or(c0 and n1(1)); sum(2)<=n1(2) xor n2(2) xor c1; c2<=(n1(2) and n2(2))or(n2(2) and c1)or(c1 and n1(2)); sum(3)<=n1(3) xor n2(3) xor c2; c3<=(n1(3) and n2(3))or(n2(3) and c2)or(c2 and n1(3)); carry<=c3; end process; end Behavioral;

VERILOG:module rcabeha( input [3:0] n1,n2, output [3:0] sum, output carry); wire c0,c1,c2,c3,c4; assign sum[0]=n1[0]^n2[0]; assign c0=n1[0]&n2[0]; assign sum[1]=(n1[1]^n2[1]^c0); assign c1=(n1[1]&n2[1])|(n2[1]&c0)|(c0&n1[1]); assign sum[2]=(n1[2]^n2[2]^c1); assign c2=(n1[2]&n2[2])|(n2[2]&c1)|(c1&n1[2]); assign sum[3]=(n1[3]^n2[3]^c2); assign c3=(n1[3]&n2[3])|(n2[3]&c2)|(c2&n1[3]); assign carry=c3; endmodule

ASCET(M.TECH) VLSI

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WAVE FORMS:-

ASCET(M.TECH) VLSI

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SYNTHESIS REPORT:TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT Synthesis Options Summary ---- Source Parameters Input File Name : "rcabeha.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "rcabeha" Output Format : NGC Target Device : xc3s100e-4-tq144 ---- Source Options Top Module Name : rcabeha Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : auto Automatic Register Balancing : No ---- Target Options ASCET(M.TECH) VLSI Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 24 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort :1 Library Search Order : rcabeha.lso Keep Hierarchy : NO Netlist Hierarchy : as_optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator :/ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 HDL Compilation Compiling vhdl file "D:/sandhya/rcabeha.vhd" in Library work. Entity <rcabeha> compiled. Entity <rcabeha> (Architecture <Behavioral>) compiled. Design Hierarchy Analysis Analyzing hierarchy for entity <rcabeha> in library <work> (architecture <Behavioral>). HDL Analysis Analyzing Entity <rcabeha> in library <work> (Architecture <Behavioral>). Entity <rcabeha> analyzed. Unit <rcabeha> generated. HDL Synthesis Performing bidirectional port resolution... Page 24

Synthesizing Unit <rcabeha>. Related source file is "D:/sandhya/rcabeha.vhd". Found 4-bit xor3 for signal <sum>. Summary: inferred 4 Xor(s). Unit <rcabeha> synthesized. HDL Synthesis Report Macro Statistics # Xors :4 1-bit xor3 :4 Advanced HDL Synthesis Loading device for application Rf_Device from file '3s100e.nph' in environment D:\Xilinx\10.1\ISE. Advanced HDL Synthesis Report Macro Statistics # Xors :4 1-bit xor3 :4 Low Level Synthesis Optimizing unit <rcabeha> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block rcabeha, actual ratio is 0. Final Macro Processing ... Final Register Report Found no macro Partition Report Partition Implementation Status ------------------------------No Partitions were found in this design. ------------------------------Final Report Final Results RTL Top Level Output File Name : rcabeha.ngr Top Level Output File Name : rcabeha Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 14 Cell Usage : # BELS :8 # LUT3 :8 # IO Buffers : 14 # IBUF :9 # OBUF :5 Device utilization summary: --------------------------ASCET(M.TECH) VLSI

Selected Device : 3s100etq144-4 Number of Slices: 4 out of 960 0% Number of 4 input LUTs: 8 out of 1920 0% Number of IOs: 14 Number of bonded IOBs: 14 out of 108 12% --------------------------Partition Resource Summary: --------------------------No Partitions were found in this design. --------------------------TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-andROUTE. Clock Information: -----------------No clock signals found in this design Asynchronous Control Signals Information: ---------------------------------------No asynchronous control signals found in this design Timing Summary: --------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 9.926ns Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 33 / 5 -----------------------------------------------------------------------Delay: 9.926ns (Levels of Logic = 6) Source: b<0> (PAD) Destination: carry (PAD) Data Path: b<0> to carry Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) Page 25

---------------------------------------- -----------IBUF:I->O 2 1.218 0.622 b_0_IBUF (b_0_IBUF) LUT3:I0->O 2 0.704 0.526 c_1_or00001 (c<1>) LUT3:I1->O 2 0.704 0.526 c_2_or00001 (c<2>) LUT3:I1->O 2 0.704 0.526 c_3_or00001 (c<3>) LUT3:I1->O 1 0.704 0.420 c_4_or00001 (c<4>) OBUF:I->O 3.272 carry_OBUF (carry)

---------------------------------------Total 9.926ns (7.306ns logic, 2.620ns route) (73.6% logic, 26.4% route) Total REAL time to Xst completion: 5.00 secs Total CPU time to Xst completion: 5.05 secs Total memory usage is 149248 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)

CIRCUIT DIAGRAMS:-

ASCET(M.TECH) VLSI

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OBSERVATION:This program concludes that When we perform an addition of two n-bit numbers, the result can be n+ 1 bit. In that n-bit is represent sum and remaining one bit is represent carry.

RESULT:Hence we developed and implemented ripple carry adder by using FPGA and CPLD devices.

2d. CARRY LOOK AHEAD ADDER

Date: AIM:To develop and implement carry look ahead adder by using FPGA and CPLD devices.

APPARATUS:SOFTWARE REQUIREMENTS:Xilinx ISE Design Suite 10.1 Version HARDWARE REQUIREMENTS:10) Personal Computer. 11) Spartan 3E(XC3S100E). 12) Buses.

PROCEDURE:CREATING A SOURCE CODE:28) Click the new source button in the NEW PROJECT WIZARD. 29) Select VHDL/Verilog Module as the source type. 30) Type the file name as indicated below. Ex:- clah_adder 31) Verify that add to project checkbox is selected. 32) Write the program, Verify the syntax & Errors by using Behavioural check. 33) Go for the project, right click, add new source in that WIZARD select Test Bench Waveform. 34) Select Unit under Test in the next WIZARD. 35) Give the corresponding user inputs. 36) Simulate the program. IMPLEMENTATION:7) Select Unit under Test as Top Level Module by using right click. 8) Double click on Synthesis.xst.

MODULE DESCRIPTION:The reduce the computation time, engineers devised faster ways to add two binary numbers by using carry look ahead adders. They work by creating two signals (P and G) each bit position, based on if a carry is propagated through from a less significant position (at least one input is a 1), a carry is generated in that bit position (both inputs are 1), or if a carry is killed in that bit position (both inputs are 0). In most cases, p is simply the sum output of half adder and G is the carry output of the same adder. After P and G re generated the carriers for very bit position are created.

PROGRAMS:VHDL:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity caladder is Port ( x_in,y_in : in STD_LOGIC_VECTOR (3 downto 0); carry_in : in STD_LOGIC; sum : out STD_LOGIC_VECTOR (3 downto 0); carry_out : out STD_LOGIC); end caladder; architecture Behavioral of caladder is signal h_sum:STD_LOGIC_VECTOR (3 downto 0); signal c_g:STD_LOGIC_VECTOR (3 downto 0); signal c_p:STD_LOGIC_VECTOR (3 downto 0); signal carry_in_internal:STD_LOGIC_VECTOR (3 downto 1); begin h_sum<=x_in xor y_in; c_g<=x_in and y_in; c_p<=x_in or y_in; process(c_g,c_p,carry_in_internal) begin carry_in_internal(1)<=c_g(0) or (c_p(0) and carry_in); for i in 1 to 2 loop carry_in_internal(i+1)<=c_g(i) or (c_p(i) and carry_in_internal(i)); end loop; carry_out<=c_g(3) or (c_p(3) and carry_in_internal(3)); end process; sum(0)<=h_sum(0) xor carry_in; sum(3 downto 1)<=h_sum(3 downto 1) xor carry_in_internal(3 downto 1); end Behavioral;

VERILOG:module claadde( input [3:0] x,y, input cin, output [3:0] sum, output carry); wire [3:0] g,p; wire [4:0] c; assign c[0]=cin; assign g[3:0]=x[3:0]&y[3:0]; assign p[3:0]=x[3:0]^y[3:0]; assign c[1]=g[0]|(p[0]&cin); assign c[2]=g[1]|(p[1]&g[0])|(p[1]&p[0]&cin); assign c[3]=g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&cin); assign c[4]=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0]) |(p[3]&p[2]&p[1]&p[0]&cin); assign sum[3:0]=p[3:0]^c[3:0]; assign carry=c[4]; endmodule

TESTBENCH WAVE FORMS:-

SYNTHESIS REPORT:Synthesis Options Summary ---- Source Parameters Input File Name : "caladder.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "caladder" Output Format : NGC Target Device : xc3s100e-4tq144 ---- Source Options Top Module Name : caladder Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 24 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort :1 Library Search Order : caladder.lso Keep Hierarchy : NO Netlist Hierarchy : as_optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator :/ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 HDL Compilation Compiling vhdl file "D:/sandhya/caladder.vhd" in Library work. Entity <caladder> compiled. Entity <caladder> (Architecture <Behavioral>) compiled. Design Hierarchy Analysis Analyzing hierarchy for entity <caladder> in library <work> (architecture <Behavioral>). HDL Analysis Analyzing Entity <caladder> in library <work> (Architecture <Behavioral>). WARNING:Xst:819 "D:/sandhya /caladder.vhd" line 47: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <carry_in> Entity <caladder> analyzed. Unit <caladder> generated. HDL Synthesis Performing bidirectional port resolution... Synthesizing Unit <caladder>. Related source file is "D:/sandhya /caladder.vhd". Found 4-bit xor2 for signal <sum>.

Found 4-bit xor2 for signal <h_sum>. Unit <caladder> synthesized. HDL Synthesis Report Macro Statistics # Xors :5 1-bit xor2 :4 4-bit xor2 :1 Advanced HDL Synthesis Loading device for application Rf_Device from file '3s100e.nph' in environment D:\Xilinx\10.1\ISE. Advanced HDL Synthesis Report Macro Statistics # Xors :5 1-bit xor2 :4 4-bit xor2 :1 Low Level Synthesis Optimizing unit <caladder> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block caladder, actual ratio is 0. Final Macro Processing ... Final Register Report Found no macro Partition Report Partition Implementation Status ------------------------------No Partitions were found in this design. ------------------------------Final Report Final Results RTL Top Level Output File Name : caladder.ngr Top Level Output File Name : caladder Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 14 Cell Usage : # BELS :8 # LUT3 :8 # IO Buffers : 14 # IBUF :9 # OBUF :5 Device utilization summary: --------------------------Selected Device : 3s100etq144-4 Number of Slices: 4 out of 960 0% Number of 4 input LUTs: 8 out of 1920 0% Number of IOs: 14

Number of bonded IOBs: 14 out of 108 12% --------------------------Partition Resource Summary: --------------------------No Partitions were found in this design. --------------------------TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-andROUTE. Clock Information: -----------------No clock signals found in this design Asynchronous Control Signals Information: ---------------------------------------No asynchronous control signals found in this design Timing Summary: --------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 9.934ns Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 33 / 5 -----------------------------------------------------------------------Delay: 9.934ns (Levels of Logic = 6) Source: x_in<0> (PAD) Destination: sum<3> (PAD) Data Path: x_in<0> to sum<3> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 2 1.218 0.622 x_in_0_IBUF (x_in_0_IBUF) LUT3:I0->O 2 0.704 0.482 carry_in_internal_1_or00001 (carry_in_internal<1>)

LUT3:I2->O 2 0.704 0.482 carry_in_internal_2_or00001 (carry_in_internal<2>) LUT3:I2->O 2 0.704 0.622 carry_in_internal_3_or00001 (carry_in_internal<3>) LUT3:I0->O 1 0.704 0.420 Mxor_sum<3>_Result1 (sum_3_OBUF)

OBUF:I->O 3.272 sum_3_OBUF (sum<3>) ---------------------------------------Total 9.934ns (7.306ns logic,

SCHEMATIC DIAGRAMS:

OBSERVATION:This program concludes that The outputs of ripple carry adder and carry look ahead adder both are same. The difference between these two is speed of operation. Carry look ahead adder is very faster than the ripple carry adder. Because the carry look adder calculates one or more carry bits before the sum. In that the ripple carry adder for which the carry bit is calculates alongside the sum bit, and each bit must wait until the previous carry has been calculated to begin calculating its own result and carry bits.

RESULT:Hence we developed and implemented carry look ahead adder by using FPGA and CPLD devices.

3a. MULTIPLEXER (8x1)

Date: AIM:To develop and implement multiplexer (8x1) by using FPGA and CPLD devices.

APPARATUS:SOFTWARE REQUIREMENTS:Xilinx ISE Design Suite 10.1 Version HARDWARE REQUIREMENTS:1) Personal Computer. 2) Spartan 3E(XC3S100E). 3) Buses.

SIMULATION PROCEDURE:CREATING A SOURCE CODE:1) Click the new source button in the NEW PROJECT WIZARD. 2) Select VHDL/Verilog Module as the source type. 3) Type the file name as indicated below. Ex:- mux8beha 4) Verify that add to project checkbox is selected. 5) Write the program, Verify the syntax & Errors by using Behavioral check. 6) Go for the project, right click, add new source in that WIZARD select Test Bench Waveform. 7) Select Unit under Test in the next WIZARD. 8) Give the corresponding user inputs. 9) Simulate the program. IMPLEMENTATION:1) Select Unit under Test as Top Level Module by using right click. 2) Double click on Synthesis.xst.

MODULE DESCRIPTION:Multiplexer or Data selector is a logic circuit that has several data-input lines and a single output line. It also consists data-select inputs that permit digital data on any one of the inputs to be switched to the output line.

PROGRAMS:VHDL:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux8beha is Port ( g : in STD_LOGIC; s : in STD_LOGIC_VECTOR (2 downto 0); d : in STD_LOGIC_VECTOR (7 downto 0); y,y1 : out STD_LOGIC); end mux8beha; architecture Behavioral of mux8beha is begin process(g,s,d) begin if(g='0')then case s is when"000"=>y<=d(0);y1<=not d(0); when"001"=>y<=d(1);y1<=not d(1); when"010"=>y<=d(2);y1<=not d(2); when"011"=>y<=d(3);y1<=not d(3); when"100"=>y<=d(4);y1<=not d(4); when"101"=>y<=d(5);y1<=not d(5); when"110"=>y<=d(6);y1<=not d(6); when"111"=>y<=d(7);y1<=not d(7); when others=>null; end case; else y<='0';y1<='1'; end if; end process; end Behavioral;

VERILOG:-

module mux74151( input [7:0] d, input [2:0] s, input en, output reg y, output reg ybar ); reg w; always @(d or s or en) begin case(s) 3'b000 : w=d[0]; 3'b001 : w=d[1]; 3'b010 : w=d[2]; 3'b011 : w=d[3]; 3'b100 : w=d[4]; 3'b101 : w=d[5];

3'b110 : w=d[6]; 3'b111 : w=d[7]; default : w="U"; endcase if(en==0) y=w; //ybar= ~y; else y="U"; // ybar="U"; end endmodule

WAVE FORMS:-

TRUTH TABLE:Inputs g 1 0 0 0 0 0 0 0 0 S(2) X 0 0 0 0 1 1 1 1 S(1) X 0 0 1 1 0 0 1 1 S(0) X 0 1 0 1 0 1 0 1 Outputs Y 0 d(0) d(1) d(2) d(3) d(4) d(5) d(6) d(7) Y1 1

SYNTHESIS REPORT:
* Synthesis Options Summary * ---- Source Parameters Input File Name : "Mux8to1.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "Mux8to1" Output Format : NGC Target Device : xc3s100e-4tq144 ---- Source Options Top Module Name : Mux8to1 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 24 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES --- General Options Optimization Goal : Speed Optimization Effort :1 Library Search Order : Mux8to1.lso Keep Hierarchy : NO Netlist Hierarchy : as_optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator :/ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 * HDL Compilation * WARNING:HDLParsers:3607 - Unit work/Mux8to1 is now defined in a different file. It was defined in "D:/Sumanth/Mux8to1.vhd", and is now defined in "F:/sandhya/Mux8to1.vhd". WARNING:HDLParsers:3607 - Unit work/Mux8to1/Behavioral is now defined in a different file. It was defined in "D:/Sumanth/Mux8to1.vhd", and is now defined in "F:/sandhya/Mux8to1.vhd". Compiling vhdl file "F:/sandhya/Mux8to1.vhd" in Library work. Entity <mux8to1> compiled. Entity <mux8to1> (Architecture <behavioral>) compiled. Design Hierarchy Analysis Analyzing hierarchy for entity <Mux8to1> in library <work> (architecture <behavioral>). HDL Analysis

Analyzing Entity <Mux8to1> in library <work> (Architecture <behavioral>). INFO:Xst:1561 "F:/sandhya/Mux8to1.vhd" line 51: Mux is complete : default of case is discarded Entity <Mux8to1> analyzed. Unit Mux8to1> generated. * HDL Synthesis * Performing bidirectional port resolution... Synthesizing Unit <Mux8to1>. Related source file is "F:/sandhya/Mux8to1.vhd". Unit <Mux8to1> synthesized. HDL Synthesis Report Found no macro * Advanced HDL Synthesis * Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx\10.1\ISE. Advanced HDL Synthesis Report Found no macro * Low Level Synthesis Optimizing unit <Mux8to1> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block Mux8to1, actual ratio is 0. Final Macro Processing ... ============= Final Register Report Found no macro * Partition Report Partition Implementation Status No Partitions were found in this design. * Final Report * Final Results RTL Top Level Output File Name : Mux8to1.ngr

Top Level Output File Name : Mux8to1 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs

: 14

Cell Usage : # BELS :8 # LUT2 :2 # LUT4 :5 # MUXF5 :1 # IO Buffers : 14 # IBUF : 12 # OBUF :2 Device utilization summary: Selected Device : 3s100etq144-4 Number of Slices: 4 out of 960 0% Number of 4 input LUTs: 7 out of 1920 0% Number of IOs: 14 Number of bonded IOBs: 14 out of 108 12% -------------------------Partition Resource Summary: --------------------------No Partitions were found in this design.-------------------------TIMING REPORT Clock Information: -----------------No clock signals found in this design Asynchronous Control Signals Information: ---------------------------------------No asynchronous control signals found in this design Timing Summary: --------------Speed Grade: -4 Minimum period: No path found

Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 9.126ns Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 38 / 2 Delay: 9.126ns (Levels of Logic = 6) Source: a (PAD) Destination: xbar (PAD) Data Path: a to xbar Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ----------IBUF:I->O 3 1.218 0.706 a_IBUF (a_IBUF) LUT4:I0->O 1 0.704 0.000 x97_F (N8)

MUXF5:I0->O 1 0.321 0.455 x97 (x97) LUT4:I2->O 2 0.704 0.622 x111 (x111) LUT2:I0->O 1 0.704 0.420 xbar1 (xbar_OBUF) OBUF:I->O 3.272 xbar_OBUF (xbar) ---------------------------------------Total 9.126ns (6.923ns logic, 2.203ns route) (75.9% logic, 24.1% route)

Total REAL time to Xst completion: 5.00 secs Total CPU time to Xst completion: 5.17 secs

Total memory usage is 148728 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 2 ( 0 filtered) Number of infos : 1 ( 0 filtered)

SCHEMATIC DIAGRAMS:

OBSERVATION:This program concludes that The above multiplexer(8x1) consists of 3 data select lines, 8 data inputs and single output line . We have 3 data select lines so, we get 23=8 select bits, each of the 8 data-input lines can be selected. S(0),S(1) and S(2) are the 8 data select inputs that allow the data on the corresponding data input to pass through to the data output.

RESULT:Hence we developed and implemented multiplexer (8x1) by using FPGA and CPLD devices.

3b. MULTIPLEXER (16x1)

Date: AIM:To develop and implement multiplexer (16x1) by using FPGA and CPLD devices.

APPARATUS:SOFTWARE REQUIREMENTS:Xilinx ISE Design Suite 10.1 Version HARDWARE REQUIREMENTS:4) Personal Computer. 5) Spartan 3E(XC3S100E). 6) Buses.

SIMULATION PROCEDURE:CREATING A SOURCE CODE:10) Click the new source button in the NEW PROJECT WIZARD. 11) Select VHDL/Verilog Module as the source type. 12) Type the file name as indicated below. Ex:- mux16beha 13) Verify that add to project checkbox is selected. 14) Write the program, Verify the syntax & Errors by using Behavioral check. 15) Go for the project, right click, add new source in that WIZARD select Test Bench Waveform. 16) Select Unit under Test in the next WIZARD. 17) Give the corresponding user inputs. 18) Simulate the program. IMPLEMENTATION:3) Select Unit under Test as Top Level Module by using right click. 4) Double click on Synthesis.xst.

MODULE DESCRIPTION:Multiplexer or Data selector is a logic circuit that has several data-input lines and a single output line. It also consists data-select inputs that permit digital data on any one of the inputs to be switched to the output line.

PROGRAMS:VHDL:entity mux16beha is Port ( g : in STD_LOGIC; s : in STD_LOGIC_VECTOR (3 downto 0);

d : in STD_LOGIC_VECTOR (15 downto 0); if(g='0')then case s is when"0000"=>y<=d(0);y1<=not d(0); when"0001"=>y<=d(1);y1<=not d(1); when"0010"=>y<=d(2);y1<=not d(2); when"0011"=>y<=d(3);y1<=not d(3); when"0100"=>y<=d(4);y1<=not d(4); when"0101"=>y<=d(5);y1<=not d(5); when"0110"=>y<=d(6);y1<=not d(6); when"0111"=>y<=d(7);y1<=not d(7); when"1000"=>y<=d(8);y1<=not d(8); when"1001"=>y<=d(9);y1<=not d(9); when"1010"=>y<=d(10);y1<=not d(10); when"1011"=>y<=d(11);y1<=not d(11); when"1100"=>y<=d(12);y1<=not d(12); when"1101"=>y<=d(13);y1<=not d(13); when"1110"=>y<=d(14);y1<=not d(14); when"1111"=>y<=d(15);y1<=not d(15); when others=>null; end case; else y<='0';y1<='1'; end if; end process; end Behavioral VERILOG: module mux16x1( input g, input [3:0] s, input [15:0] d, output reg y); always@(g,s,d) begin if(g==0) case(s) 0:y=d[0]; 1:y=d[1]; 2:y=d[2]; 3:y=d[3]; 4:y=d[4]; 5:y=d[5]; 6:y=d[6]; 7:y=d[7]; 8:y=d[8]; 9:y=d[9]; 10:y=d[10]; 11:y=d[11]; 12:y=d[12]; 13:y=d[13];

14:y=d[14]; 15:y=d[15]; endcase else y=0; end endmodule

WAVE FORMS:-

TRUTH TABLE:g 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S(3) X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Inputs S(2) X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S(1) X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S(0) X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Outputs Y Y1 0 1 d(0) d(1) d(2) d(3) d(4) d(5) d(6) d(7) d(8) d(9) d(10) d(11) d(12) d(13) d(14) d(15)

SYNTHESIS REPORT:Release 10.1 - xst K.31 (nt) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to F:/sandhya/xst/projnav.tmp Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 1.39 secs --> Parameter xsthdpdir set to F:/sandhya/xst Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 1.39 secs Reading design: mux16to1.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT Synthesis Options Summary ---- Source Parameters Input File Name : "mux16to1.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name Output Format Target Device Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 24 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort :1 Library Search Order : mux16to1.lso Keep Hierarchy : NO Netlist Hierarchy : as_optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator :/ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 * * HDL Compilation

: "mux16to1" : NGC : xc3s100e-4-tq144

---- Source Options Top Module Name : mux16to1 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto

WARNING:HDLParsers:3607 Unit work/mux16to1 is now defined in a different file. It was defined in "D:/Sumanth/mux16to1.vhd", and is now defined in "F:/sandhya/mux16to1.vhd". WARNING:HDLParsers:3607 Unit work/mux16to1/Behavioral is now defined in a different file. It was defined in "D:/Sumanth/mux16to1.vhd", and is now defined in "F:/sandhya/mux16to1.vhd". Compiling vhdl file "F:/sandhya/mux16to1.vhd" in Library work. Architecture behavioral of Entity mux16to1 is up to date. Design Hierarchy Analysis Analyzing hierarchy for entity <mux16to1> in library <work> (architecture <behavioral>). * HDL Analysis Analyzing Entity <mux16to1> in library <work> (Architecture <behavioral>). INFO:Xst:1561 - "F:/sandhya/mux16to1.vhd" line 58: Mux is complete : default of case is discarded Entity <mux16to1> analyzed. Unit <mux16to1> generated. * HDL Synthesis Performing bidirectional port resolution... Synthesizing Unit <mux16to1>. Related source file is "F:/sandhya/mux16to1.vhd". Unit <mux16to1> synthesized. HDL Synthesis Report Found no macro Advanced HDL Synthesis Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx\10.1\ISE. Advanced HDL Synthesis Report Found no macro Low Level Optimizing unit <mux16to1> ... Synthesis

Found no macro * Partition Report *Partition Implementation Status No Partitions were found in this design. Final Results RTL Top Level Output File Name : mux16to1.ngr Top Level Output File Name : mux16to1 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs

: 23

Cell Usage : # BELS : 14 # LUT4 : 12 # MUXF5 :2 # IO Buffers : 23 # IBUF : 21 # OBUF :2 Device utilization summary: --------------------------Selected Device : 3s100etq144-4 Number of Slices: 7 out of 960 0% Number of 4 input LUTs: 12 out of 1920 0% Number of IOs: 23 Number of bonded IOBs: 23 out of 108 21% Partition Resource Summary: No Partitions were found in this design. TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-andROUTE. Clock Information: No clock signals found in this design Asynchronous Control Signals Information: No asynchronous control signals found in this design Timing Summary: --------------Speed Grade: -4

Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block mux16to1, actual ratio is 0. Final Macro Processing ... Final Register Report

Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 9.264ns Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 76 / 2 ------------------------------------------------------------Delay: 9.264ns (Levels of Logic = 6) Source: s<1> (PAD) Destination: x (PAD) Data Path: s<1> to x Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 6 1.218 0.844 s_1_IBUF (s_1_IBUF)

LUT4:I0->O 1 0.704 0.000 x97_F (N18) MUXF5:I0->O 1 0.321 0.595 x97 (x97) LUT4:I0->O 2 0.704 0.482 x291_SW0 (N16) LUT4:I2->O 1 0.704 0.420 xbar1 (xbar_OBUF) OBUF:I->O 3.272 xbar_OBUF (xbar) ---------------------------------------Total 9.264ns (6.923ns logic, 2.341ns route) (74.7% logic, 25.3% route) Total REAL time to Xst completion: 6.00 secs Total CPU time to Xst completion: 5.83 secs > Total memory usage is 149752 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 2 ( 0 filtered) Number of infos : 1 ( 0 filtered)

SCHEMATIC DIAGRAMS:

OBSERVATION:This program concludes that The above multiplexer(16x1) consists of 4 data select lines, 16 data inputs and single output line . We have 4 data select lines so, we get 24=16 select bits, each of the 16 data-input lines can be selected. S(0),S(1),S(3) and S(4) are the 16 data select inputs that allow the data on the corresponding data input to pass through to the data output.

RESULT:Hence we developed and implemented multiplexer (16x1) by using FPGA and CPLD devices.