Sheet 1 of 9

MOS Long Tail Pair (Diffferential Amplifier) The basic differential amplifier schematic is shown in Figure 1. A voltage applied to Vin1 will cause a current to flow through R1, but as vcm is a virtual ground as if Vin1 goes up Vin2 will go down to balance the currents such that the current through RSINK remains the same.

VDD

+
R1 R2

VO1 I1 Vin1 Q1 Vgs1

IO + 2
Q2 vcm IO+2 RSINK

I2

VO2

Vin2

v + d 2

Vgs2

vd 2

VSS
Figure 1 Basic Differential amplifier (Long-Tailed Pair) with resistive loads.

Sheet 2 of 9

Differential mode gain Ad

= gm

vd 2 vd .R L 2

VO = gm

VO = diff mode gain Vd Ad = gmR L 2

Common mode gain Acm

Small signal current = =

vcm 2.R SINK

VO = .R L VO = vcm .R L 2.R SINK rearrange = VO vcm = RL 2.R SINK = Acm

As with the bipolar case we can double the gain be combining the two voltage outputs using an active load. Note cancel

Sheet 3 of 9

VDD Q4 Q3 +

gmR O 2

VO +

= 2

Q 1 Q2

Vin

Vin

IO

Rbias

Q5

Q6

VSS

Figure 2 Differential amplifier with current mirror load. The current mirror combines the amplified differential voltages to give one output at Vo. The gain of this amplifier will be the same as a single stage ie gm.(1/gm3)

Sheet 4 of 9

Voltage input

Vin1 Vin2 = (VGS1 VGS2 ) IO = ID1 + ID2 ID = (VGS VT ) Rearrange to get VGS =
2

ID + VT

I I VGS1 VGS2 = D1 + VT1 D2 + VT2 If VT1 = VT2 then VGS1 VGS2 = I ID1 D2 2 1 Wher e = KNW 2L

Output Voltage Ranges Referring to figure 3 shows the PMOS differential amplifier and the voltages around the circuit. Note we define VGD as VDS-VGS. Maximum Positive common mode voltage

VIC(MAX) = VDD - VSD5 VGS1 Io + VT1 and VDS5 = 21 2Io 5

Where

VGS3 =

= VDD -

2I0 I 0 VT1 2 1 5

Sheet 5 of 9

Minimum Negative common mode voltage

VIC(MIN) = VSS + VGS3 + VDS1 VGS1 With Q1 in saturation VDS1 = VGS1 - VT1 VIC(MIN) = VSS + VGS3 + (VGS1 - VT1 ) VGS1 = VSS + VGS3 - VT1 Io + VT3 2 3 Io + VT3 - VT1 2 3
VDD IO Q5 VDS5

VGS3 =

VIC(MIN) = VSS +

VGS1

Q1 VDS1 Q2 Vin2

Vin1

Q3

Q4

VGS3

VSS

Figure 3 Showing PMOS Differential amplifier and the voltages effecting the maximum and minimum output voltages.

Sheet 6 of 9

Design Example Design the currents and W/L ratios for the current-mirror load differential amplifier, to satisfy the following specifications:VDD = - VSS = 2.5V. Slew rate (SR) 10V/uS (CL = 5pF), f-3dB 100kHz (CL=5pF). Av = 100, -1.5V ICMR 2V, Pdiss 1mW. CMOS Spice parameters are :Parameter VT Kp Gamma Phi Lambda TOX NMOS 0.7 50x10-6 0.6 0.8 0.04 150x10-10 PMOS -0.7 110x10-6 0.6 0.8 0.05 150x10-10

SR(V/uS) =

I5 (uA) I5 SR * CL = 10 * 5 = 50uA CL (pF)

So the tail current needs to be > 50uA

However, The 3dB bandwidth is 100KHz so with a load capacitor of 5pF results in an output resistance of

Rout <

1 1 = Rout < 318K 2 * f.C 2 * 100x10 3 * 5 x10 12

2 rearrange to get I5 I5 ( N + P )

But also Rout =

2. 2. = = 70uA 3 Rout( N + P ) 318e (0.04 + 0.05 )

1mW = 200uA 2.5 + 2.5

Max Power = 1mW Max I5 <

So I5 must be in the range 70 to 200 uA, select say 100uA

Sheet 7 of 9

Maximum input common-mode voltage =

VIC(MAX) = VDD - VGS3 +VTN rearrange VGS3 = VDD - VIC(MAX) +VTN = 2.5 - 2 + 0.7 = 1.2V
ID = [V GS 3 - V T ]
2

Where

W O .C OX L = 2

and Kp = O .C OX

Vgs3 =

2 * ID 2.ID W3 + VT = 2 W L3 Kpp(Vgs3 - VT ) Kpp L

-6

2 * 50e W3 L3 = 50e -6 (1.2 - 0.7) 2

W4 8 also = ie dimensions of current mirror L4

Small signal gain given as 100.

Av =

gmd v 2 = out = ( N + P ) g ds2 + g ds3 v in

2

W.K P L.I 5 100e -6 100(0.04 + 0.05 ) = 2 110e -6

2

I A ( + P ) W Solve for = 5 V N L KP 2 ie W1 W = 2 = 18.4 L1 L2

= 18.4

Sheet 8 of 9

VDS5(SAT) = VIC(MIN) VSS VGS1 VDS5(SAT) = - 1.5 ( 2.5) VGS1 and 2.ID1 + VT = W Kp N L 2 * 50e -6 + 0.7 = 0.9222V 110e 6 [18.4]

Vgs1 =

VDS5(SAT) = - 1.5 ( 2.5) (0.9222) = 0.0778 V

W5 2I5 = = 2 L5 K pN .VDS5(SAT)

2 * 100e 6 = 17.33 110e 6 .(0.0778)2

The above data and circuit is now entered into ADS to simulate and confirm the calculations. There are DC and AC simulations and to provide a differential input voltage of 1V the two input sources are set to +0.5V and 0.5V (ie 1V pk-pk).

Sheet 9 of 9

MOSFET_PMOS MOSFET4 Model=MOSFETM2 Length=1 um Width=8 um Ad= As= Pd= Ps= Nrd= Nrs= Mult=2 Region= Temp= Mode=nonlinear MOSFET_NMOS MOSFET5 Model=MOSFETM1 Length=1 um Width=18.4 um Ad= As= Pd= Ps= Nrd= Nrs= Mult=2 Region= Temp= Mode=nonlinear

MOSFET_PMOS MOSFET3 Model=MOSFETM2 Length=1 um Width=8 um Ad= As= Pd= Ps= Nrd= Nrs= Mult=2 Region= Temp= Mode=nonlinear

I_Probe ID4

V_DC VDD Vdc=VDS

MOSFET_NMOS MOSFET2 Model=MOSFETM1 Length=1 um Width=18.4 um Ad= V_AC As= SRC2 Pd= Vdc=VGS Ps= Vac=0.5 V Nrd= Freq=freq Nrs= Mult=2 Region= Temp= Mode=nonlinear

C C1 C=5.0 pF V_AC SRC5 Vdc=VGS Vac=-0.5 V Freq=freq

I_Probe ID5

AC
AC AC1 Start=0 MHz Stop=5 MHz DC DC1

DC
V_DC SRC7 Vdc=0.922 V

Var Eqn

VAR VAR1 VGS=1.2 VDS=2.5

V_DC VDD1 Vdc=-VDS

MOSFET_NMOS MOSFET1 Model=MOSFETM1 Length=1 um Width=17.33 um Ad= As= Pd= Ps= Nrd= Nrs= Mult=2 Region= Temp= Mode=nonlinear

LEVEL1_Model MOSFETM2 Cgbo= NMOS=no Rsh= PMOS=yes Cj=1e-4 Vto=-0.7 Mj=0.5 Kp=50e-6 Cjsw=5e-10 Gamma=0.6 Mjsw=0.33 Phi=0.8 Lambda=0.05 Js= Tox=150e-10 Rd= Nsub= Rs= Nss= Cbd= Tpg= Cbs= Ld= Is= Uo= Pb=0.95 Nlev= Cgso=5e-10 Gdsnoi=1 Cgdo=5e-10

Kf= Af= Fc= Rg= Rds= Tnom= N= Tt= Ffe= Imax= AllParams=

LEVEL1_Model MOSFETM1 Cgbo= NMOS=yes Rsh= PMOS=no Cj=1e-4 Vto=0.7 Mj=0.5 Kp=110e-6 Cjsw=5e-10 Gamma=0.6 Mjsw=0.33 Phi=0.8 Lambda=0.04 Js= Tox=150e-10 Rd= Nsub= Rs= Nss= Cbd= Tpg= Cbs= Ld= Is= Uo= Pb=0.95 Nlev= Cgso=5e-10 Gdsnoi=1 Cgdo=5e-10

Kf= Af= Fc= Rg= Rds= Tnom= N= Tt= Ffe= Imax= AllParams=