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Published in IET Power Electronics Received on 6th May 2011 Revised on 30th August 2011 doi: 10.1049/iet-pel.2011.0178

ISSN 1755-4535

Topology for multilevel inverters to attain maximum number of levels from given DC sources
K.K. Gupta S. Jain
Department of Electrical Engineering, Maulana Azad National Institute of Technology, Bhopal, India E-mail: kk_mact@rediffmail.com

Abstract: This study introduces a new multilevel converter topology, which can synthesise all possible additive and subtractive combinations of input DC levels in the output voltage waveform with fewer power electronic switches. An appropriate modulation scheme has also been proposed for low switching frequency operation of the proposed topology. As compared with the classic multilevel topologies, the proposed topology results in reduction of the number of switches and conduction losses. The operation and performance of the proposed multilevel converter has been ascertained through simulations and veried experimentally for single-phase nine-level multilevel inverter. Moreover, a 15-level inverter with asymmetric source conguration has been also investigated for charge balance control using the proposed modulation scheme. The same has been veried experimentally for effective balanced power delivery.

Introduction

A multilevel inverter aims at synthesising a staircase waveform with the help of appropriately connected power switches and multiple input DC levels. Controlled switching of semiconductor switches plays a crucial role to achieve a multistep waveform with controllable amplitude, frequency and phase. Such an approach to DC AC conversion offers a number of advantages over conventional two-level inverters, such as: capability to operate at higher voltages using traditional semiconductors, reduced common mode voltages, reduced dv/dt stresses, staircase waveform with better harmonic prole, smaller lter requirements (if any), exibility to operate on low- and high switching frequencies and possibility of fault-tolerant operation [1 7]. As a result, multilevel inverters have been attracting lot of attention in high-power and high-voltage/medium-power applications. Although classical multilevel topologies such as neutral point clamped (NPC) converters [8], ying capacitors (FC) converters [9] and cascaded H-bridge (CHB) converters [10] have been commercialised, but device count becomes signicantly high when they are to be designed for increased number of voltage levels. This induces complexity in implementation and increased cost. Therefore new topologies are being proposed and reported to reduce the overall count of active and passive devices for multilevel power conversion [11 20]. However, reducing the number of devices involves one or more of following compromises: increased power rating of semiconductor devices, increased number of power sources, reduced number of redundant states and complex modulation and control schemes. In spite of these compromises, there remains a possibility of exploring topological structures

which can maximise the number of levels with given input DC sources. In this paper, a new multilevel inverter topology is proposed, which is capable of synthesising all possible additive and subtractive combinations of the input DC levels. Moreover, depending on the selection of conguration of input DC levels, each step in the output waveform so obtained is equal to the smallest input DC level. The proposed topology bears congurational and functional similarity to the CHB topology in two ways: rst, it needs multiple isolated input DC voltages; and secondly, it offers the possibility of combining the input DC voltage levels into all additive and subtractive values. An important advantage of the proposed topology over the CHB topology is in terms of conduction losses as discussed in Section 4. Subsequently, the topology can be explored for applications where CHB converters are effectively implemented such as: grid interfacing of renewable energy sources (e.g. photovoltaic) [21], static synchronous compensators (STATCOMs) [22, 23], as multilevel bidirectional power converter for a hybrid STATCOM integrated with energy storage systems (ESS) in distributed generation systems [24] and in medium voltage drives applications where a phase-shifting transformer with multiple secondary windings is often employed mainly for the reduction of line-current distortion, thus providing isolated DC sources [25]. Organisation of the paper is as follows. The proposed concept is explained in Section 2. This section also presents the generalised structure of the proposed topology. In Section 3, the working of the proposed topology is explained with the help of a nine-level inverter. This section also explains the proposed modulation scheme with

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low switching frequency. Simulation results are presented along with results of a laboratory prototype for a nine-level inverter based on the proposed topology. A brief comparison of the proposed topology and classical topologies is made in Section 4. In Section 5, the proposed topology is further investigated for an alternate asymmetric conguration and charge balance control. Conclusions are presented in Section 6.

Proposed topology for multilevel inverter

The proposed topology aims at synthesising all possible combinations that can be attained through additions and subtractions of input DC voltage levels as described below: 1. With single DC source: If a single DC source of voltage VDCi is present, the possible voltage levels that can be synthesised are: +VDC1 and 0. The resultant inverter can be a three-level or two-level inverter. Such a structure is shown in Fig. 1, which is a standard single-phase full-bridge inverter. 2. With two DC sources: If two DC sources with voltages VDC1 and VDC2 are present, the possible combinations are +VDC1 , +VDC2 , +(VDC1 VDC2 ), +(VDC1 + VDC2 ) and 0 Thus for two DC sources, there are total nine possible combinations and the resulting structure should produce nine levels. Such a structure is shown in Fig. 2. Fig. 3 demonstrates the possible switch combinations to obtain the desired levels. It can be noted that three switches conduct simultaneously for every level. 3. With three DC sources: If three DC sources with voltages Vdc1, Vdc2 and Vdc3 are available, the possible combinations are: +VDC1, +VDC2, +VDC3, +(VDC1 VDC2), + (VDC1 + VDC2), +(VDC1 VDC3), +(VDC1 + VDC3), + (VDC2 VDC3), +(VDC2 + VDC3), +(VDC1 + VDC2 2 VDC3), +(VDC1 2 VDC2 + VDC3), +(VDC1 2 VDC2 2 VDC3), +(VDC1 + VDC2 + VDC3) and 0. Thus, when three DC sources are present, there are 27 additive and subtractive combinations possible including a zero level. 4. With k number of DC sources: A generalised structure is shown in Fig. 4 [26] with k number of DC sources. If k number of DC sources with

Fig. 2 Proposed topology for nine-level output

voltages VDCp , where p 1 to k, are present then the expression for maximum number of possible levels is k! 2m + 1 m ! ( k m ) ! m= 1 (1) The above expression indicates the maximum possibility in synthesising the number of levels. However, the actual number of levels will depend on the source conguration. Various DC source congurations and corresponding number of levels are discussed below: 1. Unary conguration consists of DC sources of equal voltages, that is VDC1 = VDC2 = VDC3 = = VDCk = VDC (2)
k

Maximum number of levels =

Unary conguration is also called symmetric source conguration. Such a conguration results in (2k + 1) combinations of levels. 2. Binary conguration consists of DC sources with a geometric progression with a factor of 1/2, that is VDC(k )1 VDC1 VDC2 = = = =2 VDC2 VDC3 VDCk

(3)

Such a conguration results in (2(k+1) 2 1) combinations of levels. 3. trinary conguration consists of DC sources with a geometric progression with a factor of 1/3 i.e. VDC(k )1 VDC1 VDC2 = = = =3 VDC2 VDC3 VDCk
Fig. 1 A full-bridge single-phase inverter
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(4)

Such a conguration results in (3k) combinations of levels.

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Fig. 3 Working states for nine-level inverter

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Table 1
State Switching states for nine-level output Switch states (1 ON, 0 OFF) S1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDC1 VDC1 VDC2 VDC2 VDC1 VDC2 VDC1 + VDC2 0 0 0 0 2 VDC1 2 VDC1 2 VDC2 2 VDC2 VDC2 VDC1 2 VDC1 VDC2 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 S2 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 S3 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 S4 0 1 0 0 1 0 0 1 1 0 1 0 1 1 0 1 S1 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 S2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 S3 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 S4 1 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 output voltage level

Fig. 4 Generalised structure of the proposed topology

It can also be mentioned here that in the proposed converter with k number of DC sources, the total number of switching states is determined as Number of switching states = 22k (5)

Operating principle

In this section, the working principle of the proposed structure is explained with the help of a nine-level inverter for singlephase operation. An appropriate modulation scheme is also presented. The working of proposed structure is shown with the help of simulation and veried experimentally. 3.1 Switching states to achieve required voltage levels A nine-level inverter with two DC sources VDC1 and VDC2 is shown in Fig. 2. Source conguration (unary, binary or trinary) will decide the actual number of levels in the output waveform. To obtain any desired voltage level, three switches need to be ON simultaneously as observed from Fig. 3. There are four pairs of switches. Switch pairs (S1 , S1 ) and (S4 , S 4 ) operate complimentarily. Switch pairs (S2 , ) and (S3 , S 3 ) are not complimentary in the strict sense of S2 the term but they operate in a way that the two members of a pair cannot be ON simultaneously though they can remain OFF simultaneously. Thus, three switches (to remain ON) can be chosen from four possibilities in 4C3 ( 4) ways and each switch has two possibilities (either ON or OFF). Thus, total number of states possible for the topology is 24 16. All the 16 states are shown in Fig. 3 along with the corresponding voltage output level. It can be seen that in this single-phase conguration, the AC load is fed by nine levels +VDC1 , + VDC2 , +(VDC1 VDC2), +(VDC1 + VDC2) and 0. In state 1, the switch S4 conducts along with S1 and S3 so that the potential difference across the load is VDC1. Similarly, an output of (VDC1 VDC2) is obtained when S1 , S 3 and S4 are ON. Various redundant states can also be noted. Voltage levels + VDC1 and +VDC2 have two redundant states each which are (1, 2), (3, 4), (11, 12) and (13, 14), respectively. Zero level has four redundant states viz. 7, 8, 9 and 10. All the possible states, voltage levels and switch positions are summarised in Table 1. It is evident that asymmetry in source conguration decreases the number of redundant states. For example, if VDC1 VDC2 VDC , then with reference to Table 1, the output levels +VDC and 0 would have increased number of redundant states. However, irrespective of source conguration, the level +(VDC1 + VDC2) would have just
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one working state and no redundant state. This aspect limits the prospect of programming a fault-tolerant operation scheme with all possible output voltage levels. Faulttolerant operation pertains to the ability of a converter to recongure itself so as to synthesise a given voltage level in case of power device failure(s) [27, 28] and therefore redundant states available in a topology determine the possibility of fault-tolerant operation. 3.2 Output voltage expressions

Corresponding to a switch Sj , let Tj be a switching function, where j {1, 2, 3, 4}, dened as Tj = 1, if Sj is ON 0, if Sj is OFF With reference to Fig. 2, following expressions can be written Vaa1 = (1 T1 ) VDC1 Va1a2 = (1 T2 ) [ T2 (VDC2 ) + T3 (VDC1 )
+ T3 (VDC1 VDC2 )]

(6)

(7)

Va2b = (1 T4 )VDC2 And Vab = Vaa1 + Va1a2 + Va2b 3.3 Modulation scheme (8)

High switching frequency modulation methods like multicarrier pulsewidth modulation (PWM) and space vector modulation techniques have been employed for multilevel inverter modulation control [29 31]. Also, methods such as active harmonic elimination [32], selective harmonic elimination (SHE) [32 34] and fundamental frequency method [33] are considered as low switching frequency methods. Any one of these methods, with suitable adaptation, can be used for the control of proposed structure. In this study, the control is demonstrated through
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low switching frequency multicarrier PWM scheme [35, 36]. In a multicarrier PWM scheme, carrier signals are compared with the reference signal and the pulses so obtained are used for switching of devices corresponding to the respective voltage levels [35]. The overall modulation scheme and corresponding waveforms are shown in Figs. 5 and 6 respectively. Eight triangular waveforms of 100 Hz frequency each are used as carriers. A sinusoidal waveform of 50 Hz frequency is the reference signal. Carrier signals above the time-axis are designated as Cp , {p 1, 2, 3, 4} and those below the timeaxis are designated as Cq , {q 5, 6, 7, 8}. In this scheme, if the reference is greater than carrier Cp , the comparator gives 1 otherwise 0. If the reference is greater than carrier Cq , the comparator gives 0, otherwise 21. However, in the proposed structure, various switches do not operate independent of each other. Therefore the signals obtained from the comparison of the carriers and reference cannot be fed directly to the switches. Therefore the signals so obtained are aggregated so as to synthesise an aggregated signal As. The aggregated signal As has same number of levels as desired in the output waveform. The switching signals are derived from this aggregated signal by comparison of the signal with desired level and the output is fed to the switches corresponding to the level using the lookup table, given in Table 2. 3.4 Simulation study Two DC sources with VDC1 36 V and VDC2 12 V are used to obtain a trinary arrangement. The load is considered to be RL load (R 2 V, L 5 mH). The inverter is operated in open loop mode. The load voltage and current waveforms and their corresponding harmonic spectrum are shown in Fig. 7. It is observed that the nine-level voltage waveform has equal steps of 12 V each and a total harmonic distortion (THD) of 11.41%. The harmonic prole of the load voltage can be further improved by using appropriate switching angles [32, 33]. The load current reects inductive behaviour and the waveform is in close imitation of sinusoidal shape with THD below 5% limit. 3.5 Experimental results

To examine the performance of the proposed multilevel inverter, a simulation model of single-phase nine-level inverter is developed in MATLAB/Simulink environment.

To validate the proposed topology, a prototype of singlephase nine-level inverter has been developed in the laboratory. MOSFETs (IRF460) powered with suitable gate drivers are used as switching devices. Two batteries with voltages VDC1 36 V and VDC 12 V are used as DC sources. dSPACE DS1103 real-time controller is used to generate the switching pulses. A schematic diagram and the experimental set-up of the laboratory prototype are shown in Figs. 8 and 9, respectively. A 0.5 hp single-phase induction motor is used as an AC load. The output voltage and current waveforms are shown in Fig. 10. Their respective frequency spectra are shown in Fig. 11. The voltage waveform and its THD are in close agreement with the respective simulations results. The load voltage is a stepped waveform of 50 Hz frequency with equal-sized steps of 12 V. The transient response is shown in Fig. 12 for a change in load. The change in load is

Fig. 5 Proposed modulation scheme for nine-level inverter

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Fig. 6 Waveforms pertaining to the proposed modulation scheme

brought about by adding a resistance in parallel with the induction motor and thereby increasing the load current of the inverter. It is seen that the change in load current does not affect the output voltage waveform.
Table 2
Look-up table for modulation scheme Corresponding voltage output level VDC1 + VDC2 VDC1 VDC1 VDC2 VDC2 0 2 VDC2 VDC2 VDC1 2 VDC1 2 VDC1 VDC2 Switch states (1 ON, 0 OFF) S1 S2 S3 S4 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 S1 0 0 0 0 1 1 1 1 1 S2 0 0 0 0 0 0 0 0 1 S3 0 1 1 0 1 1 0 0 0 S4 1 1 0 1 1 0 1 0 0

4 Comparison of proposed topology with classic multilevel topologies

NPC, FC and CHB are considered to be classic topologies for multilevel converters. In this section, a comparative study of the proposed topology is made with these. 4.1 Comparison with neutral point diode clamped and ying capacitor topologies NPC topology is characterised by the used of clamping diodes apart from power switches and present an additional drawback. As for the ying capacitor topology, the zero voltage level is produced using the difference between the voltages of ying capacitor and that of one of DC link capacitor. The proposed topology is compared with NPC and FC topologies for nine-level output in terms of requirement of various active and passive components as shown in Table 3. It is seen that the device count is signicantly reduced for the proposed topology.
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Level of aggregated signal As 4 3 2 1 0 21 22 23 24

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Fig. 7 Simulation results for a nine-level single-phase inverter based on proposed topology
a b c d Single-phase nine-level voltage output Harmonic spectrum of nine-level voltage output Load current waveform for nine-level voltage Harmonic spectrum for load current

4.2

Comparison with cascaded H bridge topology

Fig. 8 Schematic of the laboratory prototype of nine-level inverter

(CHB topology has been used with symmetric (when all DC sources are equal) and asymmetric (when DC sources are unequal) congurations [3, 10, 14]. Asymmetric CHB topology is a very competitive topology in terms of device count. In fact for a nine-level output, a symmetric CHB and the proposed topology require eight-power switches each. An important difference however can be made out in terms of conduction losses. In asymmetric CHB, for a nine-level output, four switches need to conduct simultaneously to obtain any output level. In the proposed topology, however, only three switches need to conduct to obtain a given level. This difference becomes more signicant as the number of levels is increased. This trend is summarised in Table 4. Moreover, for asymmetric conguration of sources, semiconductor switches with different capabilities to block voltages are required. Assuming the case of an asymmetric

Fig. 9 Experimental set-up of the proposed inverter

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Fig. 10 Voltage and current waveforms of laboratory prototype of single-phase nine-level inverter

topology with distinct sources VDC1 and VDC2 and VDC1 . VDC2 , the proposed structure would require four switches with minimum blocking voltage of VDC1 , two switches with minimum blocking voltage of VDC2 and two switches with minimum blocking voltage of (VDC1 + VDC2). A CHB topology, on the other hand, would require four switches with blocking capacity of VDC1 and four switches with minimum voltage blocking capability of VDC2 .

5 Charge balance control with asymmetric congurations

A multilevel inverter utilises multiple DC sources to synthesise a stepped waveform. The power drawn from the different voltage sources vary as a function of modulation index, output voltage levels and load power factor [37]. This may result in unsteady and, at times, unstable DC voltage levels. Hence the DC sources deliver unequal power. As a result, different DC sources would have different lifetimes. This section addresses the selection of an optimal asymmetric conguration of the proposed topology with the possibility of charge balance control. The DC sources balancing in asymmetric multilevel inverters depend on the duty cycle of each level that is synthesising the desired output waveforms [38]. When multiple input DC sources are used, it is desirable that these sources maintain a balanced state of charge [39] or, in other words, exhibit equal load sharing. Available literature indicates that though charge balancing is achieved with symmetrical converters [37 40], it is not possible for binary and trinary congurations [38]. Charge balance control can be achieved if there are two or more input DC sources with equal voltages [38, 40]. Table 5 summarises various source congurations and corresponding availability of redundant states, number of levels in the output voltage and possibility of charge balance control.
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Fig. 11 Frequency spectra of waveforms shown in Fig. 10

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Fig. 12 Waveforms depicting effect of change in load

Table 3 Comparison of proposed topology with diode clamped and ying capacitor topologies
Voltage levels Components Classical topologies Diode clamped 9 DC link capacitors clamping diodes clamping capacitors power switches 8 56 16 Flying capacitors 8 28 16 2 0 0 8 Proposed topology

In the light of above discussion, it can be argued that an optimal conguration would involve a trade-off between asymmetry and charge balancing considerations. Babaei and Hosseini [38] and Laali et al. [40] offer congurations with more number of redundant states as compared to a binary or trinary conguration along with possibility of charge balancing control. Although the proposed topology can be employed for all the congurations mentioned in Table 5, a source conguration
Table 4
Comparison with asymmetric CHB topology Number of switches conducting simultaneously to synthesise a level CHB topology (with trinary sources) 9 27 81 243 729 4 6 8 10 12 Proposed topology (with trinary sources) 3 4 5 6 7

Number of levels in the output voltage waveform

shown in Fig. 13 is employed to demonstrate the proposed modulation scheme for charge balance control. It has three input DC sources with voltages VDC1 36 V, VDC2 36 V and VDC3 12 V. Such a conguration is asymmetric and can synthesise 15 levels in the output waveform (284 V to + 84 V, in steps of 12 V each). Also, it has a total of 26 64 states, of which 53 states would be redundant (number of redundant states 22k 4k + 1, k number of sources 3). However, it can be emphasised that all voltage levels possibly cannot have redundant states [37]. The fundamentals of the proposed modulation scheme as explained in Section 3 are utilised to achieve charge balance control in the voltage sources VDC1 and VDC2 . As per discussed in Section 3, for a 15-level voltage waveform, the obtained aggregated signal As is shown in Fig. 14. Charge balance control can be achieved if sources VDC1 and VDC2 are utilised alternately in alternate cycles of the output waveform and thus balancing would be achieved in two cycles. Therefore the aggregated signal As is altered to A s in a manner that its one cycle has four sub-parts as shown in Fig. 15. The signal has 33 levels and they are utilised as per the look-up table given in Table 6. A 15-level asymmetric multilevel inverter based on Fig. 13 is simulated using MATLAB/Simulink and SimPowerSystems toolbox. A highly inductive RL load with R 2 ohm and L 8 mH is considered so as to observe the charge and discharge patterns of the DC sources. The output voltage waveform along with its harmonic spectrum is shown in Fig. 16. It is a 15-level stepped waveform in equal steps of 12 V. The current waveforms through the three DC sources are shown in Fig. 17. The current waveforms of two equal DC sources (VDC1 and VDC2) indicate an alternating pattern which is a result of swapping the two sources for voltage-level synthesis in alternate cycles. For example, the current waveform of source VDC1 in the duration t 0.94 to 0.96 s is same as that of source VDC2 in the duration t 0.96 to
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Table 5
S. No Various source congurations and charge balancing possibilities Source conguration Number of switches required Number of levels in the output voltage 2k + 1 2k+1 1 3k 4k 1 Number of redundant states Possibility of charge balancing

1 2 3 4

unary VDC(n21) VDCn VDCk binary VDC(n21)/VDCn VDC(k21)/VDCk 2 trinary VDC(n21)/VDCn VDC(k21)/VDCk 3 as proposed in [37] VDC1 VDC2 . . . VDCn . . . VDCk21 2VDC and VDCk VDC As proposed in [40] VDC1 VDC2 . . . VDCn . . . VDCk21 3VDC and VDCk VDC

4k 4k 4k 4k

22k 2k 1 22k 2k+1 + 1 22k 3k 22k 4k + 1

Yes No No Yes

4k

6k 3

22k 4k + 1

Yes

0.98 s and vice versa. Thus, the effective charge/discharge of these two sources is identical, thereby achieving charge balancing of the two sources.

Experimental execution of the 15-level inverter using dSPACE DS1103 and batteries as DC sources is done to validate the scheme. A single-phase induction motor of 0.5 HP is used as load. Output voltage waveform and the THD are shown in Figs. 18a and b, respectively. The output voltage waveform has equal steps of 12 V and a
Table 6 Look-up table for 15-level inverter with balanced charge
control Level of altered aggregated signal As 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Corresponding voltage output level [V ] (VDC1 VDC2 36 V, Vdc3 12 V) 0 VDC3 12 VDC1 VDC3 24 VDC1 36 VDC1 + VDC3 48 VDC1 + VDC2 VDC3 60 VDC1 + VDC2 72 VDC1 + VDC2 + VDC3 84 0 2 VDC3 212 VDC3 VDC1 2 24 2 VDC1 2 36 2 VDC1 VDC3 2 48 VDC3 VDC1 Vdc2 2 60 2 VDC1 VDC2 2 72 2 VDC1 vDC2 VDC3 2 84 0 VDC3 12 VDC2 VDC3 24 VDC2 36 VDC2 + VDC3 48 VDC1 + VDC2 VDC3 60 VDC1 + VDC2 72 VDC1 + VDC2 + Vdc3 84 0 VDC3 2 12 VDC3 VDC2 2 24 2 VDC2 2 36 2 VDC2 VDC3 2 48 VDC3 VDC1 VDC2 2 60 2 VDC1 VDC2 2 72 2 VDC1 VDC2 VDC3 2 84 Switches in ON state (other switches remain OFF) S1 , S2 , S4 , S6 S1 , S2 , S4 , S 6 S1 , S 3 , S 5 , S6 S1 , S 3 , S 5 , S 6 S1 , S3 , S4 , S 6 S1 , S3 , S 5 , S6 S1 , S3 , S 5 , S 6 S1 , S3 , S5 , S 6 S1 , S2 , S4 , S6 S 1 , S 3 , S 5 , S6 S 1 , S2 , S4 , S 6 S 1 , S2 , S4 , S6 S 1 , S 2 , S 5 , S6 S 1 , S 2 , S4 , S 6 S 1 , S 2 , S4 , S6 S 1 , S 2 , S 4 , S6 S1 , S2 , S4 , S6 S1 , S2 , S4 , S 6 S1 , S2 , S 5 , S6 S1 , S2 , S 5 , S 6 S1 , S2 , S5 , S 6 S1 , S3 , S 5 , S6 S1 , S3 , S 5 , S 6 S1 , S3 , S5 , S 6 S1 , S2 , S4 , S6 S 1 , S 3 , S 5 , S6 S 1 , S 3 , S4 , S 6 S 1 , S 3 , S4 , S6 S 1 , S 3 , S 4 , S6 S 1 , S 2 , S4 , S 6 S 1 , S 2 , S 4 , S 6 S 1 , S 2 , S 4 , S6

Fig. 13 15-level single-phase asymmetric inverter based on a source conguration proposed in [40]

Fig. 14 Aggregated signal As to obtain a 15-level output voltage

Fig. 15 Altered aggregated signal As for a 15-level output waveform

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Fig. 16 Simulations results for15-level inverter

a Output voltage b Harmonic spectrum

THD of 5%. Fig. 18a also shows the currents through voltage sources VDC1 and VDC2 . The current waveforms reect the effect of power balancing scheme with similar alternate patterns in the waveshapes. The power measurements from the three sources are summarised in Table 7. It is seen that

Fig. 17 Current waveforms through DC sources in 15-level inverter

a Current through the source VDC1 b Current through the DC source VDC2

Fig. 18 Output voltage waveform and the THD showing

a Waveforms for experimental set-up of 15-level inverter b Harmonic spectrum of 15-level voltage IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 435446 doi: 10.1049/iet-pel.2011.0178 445

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Table 7
Output power Power measurements for prototype of 15-level inverter Input power Power delivered Power delivered Power delivered by source VDC1 by source VDC2 by source VDC3 294.4 W 150.0 W 150.0 W 34.0 W 15 Pan, Z., Peng, F.Z., Stefanovic, V., Leuthen, M.: A diode-clamped multilevel converter with reduced number of clamping diodes. 19th Annual IEEE Applied Power Electronics Conf. and Exposition, APEC 04, 2004, vol. 2, pp. 820824 16 Chaturvedi, P.K., Jain, S., Agarwal, P.: A simple carrier based neutral point potential regulator for 3-level diode clamped inverter, Int. J. Power Electron., 2011, 3, (1), pp. 1 25 17 Ceglia, G., Guzman, V., Sanchez, C., Ibanez, F., Walter, J., Gimenez, M.I.: A new simplied multilevel inverter topology for DC to AC conversion, IEEE Trans. Power Electron., 2006, 21, (5), pp. 1311 1319 18 Babaei, E.: A cascade multilevel converter topology with reduced number of switches, IEEE Trans. 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both the sources VDC1 and VDC2 make equal contribution indicating an effective charge balancing control.

Conclusions

A novel multilevel topology is proposed in this paper with a view to reduce the device count and to obtain all possible additive and subtractive combinations of the input DC levels in the output voltage waveform. Multicarrier sine pulse width modulation technique as adapted for the proposed structured is explained. When compared to the classic topologies, the device count is signicantly reduced for a given number of levels in the output. The proposed concept is investigated through simulations and validated experimentally on a single-phase nine-level prototype. A charge balance control scheme has been investigated with a 15-level inverter based on the proposed structure with asymmetric source conguration. The scheme works satisfactorily and results validate the proposed concepts.

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