EEL201 Term paper on Clock Distribution and Skew, November 2012

Clock Distribution and Skew Optimization

Sambhav Gupta, 2011EE10484, Department of Electrical Engineering, IIT Delhi.
AbstractClock Distribution Networks and their importance in synchronizing the clock signals throughout the synchronous machines are described. Clock skew is explained briefly with conditions on clock periods to prevent hazards. A little discussion on both hazardous and beneficial skew is provided. Design, advantages and disadvantages of various Clock Distribution Networks is analysed. Methods on clock power and skew reduction are described, followed by a discussion on future aspects including the possibility of on chip optical clocks. Index TermsClock distribution, clock skew, synchronous circuits, interconnect analysis.

wasted providing clock signal to the registers whose output is not needed. Therefore, using combinational logic circuits in the distribution network, portions of the network can be turned off when not needed. This is called clock gating. B. Clock Based Performance A typical synchronous machine would comprise of registers, combinational gates, and a clock distribution network. Every logic gate fulfills a functional requirement of the system, but induces a delay in data propagation, affecting both the global and local timing considerations. A carefully designed distribution system would require to take into account all these timing constraints, and to make sure that all time violations caused by clock skew are minimized. The contents of the paper are organized in the following way. Section II looks at the clock skew and its invariant conditions, with a brief overview of its hazards and benefits. In Section III, different techniques of designing a clock distribution network are discussed. Section IV looks into some procedures and algorithms to reduce unwanted clock skew, and Section V gives an overview of power control in the Clock circuits. Future prospects are talked about in Section V, followed by summary and conclusions in Section VI.

I. INTRODUCTION A clock is an essential part of a synchronous machine, wherein it sets the datum time for data propagation. The clock distribution network is responsible for the clock signal(s) to reach every part of the circuit where it is required. Because of the utter importance of the clock signal to the working of the machine, a lot of research is done on this distribution. A clock skew is the time difference between clock arrivals in two (essentially sequentially adjacent) registers. where, , is the clock arrival time at register . Clock skew can be positive, negative, or zero, depending upon the relative clock arrival times. Interconnect length, temperature, capacitance, variations in transistor parameters, wire thickness, space to adjacent wires, and material and device imperfections are responsible for clock skew. [1] A. Considerations Both the fan-out (the number of gate inputs to which the output is connected) and the operational speed of a clock signal are very high, Also, the clock signals set the time reference for the machine, so they must be particularly clean and sharp[2]. Besides, with the decrease in the interconnect dimensions in accordance with the Moores law, the electrical resistance offered to the clock signals also increases. Lastly, the performance of the synchronous machine depends on the clock signal arrival so much that any delay or unpredictability can cause a lot of malfunctioning in the machine. Another important consideration is that a lot of power is
Manuscript received November 12, 2012. This work was supported in part by the Department of Electrical Engineering, IIT Delhi. Sambhav Gupta is a sophomore pursuing B.Tech in Electrical Engineering at IIT Delhi (email: sambhav.kgupta@gmail.com).

is the clock skew between registers

and

Figure 1: Data Path and Clock Timings [1]

II. CLOCK SKEW The minimum allowable clock period between two registers in a sequential data path is given by where is the time required by the data to leave the initial register once the clock arrives, is the time required to propagate through the logic and the interconnect, is the time required to successfully leave the latch within the final register of the data path.[1]

EEL201 Term paper on Clock Distribution and Skew, November 2012 A. Positive Clock Skew If the time of arrival of clock at the final register is more than the time of arrival of clock at the initial register ( ), it is called a positive skew, which is the time that must be added to such that a new clock signal, both of high and low frequency can be applied at the final register safely.

The tree network is connected to the source via the root, and to the registers at the leaves. A variant to this obtained by adding parallel paths are used at the leaf levels to reduce wire resistance, greatly minimizing clock skew. An even improved technique is to introduce buffers at every level instead of just one at the source. Though a little more area is required, this rectifies the signal strength against the interconnect impedances, and maintains a clean and sharp signal. Buffers require a high current output, since interconnect and fan-out may have high capacitance, ability to maintain shape and sharpness of the clock signal waveform, and a high output resistance to reduce the effect of interconnect impedance on the signal. B. Symmetric Trees One of the approaches to minimize clock skew is to maintain an identical clock signal path to every register. This is done by designing an H Tree (or an X Tree). An H Tree is constructed by repeatedly making H structures of wires, each originating from the previous one. The H Tree forms a compact space filling structure, and at the final end points are connected to registers. Again, buffers are used locally to enhance signal strength and sharpness. Adhering to the identical path, the only possible skew that can be induced is due to variations in buffers or transistor parameters. Hence, this provides a near zero clock skew. In spite of the advantage, other considerations such as increased interconnect impedance (both resistive and capacitive), increased clock delay (wire length is greatly increased), and the fact that clock skew affects only sequentially adjacent registers put forward important tradeoffs with zero clock skew.

Figure 2: Positive and Negative Skews [1]

B. Negative Clock Skew If the clock arrival at the transmitting register is prior to the clock arrival at the receiving register ( ), it is called a negative skew. Here, the clock skew needs to be less than , otherwise, the data in C1 overwrites the data in C2 before the clock signal comes. C. Beneficial Skew If the clock arrives at the transmitting register before the receiving register , there is a time shift from the nearby data paths to the critical local data paths [1]. A negative skew is the extra time that the output signal of C1 has to propagate through the combinational logic before reaching C2, resulting in the decrease of the clock period, which in turn gives the combination logic more time to complete its functional requirements before the data reaches the receiving register. This reduces the delay differences between local data paths.

III. CLOCK DISTRIBUTION DESIGN With the need to design a clock distribution network that would not only minimize skew, power dissipation and area requirements, but also maximize speed and performance, several algorithms and designs have been worked out. .In this section, we will talk about the commonly known buffered trees, symmetric trees, and also about a tree grid hybrid technique. A. Buffered Trees The most trivial network is a tree formed by adding buffers in the clock path a bottom up fashion, forming a tree structure.

Figure 3: Different types of Clock Distribution Networks Tree, H Tree, and a Mesh [2]

EEL201 Term paper on Clock Distribution and Skew, November 2012

C. Grids driven by more than one Trees Another technique of implementing a clock distribution network is by driving a clock grid by many trees, amalgamating benefits of both. Trees, when used without grids, need to be restructured whenever the register positions, clock pins, or capacitance on the load change. With the grid, a structure which can drive the clock to almost every position where it may be needed can be designed. A grid structure can also reduce the interconnect capacitance that results from a tree structure. This is typically achieved using H Trees powering a grid having uniformly spaced wires. An increasing need of buffers results as the clock frequency and wire interconnect impedance increases. This structure will yield satisfactory results only if all the constituting trees have similar delay and skew, otherwise different parts of the grid will have different switching times [3].

to capacitance C, square of supple voltage and clock frequency . Since reducing might change the machine performance and speed, controlling C and seems the only possible option. Techniques have been devised using buffers and pipeline registers, which reduce the power consumption by as good as 60% [1]. VI. FUTURE PROSPECTS As of today, research in the field focuses mainly on distribution network designs yielding high performance, and there is a lot of scope on beneficiary use of negative skew, localized clock skew for faster processing, and RC interconnect and buffer delay models for delay control. Focus can shift on interconnect impedance and skew reduction, using various methods such as mesh implementation in tree networks. Another significant topic of concern is insensitivity to environmental variations, since the nowadays, clocks speed used are of the order of Gigahertz, and even discrepancies of 10 picoseconds can affect high speed machines [1]. With the limitations on electrical clock due to space, power and skew considerations, there is an utter need for the clock signals to shift on to optical signals. This would effect a very low power consumption and small skew, conversion of optical signal to electrical signal or vice versa is an area of wide research opportunities [8].

IV. CLOCK SKEW REDUCTION In order to control the delay of each clock signal path and to minimize the skew between these paths, passive RC delay elements, or geometrically sized transistor widths are used to compensate for the variation of the delay of each clock signal path caused by different on-chip locations (i.e. different path dependent interconnect impedances) and capacitive loading of the clock destinations (i.e. the number and load of the clocked registers clock signal path) [2]. So as to drive highly resistive interconnect lines on low capacitance loads, and the ones with low resistance to drive on high capacitance loads, clock buffers are placed on the interconnect paths. Hence, interconnect impedance is greatly reduced by either using a central clock buffer, or by inserting buffers that load on high capacitance close to flip flops.

VII. SUMMARY AND CONCLUSION One of the very important reasons that asynchronous circuits have recently come into a lot of focus is the difficulty in design of clock distribution networks. But with a lot of improvements and scientific advancements in the recent times, synchronous circuits will still continue to be more commonly used for high speed systems. In practice, no system is synchronous in nature. It is only because of local timing and functional relationships, synchronous design properties can be approximated. REFERENCES
[1] [2] [3] [4] [5] [6] [7] [8] E, G, Friedman, Clock Distribution Design in VLSI circuits an Overview Rochester, New York: 14627 USA. E. G. Friedman, Clock Distribution Networks in Synchronous Digital Integrated Circuits Phillip J. Restle, A Clock Distribution Network for Microprocessors Sue B. Moont, Estimation and Removal of Clock Skew from Network Delay Measurements Ren-Song Tsay, An Exact Zero-Skew Clock Routing Algorithm JOHN P. FISHBURN, Clock Skew Optimization Phillip J. Restle, Designing the Best Clock Distribution Network Shiou Lin Sam, Variation Issues in On-Chip Optical Clock Distribution

Figure 4: Clock Distribution Network [2]

V. POWER CONTROL Due to a large number of flip flops and interconnects; the machine may develop very high capacitance, which, in addition to a large clock supply at high frequency, results in great demands for energy. This energy is directly proportional