Boolean Expression & Truth Table

table is a list of the possible combinations of input variable values and the corresponding output values ( 1 or 0).
Inputs Output X
A truth

Truth Table
How to design a logic gate for this truth table?

Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

Karnaugh Map
The Karnaugh map (K-map) provides a systematic method for simplifying Boolean expressions.
AK K-map map A K-map

is similar to a truth table. table

is a tool for simplifying combinational logic with multiple (ex. 3 or 4) variables. For 3 variables, 8 cells are required (23). 3-Variable Karnaugh Map ; The map shown is for three variables labeled A, B, and C. Each cell represents possible p product term. one p ; Each cell differs from an adjacent cell by only one variable. Gray code

Gray code
Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

Cells are usually labeled using 0s and 1s to represent the variable and its complement. Ones are read as the true variable Zeros are read as the complemented variable.
Alternatively,

cells can be labeled with the variable letters. This makes k it simple i l to t read, d but b t it takes t k more time ti preparing i the th map. Read the terms for the K-map.
C AB C C C

AB
AB

AB
AB

1
AB AB

AB AB

ABC

ABC + ABC.
AB AB

AB

ABC

Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

 Example of mapping a standard SOP expression.

Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

K-maps can simplify K i lif combinational bi i l logic l i by b grouping i cells ll and d eliminating variables that change.

Group the 1s on the map and read the minimum logic. C

C AB 00
01

0
1

1.

2.
1

11

3. 4.

Group th G the 1 1s i into t two t overlapping l i groups as indicated. Read each group by eliminating any variable i bl that h changes h across a boundary. The vertical group is read AC. The horizontal group is read AB. X = AC +AB

A
10

C changes across this boundary

Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

4-Variable 4 V i bl K Karnaugh hM Map ; The map shown is for three variables labeled A, B, C, and D. ; Each cell differs from an adjacent cell by only one variable. Gray code

B A

D
Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

Group the 1s on the map and read the minimum logic. C

CD 00 AB 00 1 01 11 1 1 1 1 1
4 4.

01

11

10 1

1.

2.

B A
10
3.

Group the 1s into two separate groups as indicated. Read each group by eliminating any variable that changes across a boundary. The upper (yellow) group is read as AD. The lower (green) group is read as AD. X = AD +AD

D X

Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

Karnaugh Map Simplification

an SOP expression i h has b been mapped, d a min. i SOP expression i i is obtained by grouping the 1s and determining the min. SOP expression from the map.
After Af

Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

Karnaugh Mapping from a Truth Table

Example of mapping directly from a truth table to a Karnaugh map.

Digital Logic Circuits 2008, Hongik Univ.

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Prof. Jongsun Kim

 Example of the use of dont care conditions to simplify an expression.

When some input variable combinations are not allowed, these unallowed states will not never occur. Treated as dont don t care care represented with X

Digital Logic Circuits 2008, Hongik Univ.

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Prof. Jongsun Kim

Karnaugh Map POS Simplification

For a POS expressions, F i 0 (representing 0s ( i the h standard d d sum terms) ) are placed on the K-map instead of 1s.

Digital Logic Circuits 2008, Hongik Univ.

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Prof. Jongsun Kim

Hardware Description Languages (HDLs)

A Hardware

Description Language (HDL) is a tool for implementing a logic design in a PLD. Two famous HDLs:
VHDL

(Very high speed integrated circuit HDL)

Verilog In VHDL, there are three approaches to describe logic: 1. Structural

Description is like a schematic (components and block diagrams). Description is equations, such as Boolean operations, and registers. Description is specifications over time (state machines, etc.).

2. Dataflow

3. Behavioral

Digital Logic Circuits 2008, Hongik Univ.

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Prof. Jongsun Kim

VHDL
The data flow method for VHDL uses Boolean-type statements. There are two-parts to a basic data flow program: Entity ; The entity portion describes the I/O. Architecture ; The architecture portion describes the logic.

Example) p )

Digital Logic Circuits 2008, Hongik Univ.

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Prof. Jongsun Kim

Verilog
Another

standard HDL is Verilog. In Verilog, the I/O and the logic is described in one unit called a module. Verilog uses specific symbols to stand for the Boolean logical operators operators.
NOT AND OR

~ & |

E ) 2-input Ex) 2i t AND gate t written itt for f Verilog: V il module And_Gate2 And Gate2 (X (X, A A, B); input A, B; output p X; ; Assign X = A & B; endmodule
15

Digital Logic Circuits 2008, Hongik Univ.

Prof. Jongsun Kim

Application: 7-segment Display

Digital Logic Circuits 2008, Hongik Univ.

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Prof. Jongsun Kim