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PACKAGE TYPES
DIP/SOIC
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
27C64
PLCC
A7 A12 VPP NU Vcc PGM NC
4 3 2 1 32 31 30
DESCRIPTION
The Microchip Technology Inc. 27C64 is a CMOS 64K bit (electrically) Programmable Read Only Memory. The device is organized as 8K words by 8 bits (8K bytes). Accessing individual bytes from an address transition or from power-up (chip enable pin going low) is accomplished in less than 120 ns. CMOS design and processing enables this part to be used in systems where reduced power consumption and high reliability are requirements. A complete family of packages is offered to provide the most exibility in applications. For surface mount applications, PLCC or SOIC packaging is available. Tape and reel packaging is also available for PLCC or SOIC packages.
A6 A5 A4 A3 A2 A1 A0 NC O0
5 6
29 28
7 8 9 10 11 12 13 14 15 16
27 26 25 24 23 22 21
A8 A9 A11 NC OE A10 CE O7 O6
17
18
19
O1 O2 VSS NU O3 O4 O5
20
27C64
DS11107L-page 1
27C64
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name A0-A12 CE OE PGM VPP O0 - O7 VCC VSS NC NU
VCC and input voltages w.r.t. VSS ....... -0.6V to + 7.25V VPP voltage w.r.t. VSS during programming .......................................... -0.6V to +14V Voltage on A9 w.r.t. VSS ...................... -0.6V to +13.5V Output voltage w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature .......................... -65C to +150C Ambient temp. with power applied ..... -65C to +125C
*Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specication is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
Parameter Input Voltages Input Leakage Output Voltages Output Leakage Input Capacitance Output Capacitance Power Supply Current, Active
Status Logic "1" Logic "0" Logic "1" Logic "0" TTL input TTL input
Symbol VIH VIL ILI VOH VOL ILO CIN COUT ICC1 ICC2
Units V V A V V A pF pF mA mA
Conditions
VIN = 0 to VCC IOH = -400 A IOL = 2.1 mA VOUT = 0V to VCC VIN = 0V; Tamb = 25C; f = 1 MHz VOUT = 0V; Tamb = 25C; f = 1 MHz VCC = 5.5V; VPP = VCC; f = 1 MHz; OE = CE = VIL; IOUT = 0 mA; VIL = -0.1 to 0.8V; VIH = 2.0 to VCC; Note 1
-10
10 6 12 20 25
Power Supply Current, Standby IPP Read Current VPP Read Voltage
TTL input TTL input CMOS input Read Mode Read Mode
VCC-0.7
mA mA A A V
Note 1: Typical active current increases .5 mA per MHz up to operating frequency for all temperature ranges.
DS11107L-page 2
27C64
TABLE 1-3: READ OPERATION AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature: 27C64-12 Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to O/P High Impedance Output Hold from Address CE or OE, whichever occurs rst Sym Min Max Min Max Min Max Min Max Min Max tACC tCE tOE tOFF tOH 0 0 120 120 65 50 0 0 150 150 70 50 0 0 170 170 70 50 0 0 200 200 75 55 0 0 250 250 100 60 ns ns ns ns ns CE = OE = VIL OE = VIL CE = VIL VIH = 2.4V and VIL = 0.45V; VOH = 2.0V VOL = 0.8V 1 TTL Load + 100 pF 10 ns Commercial: Tamb = 0C to +70C Industrial: Tamb = -40C to +85C 27C64-17 27C64-20 27C64-25 Units Conditions
27C64-15
FIGURE 1-1:
VIH Address VIL VIH CE VIL
READ WAVEFORMS
Address Valid
tCE(2)
VIH OE VIL VOH VOL t ACC t OE(2) High Z t OFF(1,3) t OH Valid Output High Z
Outputs O0 - O7
Note 1: tOFF is specied for OE or CE, whichever occurs rst. 2: OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 3: This parameter is sampled and is not 100% tested.
DS11107L-page 3
27C64
TABLE 1-4: PROGRAMMING DC CHARACTERISTICS
Ambient Temperature: Tamb = 25C 5C VCC = 6.5V 0.25V, VPP = VH = 13.0V 0.25V Parameter Input Voltages Input Leakage Output Voltages VCC Current, program & verify VPP Current, program A9 Product Identication Status Logic1 Logic0 Logic1 Logic0 Symbol VIH VIL ILI VOH VOL ICC2 IPP2 VH Min 2.0 -0.1 -10 2.4 11.5 Max. VCC+1 0.8 10 0.45 20 25 12.5 Units V V A V V mA mA V VIN = 0V to VCC IOH = -400 A IOL = 2.1 mA Note 1 Note 1 Conditions
Note 1: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
TABLE 1-5:
PROGRAMMING AC CHARACTERISTICS
AC Testing Waveform: VIH=2.4V and VIL=0.45V; VOH=2.0V; VOL=0.8V Ambient Temperature: Tamb=25C 5C VCC= 6.5V 0.25V, VPP = VH = 13.0V 0.25V Symbol tAS tDS tDH tAH tDF tVCS tPW tCES tOES tVPS tOE Min 2 2 2 0 0 2 95 2 2 2 Max 130 105 100 Units s s s s ns s s s s s ns 100 s typical Remarks
for Program, Program Verify and Program Inhibit Modes Parameter Address Set-Up Time Data Set-Up Time Data Hold Time Address Hold Time Float Delay (2) VCC Set-Up Time Program Pulse Width (1) CE Set-Up Time OE Set-Up Time VPP Set-Up Time Data Valid from OE
Note 1: For express algorithm, initial programming width tolerance is 100 s 5%. 2: This parameter is only sampled and not 100% tested. Output oat is dened as the point where data is no longer driven (see timing diagram).
DS11107L-page 4
27C64
FIGURE 1-2: PROGRAMMING WAVEFORMS (1)
Program VIH Address VIL VIH Data VIL t DS 13.0 V (3) VPP 5.0 V 6.5 V (3) VCC 5.0 V VIH CE VIL tCES VIH PGM VIL t PW VIH OE VIL Notes: (1) The input timing reference is 0.8 V for V IL and 2.0 V for V IH . (2) t DF and tOE are characteristics of the device but must be accommodated by the programmer. (3) Vcc = 6.5 V 0.25 V, V PP = VH = 13.0 V 0.25 V for Express algorithm. t OPW t OES t OE (2) tVCS tVPS tAS High Z Data In Stable t DH Data Out Valid t DF (2) t AH Address Stable Verify
TABLE 1-6:
Operation Mode Read Program Program Verify Program Inhibit Standby Output Disable Identity
X = Dont Care
MODES
CE VIL VIL VIL VIH VIH VIL VIL OE VIL VIH VIL X X VIH VIL PGM VIH VIL VIH X X VIH VIH VPP VCC VH VH VH VCC VCC VCC A9 X X X X X X VH O0 - O7 DOUT DIN DOUT High Z High Z High Z Identity Code
1.2
Read Mode
(See Timing Diagrams and AC Characteristics) Read Mode is accessed when a) b) the CE pin is low to power up (enable) the chip the OE pin is low to gate the data to the output pins
For Read operations, if the addresses are stable, the address access time (tACC) is equal to the delay from CE to output (tCE). Data is transferred to the output after a delay from the falling edge of OE (tOE).
DS11107L-page 5
27C64
1.3 Standby Mode 1.7 Verify
The standby mode is dened when the CE pin is high (VIH) and a program mode is not dened. When these conditions are met, the supply current will drop from 20 mA to 100 A. After the array has been programmed it must be veried to ensure all the bits have been correctly programmed. This mode is entered when all the following conditions are met: a) b) c) d) e) VCC is at the proper level, VPP is at the proper VH level, the CE line is low, the PGM line is high, and the OE line is low.
1.4
Output Enable
This feature eliminates bus contention in microprocessor-based systems in which multiple devices may drive the bus. The outputs go into a high impedance state when the following condition is true: The OE and PGM pins are both high.
1.8
Inhibit
1.5
Windowed products offer the capability to erase the memory array. The memory matrix is erased to the all 1s state when exposed to ultraviolet light. To ensure complete erasure, a dose of 15 watt-second/cm2 is required. This means that the device window must be placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensity of 12,000W/cm2 for approximately 20 minutes.
When programming multiple devices in parallel with different data, only CE or PGM need be under separate control to each device. By pulsing the CE or PGM line low on a particular device in conjunction with the PGM or CE line low, that device will be programmed; all other devices with CE or PGM held high will not be programmed with the data, although address and data will be available on their input pins (i.e., when a high level is present on CE or PGM); and the device is inhibited from programming.
1.9
Identity Mode
1.6
Programming Mode
The Express Algorithm has been developed to improve the programming throughput times in a production environment. Up to ten 100-microsecond pulses are applied until the byte is veried. No overprogramming is required. A owchart of the express algorithm is shown in Figure 1-3. Programming takes place when: a) b) c) d) e) VCC is brought to the proper voltage, VPP is brought to the proper VH level, the CE pin is low, the OE pin is high, and the PGM pin is low.
In this mode, specic data is output which identies the manufacturer as Microchip Technology Inc. and device type. This mode is entered when Pin A9 is taken to VH (11.5V to 12.5V). The CE and OE lines must be at VIL. A0 is used to access any of the two non-erasable bytes whose data appears on O0 through O7.
Pin Identity
Output 0 O O O O O O O 7 6 5 4 3 2 1 0 H e x
0 0 1 0 1 0 0 1 29 0 0 0 0 0 0 1 0 02
Since the erased state is 1 in the array, programming of 0 is required. The address to be programmed is set via pins A0-A12 and the data to be programmed is presented to pins O0-O7. When data and address are stable, OE is high, CE is low and a low-going pulse on the PGM line programs that location.
DS11107L-page 6
27C64
FIGURE 1-3: PROGRAMMING EXPRESS ALGORITHM
Conditions: Tamb = 25C 5C VCC = 6.5 0.25V VPP = 13.0 0.25V
Start
ADDR = First Location VCC = 6.5V VPP = 13.0V X=0 Program one 100 s pulse Increment X
Verify Byte
Pass
X = 10 ?
Last Address?
Yes
No Increment Address
Device Passed
Yes
No
Device Failed
DS11107L-page 7
27C64
NOTES:
DS11107L-page 8
27C64
NOTES:
DS11107L-page 9
27C64
NOTES:
DS11107L-page 10
27C64
27C64 Product Identication System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales ofces.
27C64
25
/P Package: L = Plastic Leaded Chip Carrier P = Plastic DIP (600 Mil) SO = Plastic SOIC (300 Mil) Blank = 0C to +70C I = 40C to +85C 12 15 17 20 25 27C64 = = = = = 120 ns 150 ns 170 ns 200 ns 250 ns 64K (8K x 8) CMOS EPROM
Device:
DS11107L-page 11
ASIA/PACIFIC
China Microchip Technology Unit 406 of Shanghai Golden Bridge Bldg. 2077 Yanan Road West, Hongiao District Shanghai, Peoples Republic of China Tel: 86 21 6275 5700 Fax: 011 86 21 6275 5060 Hong Kong Microchip Technology RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431 India Microchip Technology No. 6, Legacy, Convent Road Bangalore 560 025 India Tel: 91 80 526 3148 Fax: 91 80 559 9840 Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934 Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65 334 8870 Fax: 65 334 8850 Taiwan, R.O.C Microchip Technology 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139
EUROPE
United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Pas Taurus 1 Viale Colleoni 1 20041 Agrate Brianza Milan Italy Tel: 39 39 6899939 Fax: 39 39 689 9883
JAPAN
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122
9/3/96
DS11107L-page 12
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