Novel Field Programmable Transistor Array (FPTA) for Rapid Prototyping of Circuits

Guillaume Villeneuve, Michel Voyer, Danny Savard, Hung Tien Bui

Department of applied sciences Universit du Qubec Chicoutimi Montreal, Canada
Abstract In this paper, we present a novel field programmable transistor array (FPTA) for the purpose of rapid prototyping of integrated circuits. The proposed FPTA consists of 144 usable transistors whose connections and sizes can be configured to obtain a desired circuit topology. The connections are configured through memory cells that are programmed via a graphical user interface and a communications module. The FPTA has been designed and simulated in a 0.18m CMOS technology and simulation results for several prototyped circuits show that it works as expected.

transistor. Another point, which is not shown in the diagram, is that each transistor cell is connected an output buffer. While desirable in some applications, these buffers may also alter the characteristics to be measured.

I. INTRODUCTION Rapid prototyping has become an important step that helps reduce risks when designing and manufacturing circuits. In the digital world, field programmable gate arrays (FPGA) allow for quick and inexpensive prototyping of a system before fabrication. This step allows the designer to uncover possible compatibility issues between different components within the system. In the analog world, similar systems, known as field programmable analog arrays (FPAA), have also been proposed. FPAAs are useful when prototyping systems that require analog blocks such as transconductance amplifiers, resistors and capacitors. While these FPAAs may be beneficial in many circumstances, they have limited flexibility. For instance, FPAAs would not be usable when prototyping novel transistor-level circuits. To facilitate the prototyping of such circuits, one option is to move to a lower level of abstraction and allow for transistorlevel connections to be programmable. This can be done with a field programmable transistor array (FPTA). The FPTA concept is not a new one and has already been proposed in the past for applications in evolutionary systems [1-5]. The architecture of the previously proposed FPTA is shown in Fig. 1. The figure shows an array of programmable transistors in the middle of the design while interface circuits are on the outside. While the design is well thought out, there are several points to note concerning its use in rapid prototyping. The first drawback is the structure of its interconnections. Having to route the signal through transistor cells could be inefficient and also limit the use of that

Figure 1. Top level block diagram of the FPTA [4]

In this paper, we propose a novel FPTA and a design environment that is geared towards rapid prototyping of transistor-level circuits. We describe the architecture and the design choices in Section II. The resulting design and the simulation results are presented in Section III and the conclusions will be drawn in Section IV. II. PROPOSED ARCHITECTURE In the proposed FPTA, the transistors are grouped hierarchically in nine blocks each containing a 4x4 matrix of transistors. A top view of the design is shown in Fig. 2.

Figure 2. Top level block diagram of the FPTA

The authors would like to acknowledge financial support from NSERC and RESMiQ

The figure shows that a given 4x4 matrix of transistors has a number of I/Os on each side that are connected to buses in order to communicate with other transistor matrices. These buses are distributed both vertically and horizontally in order to improve connectivity. At the intersection between any horizontal and vertical buses, there is a switch box which allows for any line to be connected to virtually any other line. These switch boxes are configured by the FPTA memory which can be programmed via a graphic user interface. A scaled down version of such a switch box is shown in Fig. 3, where there are only two horizontal lines and two vertical lines. The figure shows that the switch box has 12 switches that control how the signals are routed. Depending on the configuration, signals can either pass horizontally or vertically and in addition, the box also allows horizontal signals to switch into vertical ones and vice versa. This can be a useful feature when designing certain circuit topologies.

PMOS or an NMOS. In addition, their sizes can be adjusted by connecting several binary weighted transistors in parallel. Each transistor block contains five binary weighted PMOS and five binary weighted NMOS (Fig. 5). The designer therefore has 32 different sizes to choose from using either of the two transistor types.

Figure 5. Transistor Cell

Figure 3. Switch Box

The architecture inside each transistor matrix is four columns and four rows of transistors. A small section of the matrix, with only two transistors, is shown in Fig. 4. Each pin of these transistors is connected to a switch box that selects the signal that is connected to it. These switches that are configured via the FPTA memory are shown as gray boxes in the figure. In addition, when vertical buses intersect horizontal ones, there is another switch box. These bigger switch boxes, whose internal connections are similar to the ones in Fig. 3, are shown as black boxes. Since there are many switches for a relatively small number of programmable transistors, the overhead space is very large. However, we believe that this type of overhead is necessary to provide support for efficient rapid prototyping.

Figure 4. Top level block diagram of the FPTA

To give maximum flexibility to the designer, each configurable transistor can have many different characteristics. First of all, each transistor can either be a

It should be noted that, while this transistor cell architecture allows much flexibility for increasing the W, it reduces the flexibility in increasing L. Even though it is possible to connect several transistor blocks in series, it is wasteful. In order to mitigate some of these drawbacks of short channels, the proposed FPTA does not use minimum length transistors. A. Configuration Memory In order to store the configuration of the transistors and the different switches, a memory module had to be designed. Each switch in the FPTA is assigned a distinct configuration bit which determines whether it conducts or not. There are several options available to create the configuration memory including DRAM, SRAM, latches and flip flops. To reduce the possibility of errors in this first iteration of the design, it was decided to use either latches or flip flops from a standard cell library. The latch was chosen to reduce the required space at the expense of a more complex control mechanism. A sample memory space is shown in Fig. 6. In this proposed implementation, the programming data is sent from the user interface on a computer to the FPTA using a simple RS-232 interface. The information is then serially sent into the shiftregister row at the bottom of the figure. Once this row is complete, the data are transferred to the next row. As the new configuration information flows into the FPTA, the data from the lower rows are propagated to the higher rows. This process continues until the FPTA is fully configured. The bottom shift-register uses flip flops whereas the storage elements used to configure the switches are implemented using latches. To transfer the data from one row to another, there is a separate shift register to the left of the figure that controls how the data are transferred. This shift register prevents data on one row from overwriting the data on another row.

number of switches in the interconnections, it is expected that the capacitance will be high and that therefore, delay and bandwidth performance would be poor. Several logic gates were designed and tested using the FPTA. To create these circuits, the configuration memory had to be altered. To facilitate the design process, these memory locations were configured manually by adjusting the voltage at the different nodes. After validating the operation of several logic gates, a simple current mirror was designed. It consists of an NMOS current mirror followed by a PMOS current mirror as shown in Fig. 8.

Figure 6. Configuration Memory

B. User Interface To facilitate the process of designing using an FPTA, a software user interface was designed. It features a graphic user interface (GUI) that allows the user to choose the transistor types, the transistor sizes and way they are connected together. A sample screenshot of the GUI is shown in Fig. 7. It shows a partial transistor matrix and the switches that can be used to make the connections.

Figure 8. Implemented Circuit for Simple Current Mirror

To evaluate the performance of the current mirror, DC simulations were run and results are shown in Fig. 9. In this figure, the solid line represents the current from the source, whereas the two other dashed lines are the results from the circuits. The line with the longer dashes is the result from the FPTA and the line with the shorter dashes is the result from a classic current mirror circuit implemented with the four transistors shown in Fig 8. The result shows that the current supplied by both mirrors is similar for relatively low values. The difference in current becomes more noticeable as the reference value increases. Results show that, while an FPTA current mirror tries to supply the necessary current, it fails to do so at higher current values. This seems to indicate that its output impedance is lower than for the non-FPTA current mirror.

Figure 7. GUI for the Design using an FPTA

The program also features an option to draw the circuit in a typical design environment and having it place and route the design automatically. Currently, the implemented algorithm only places the transistors sequentially but further work is in progress to allow the user to specify constraints. III. DESIGN AND SIMULATION In order to validate the proposed concept, a section of the FPTA was designed in 180nm CMOS technology and simulated using Cadences Spectre simulator. In this implementation, a single 4x4 matrix of transistors was created with six horizontal and six vertical bus lines. In each direction, there are also VDD and VSS lines to help free the buses. In the implemented design, there are 16 configurable transistor blocks which, along with switches and configuration memory, requires a total of roughly 15000 transistors. With that kind of overhead and with the large
Figure 9. Simulation Result for Simple Current Mirror

The other design that was implemented is a differential amplifier with a simple current mirror load. The input transistors were NMOS whereas the current mirror load was PMOS. The current source for the tail current was a simple current mirror.

IV. CONCLUSION In this paper, we presented a new design for FPTAs that is more suited for rapid prototyping of integrated circuits. Compared to a previous design, this FPTA has increased flexibility in terms of transistor configuration and interconnection. To validate the proposed design, it was used to create several test circuits including logic gates, a current mirror and a differential amplifier. While the performance of these FPTA-implemented designs is clearly inferior to the one of the directly implemented versions, the prototyping value of the FPTA has been validated. The physical design of the FPTA is currently under way and will thereafter be sent for fabrication. REFERENCES
[1] M. Trefzer, J. Langeheine, K. Meier, J. Schemmel, A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures, NASA/ESA Conference on Adaptive Hardware and Systems, 2006, pp. 32-39. J. Langeheine, J. Becker, S. Folling, K. Meier, J. Schemmel, Initial Studies of a new VLSI Field Programmable Transistor Array, International Conference on Evolvable systems: From Biology to Hardware, 2001. A. Stoica, R. Zebulum and D. Keymeulen, Mixtrinsic Evolution, International Conference on Evolvable systems: From Biology to Hardware, April 2000, pp 208-217. Jrg Langeheine, Intrinsic Hardware Evolution on the Transistor Level, Ph. D. Dissertation, University of Heidelberg, July 2005. M. A. Trefzer, Evolution of Transistor Circuits, Ph. D. Dissertation, University of Heidelberg, Dec. 2006.

Figure 10. Implemented Circuit for Differential Amplifier

The implemented circuit was simulated along with a reference design. The frequency responses are shown in Fig. 11. The solid line is the design that was implemented directly using the circuit of Fig. 10 whereas the dotted line is the design implemented using the FPTA. The higher low frequency gain could perhaps be explained by the smaller tail current obtained when using an FPTA implementation. The cutoff frequency of the FPTA implemented amplifier is more than two decades below that of the directly implemented one. This goes to show that for bandwidth critical implementation, the FPTA may not be a good choice. However, it other applications it may be acceptable as the goal of the FPTA is only to provide a fast way of prototyping novel circuit topologies.

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Figure 11. Simulation Result for Differential Amplifier