Configurable Command and Control Structure With Soft-Core Processor

CONFIGURABLE COMMAND AND CONTROL STRUCTURE WITH SOFT-CORE PROCESSOR

Dan Rotar "Vasile Alecsandri" Bacau University, Calea Marasesti 157, Bacau, Romania, 600115, drotar@ub.ro Abstract: The mechatronic systems in use today have some command and control systems, generally represented by microsystems, which are made with the microprocessors or the microcontrollers. Depending on the complexity of the mechatronic system and the control solution adopted, the CPUs used may have an 8, 16 or 32 bits data bus. Such an approach has the advantage of a specified hardware and the task of the designer is to connect the existing physical structures and to develop the command and the control software. The development of such physical structures represented by programmable logic arrays allows a new approach to such systems. Such a structure provided with a soft-core processor and the configuration ability as needed can bring certain advantages of the control system performance and optimization. The judicious choice of program components and the necessary physical structure increases the working speed and lowers the overall consumption. The article presents a solution to achieve the command and control system drives of the robot through its implementation with Xilinx programmable logic array fitted with a soft-core processor. The article explains how to program the physical structures necessary to command and control the robot motors and how to use the soft-core processor. The main advantage of this approach is the simple ability to change the physical structure depending on the engine used (stepper or DC motor) and using the strictly necessary physical components. At the same time, the designer can choose the required rapport between the software and the hardware components so as to ensure both the necessary operating speed and the simplicity to achieve the command and control program. Keywords: soft-core processor, programmable logic arrays, command and control system, drive robots, microprocessor, microcontroller.

1. Introduction The FPGA (Field Programmable Gate Array) allow the HDL (Hardware Description Language) programming of the digital physical structures. Programming the logical structures brings a few important advantages, such as: the possibility of the optimization of the physical structure according of the application, the computing speed is higher due to the parallel processing, the intake is low, etc. The fact that programming the physical structures with the help of the HDL languages must be also taken into consideration because it is generally harder than the programming of the software structures with high level programming languages. Sometimes, a certain physical structure that is not modified is needed, but the change of the corresponding commands is necessary. Because of this reason, in some cases, the use of soft-care processors in the structure built through the FPGA programming. A soft-core processor is the main component of a

computing system built in a single FPGA circuit. Such a component is a hardware structure programmed on a FPGA circuit and which can execute a program from a ROM memory (Read Only Memory) also done through HDL programming on the FPGA circuit. The user can add as they desire hardware modules such as ports, timers, communication modules, and other, depending on the obtained application so as to achieve an optimization of the hardware structure. Such a system built on a FPGA is programmed using two methods. First of all, a HDL is used to program the physical structure and then an assembly language for programming the central unit of the soft-core processor. This way, the biggest advantage is that along with the change of the program for the central unit, the physical structure associated can also be changed through a single operation. For an embedded system used for the command and control of a structure such as a mechatronic structure, improvements and changes always appear. Due to 13

The Romanian Review Precision Mechanics, Optics & Mechatronics, 2012, No. 41

Configurable Command and Control Structure With Soft-Core Processor this, such a completely programmable system leads to a series of supplementary facilities in programming and in exploitation [10]. If we count the continuous developing of the FPGA, the improvements made and the supplementary facilities added, we can say that such a solution is extremely attractive for the system designers. 2. The Soft-core used For the experiments presented in this paper, intellectual property (IP), open-source cores or free cores were used. Open-source cores are IP components that are freely available in the opensource community [6] [7]. The free version used is the PicoBlaze 8 bit processor offered by Xilinx, and the open-source was the AVR core, which is compatible with the 103 ATMEL ATmega 8 bit microcontroller offered by the OpenCores community [1]. Each of these solutions was implemented on a Xilinx Spartan-3 platform due to the fact that the chosen soft-core processors are optimized for this platform. In figure 1, the general structure of the AVR microprocessor is presented. Such a structure in the minimal configuration contains a soft-core with a program memory and a data memory. microcontroller is through an input/output port created by the user. This way, the transfer of the information with the created module is done through the input/output instructions of the microcontroller. It is obvious that the transfer speed of the data is lower, but in this situation, we do benefit from all the advantages of using an input/ output port: the high impedance state, interruptions, etc. Due to the fact that the AVR ATmega microcontroller [2] is well known and used in other applications, we benefit from lots of already created tools for its programming. These tools can be used with some modifications in the systems embedded on the FPGA [3]. For example, C or C++ applications can be developed with the help of the tools for the developing of the WinAVRTM [4] software based on the GNU GCC compilator and uploaded into the ROM memory of the microcontroller through the FPGA programming folder. The second soft-core used is the one offered by the Xilinx firm named PicoBlaze. In figure 2 the minimal structure of a Soc (System on Chip) done with this 8 bit microcontroller.

Figure 1. The AVR system There are two ways to add the user modules. One of them is to associate an address from the addressing space of the data memory, which is not used, to the newly made module. This way, the data transfer between the microcontroller and the new created module is done through operations of writing/reading of the memory making sure that an increased speed for the data transfer is available. The main inconvenient of this method consists of the fact that the high impedance state of the interface cannot be maintained through the program. The second possibility to add new modules to the 14

Figure 2. The PicoBlaze system The programming of the microcontroller is done in the assembly language, a special programming environment for this being available. The writing of the ROM memory is done through the FPGA configuration folder. In order to connect the supplementary modules, the input/output ports of the microcontroller are used. In this situation, the additional modules being added by the user and benefiting from all the advantages of the input/output operations with which the microcontroller is equipped.

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Configurable Command and Control Structure With Soft-Core Processor 3. Command and control solution for the drives The command and control solutions of the drives are essentially depend on the type of engine used [5] [11]. The drives used for robots were studied without making an exhaustive study about them. The main purpose of the tests was to determine which the advantages of the method are and to analyze the obtained results. To this purpose, this paper will presents the contributions of the author to the execution of the PWM generator and the function generator of a SoC done on a Xilinx Spartan 3E platform. 4. The PWM generator Figure 3 presents the main block of the hardware structure of the PWM generator. The PWM generators working is based on comparing the content of the U5 and U6 registers. Depending on the type of the wave form desired, symmetric or asymmetric, one or two comparators (the U7 and U8 circuits) are used.

Figure 3. The main block of the PWM generator In figure 4, the wave forms of the PWM generator are presented, when an asymmetric wave form is generated, which explains the way it works.

start cycle

end duty cycle Figure 4. The wave forms of the PWM generator.

end PWM cycle

For the PWM circuits with which the microcontrollers are equipped, the designer has the possibility to establish the tact frequency of the PWM period counter and the Duty Cycle value. Due to this, the PWM generator resolution is limited by the size of the counters (usually 10 or 12 bits) and by the command frequency. For the presented solution, the designer establishes through the soft-core program the frequency of the clock signal the value of the Duty Cycle duration, and through the hardware structure, the size of the

counters used. These parameters can be easily modifies through the change of some constants of the programs for the software and hardware structures. This new proposed solution allows the introduction of some new facilities for the PWM generator. This way, the value obtained by the U6 register (for establishing the Duty Cycle) can be dynamically changed according to a certain profile. In figure 5, such a situation is presented; the signal generated being used for the command of a LED (Light Emitting Diode) illuminating device. 15

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Configurable Command and Control Structure With Soft-Core Processor

Figure 5. The Duty Cycle modulation The command of the physical structure of the PWM by the soft-core is done through 3 ports or memory locations. Due to the fact that the size of the U5 and U6 counters is variable and it is chosen by the user, in order to allow the use of some common, configurable codes for the software, a multiplexor for the successive command of the structure is used. There are two 8 bit data ports (U1 and U2) so that 16 bit data can be written and an 8 bit command port (U4). The command port allows the configuration of the hardware structure and of the output signal. 5. The function generator A particular situation is represented by the case in which the synthesis of an output signal that can reproduce an analogue function is required. Usually, the generated system is a sinusoidal system used at the command of the invertors and then the technique used is called the PWM sinusoidal technique. The circuit used for the generation of the sinusoidal circuit is presented in figure 3. At present, the modulation of the output signal through the alteration of the duration of the impulse is done based on some tables places in a memory which are read sequentially. These tables contain the values of the duration of the impulse (of the Duty Cycle duration). In the case of the symmetrical signals, such as the sinusoidal signal, a great quantity of memory can be saved by using the symmetry of the signal. For example, for the sinusoidal signal is enough to memorize the values form the 0-/2 interval. The synthesis of the system is done, as it is shown in figure 6 with the help of some bidirectional counters, operated depending on the number of read values to cover four times in a period, the saved values being ascending and descending.

Figure 6. The signals of the function generator In Figure 6, the signal "clock" is the clock command with which the frequency of the generated signal is changed, "state" is a direction control signal for the counters generating the address for the memory table containing waveform signal, "table_index" is the generated address, the "wave_out" signal is the digital output signal converted to analog signal for easy visualization and the "positive_cycle" signal is the signal order to reverse the signal for the synthesis of alternating positive and negative. The main disadvantage of the method shown is that the values needed to generate the function once 16 stored in the memory cannot be modified. The solution proposed in this paper generated the necessary values for the command of the duration of the impulse with the help of a program of the softcore processor created in the programmable logical array. This allows the increase of the flexibility of the generator through the change of the characteristics of the function generated taking into consideration the process parameters. At the same time, the system even allows the change of the type of function generated while working. The output signal generation can be done in two

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Configurable Command and Control Structure With Soft-Core Processor ways: on one bit or more bits. Generating the output signal on a single bit is done by modulating the width of the signal (as shown in Figure 5). In this case, the output is likely to be required to install a filter for the correction of the output signal. In the second case, where through the output more bits are sent, it is no longer the case of the pulse width modulation but of the sending of the codes directly to a digital-analog converter. The designer determines the number of bits for synthesis according to the desired resolution. And in this case it may be necessary to mount the output of an interpolation circuit. The solution currently used for the realization of such a circuit involves the use of fixed hardware structures possibly supplemented by a programming structure to increase system flexibility. The new solution presented in this paper allows maximum flexibility by using programmable structures. The choice of the solutions presented is facilitated by the possibility of modifying the structure of both software and hardware simultaneously. Also, the drive control is achieved by modifying the parameters of the generator; the control possibilities are broader than those for the classical solutions due to flexibility of the proposed system. In case of the complex functions generation, the softcore module must perform complex calculations. At the same time the chosen control algorithms require some calculations from a certain complexity. Depending on when the data is needed: the table function values are created before the start of the command or a function values table is created during the command, the computing time can become critical. To meet these demands a mixed solution was adopted. Thus, the complex calculations are done using hardware, also connected through a port or a memory location. This custom hardware, also depending on the application implemented, can be treated as a mathematical processor. But in this situation the designer can choose a different solution. For example, a soft-core with the corresponding number of bit data bus, 16 or 32 bits can be adopted, for the corresponding increase in computing speed. In this situation the mathematical process can be waived and the problem can be solved exclusively by the software methods. As noted, the programming in a high-level programming language raises fewer problems than writing a program in HDL. The flexibility of the solution presented in this paper allows choosing the best solution to solve the problem. 6. Conclusions This paper presents a new method of establishing the PWM interface for the command for the robot drives. The presented solution represents a SoC done on a FPGA Xilinx Spartan 3E platform. Due to this approach, many advantages can be stated. These advantages are: o the designer can choose the balance between the software and the hardware components used in the project, mainly taking into consideration the performances which are wanted; o changing the structure and the characteristics of the PWM interface presented in this article can be made in a simple way through the change of some parameters from the HDL description or from the soft-core program; o the insurance of an increased flexibility, optimizations being easily made according to the actual conditions imposed; o increasing the drive control flexibility because the system introduced the possibility of programming the hardware structure and software component. Through the experiments made on a Digilent Basys2 platform, the fact that SoC is used for the robot drives allows the acquiring of superior performances in comparison to the classic systems. 7. References [1] http://opencores.org/project,avr_core [2] http://www.atmel.com/Images/doc0945.pdf [3] https://github.com/ [4] http://winavr.sourceforge.net/ [5] Fredrik Roos, Hans Johansson, Jan Wikander, Optimal selection of motor and gearhead in mechatronic applications, ELSEVIER, Mechatronics 16, pp. 6372, 2006 [6] Franjo Plavec, Soft-Core Processor Design, Thesis for the Degree of Master of Applied Science, Graduate Department of Electrical and Computer Engineering University of Toronto, 2004 [7] Jason G. Tong, Ian D. L. Anderson and Mohammed A. S. Khalid, Soft-Core Processors for Embedded System, The 18th International Conference on Microelectronics (ICM), pp. 170-173, 2006 [8] Xiao Wanang, Fang Zhi, Shi Yin, The Design and Implementation of the IEEE 802.11 Mac Based On SoftCore Processor and Rtos, Journal of Electronics (CHINA), Vol.24 No.2, pp. 232-237, March 2007 [9] M. Finc, A. Zemva, Profiling soft-core processor applications for hardware/software partitioning, Journal of Systems Architecture 51, pp. 315329, 2005 [10] Alexander Biedermann, Marc Stttinger, Lijing Chen and Sorin A. Huss, Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture, Lecture Notes in Computer Science, 2011, Volume 6578, Reconfigurable Computing: Architectures, Tools and Applications, pp. 385-396, 2011 [11] Markus Flckiger, Sensorless Position Control of Piezoelectric Ultrasonic Motors: a Mechatronic Design Approach, Thse no 4752 (2010) cole polytechnique fdrale de Lausanne prsente le 27 aot 2010 la Facult Sciences et Techniques de l'ingnieur laboratoire d'actionneurs intgrs programme doctoral en systmes de production et robotique, pp. 68-113, 2010 17

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