1-Wire Command Set for iButton 1.0 iButton with ROM 1.1 DS1904 1.1.

1 READ CLOCK [66h] The read clock command is used to read the device control byte and the contents of the real-time clock counter. After having received the most significant bit of the command code the device copies the actual contents of the real-time clock counter to the read/write buffer. Now the bus master reads data beginning with the device control byte followed by the least significant byte through the most significant byte of the real-time clock. After this the bus master may continue reading from the DS1904. The data received will be the same as in the first pass through the command flow. The read clock command can be ended at any point by issuing a Reset Pulse. 1.1.2 WRITE CLOCK [99h] The write clock command is used to set the real-time clock counter and to write the device control byte. After issuing the command, the bus master writes first the device control byte, which becomes immediately effective. After this the bus master sends the least significant byte through the most significant byte to be written to the real-time clock counter. The new time data is copied from the read/write buffer to the real-time clock counter and becomes effective as the bus master generates a reset pulse. If the oscillator is intentionally stopped, the real-time clock counter behaves as a four-byte non-volatile memory. 1.1.3 Read ROM [33h] This command allows the bus master to read the DS1904s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number read by the master will be invalid. 1.1.4 Match ROM [55h] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1904 on a multidrop bus. Only the DS1904 that exactly matches the 64-bit ROM sequence will respond to the following clock function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 1.1.5 SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify the ROM codes of the remaining devices. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 1.1.6 Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the clock functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-AND result). 1.1.7 Transaction Sequence The protocol for accessing the DS1904 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Clock Function Command

1.2 DS1990 1.2.1 Read ROM [33h] or [0Fh] This command allows the bus master to read the DS1990As 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1990A on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The DS1990A Read ROM function will occur with a command byte of either 33h or 0Fh in order to ensure compatibility with the DS1990, which will only respond to a 0Fh command word with its 64-bit ROM data. 1.2.2 Match ROM [55h] / Skip ROM [CCh] The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Match ROM and a Skip ROM command. (See the Book of DS19xx iButton Standards.) Since the DS1990A contains only the 64- bit ROM with no additional data fields, the Match ROM and Skip ROM are not applicable and will cause no further activity on the 1-Wire bus if executed. The DS1990A does not interfere with other 1Wire parts on a multidrop bus that do respond to a Match ROM or Skip ROM (example DS1990A and DS1994 on the same bus). 1.2.3 Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual example. 1.2.4 TRANSACTION SEQUENCE The sequence for accessing the DS1990A via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Read Data

2.0 iButton with EROM 2.1 DS1982 2.1.1 READ MEMORY [F0h] The Read Memory command is used to read data from the 1024-bit EPROM data field. The bus master follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. An 8bit CRC of the command byte and address bytes is computed by the DS1982 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and receives data from the DS1982 starting at the initial address and continuing until the end of the 1024-bit data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus master may issue eight additional read time slots and the DS1982 will respond with an 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the CRC is received by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 8-bit CRC available. Typically a 16-bit CRC would be stored with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-Wire environment.) If CRC values are imbedded within the data, a Reset Pulse may be issued at the end of memory space during a Read Memory command. 2.1.2 READ STATUS [AAh] The Read Status command is used to read data from the EPROM Status data field. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. An 8bit CRC of the command byte and address bytes is computed by the DS1982 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and receives data from the DS1982 starting at the supplied address and continuing until the end of the EPROM Status data field is reached. At that point the bus master will receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte through the final factory-programmed byte that contains the 00h value. This feature is provided since the EPROM Status information may change over time making it impossible to program the data once and include an accompanying CRC that will always be valid. Therefore, the Read Status command supplies an 8-bit CRC that is based on and always is consistent with the current data stored in the EPROM Status data field. After the 8-bit CRC is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is issued. The Read Status command sequence can be exited at any point by issuing a Reset Pulse. 2.1.3 READ DATA/GENERATE 8-BIT CRC [C3h] The Read Data/Generate 8-bit CRC command is used to read data from the 1024-bit EPROM memory field. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by the DS1982 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and receives data from the DS1982 starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send eight additional read time slots and receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. Once the 8-bit CRC has been received, data is again read from the 1024-bit EPROM data field starting at the next page. This sequence will continue until the final page and its accompanying CRC are read by the bus master. Thus each page of data can be considered to be 33 bytes long, the 32 bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at the end of each page. This type of read differs from the Read Memory command which simply reads each page until the end of address space is reached. The Read Memory command only generates an 8-bit CRC at the end of memory space that often might be ignored, since in many applications the user would store a 16-bit CRC with the data itself in each page of the 1024-bit EPROM data field at the time the page was

programmed. The Read Data/Generate 8-bit CRC command provides an alternate read capability for applications that are bit-oriented rather than page-oriented where the 1024-bit EPROM information may change over time within a page boundary, making it impossible to program the page once and include an accompanying CRC that will always be valid. Therefore, the Read Data/Generate 8-Bit CRC command concludes each page with the DS1982 generating and supplying an 8-bit CRC that is based on and therefore is always consistent with the current data stored in each page of the 1024-bit EPROM data field. After the 8-bit CRC of the last page is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is issued. The Read Data/Generate 8-Bit CRC command sequence can be exited at any point by issuing a Reset Pulse. 2.1.4 WRITE MEMORY [0Fh] The Write Memory command is used to program the 1024bit EPROM data field. The bus master will follow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of data (D7:D0). An 8-bit CRC of the command byte, address bytes, and data byte is computed by the DS1982 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. The highest starting address within the DS1982 is 007FH. If the bus master sends a starting address higher than this, the nine most significant address bits are set to 0 by the internal circuitry of the chip. This will result in a mismatch between the CRC calculated by the DS1982 and the CRC calculated by the bus master, indicating an error condition. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1- Wire bus for 480 s) is issued by the bus master. Prior to programming, the entire unprogrammed 1024-bit EPROM data field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the 1024bit EPROM will be programmed to a logical 0 after the programming pulse has been applied at that byte location. After the 480 s programming pulse is applied and the data line returns to a 5-volt level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS1982 responds with the data from the selected EPROM address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s in bit positions where the byte issued by the master contains 0s, a Reset Pulse should be issued and the current byte address should be programmed again. If the DS1982 EPROM data byte contains 0s in the same bit positions as the data byte, the programming was successful and the DS1982 will automatically increment its address counter to select the next byte in the 1024-bit EPROM data field. The least significant byte of the new 2-byte address will also be loaded into the 8-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS1982 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address, and the result is an 8-bit CRC of the new data byte and the LSB of the new address. After supplying the data byte, the bus master will read this 8-bit CRC from the DS1982 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Memory command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Memory flow chart will generate an 8-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the 2 address bytes, and finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS1982 automatically incrementing its address counter will generate an 8-bit CRC that is the result of loading (not shifting) the LSB of the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a program pulse to the DS1982) is made entirely by the bus master, since the DS1982 will not be able to determine if the 8-bit CRC calculated by the bus master agrees with the 8-bit CRC calculated by the DS1982. If an incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS1982. Also note that the DS1982 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the bus master; therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Memory command, incorrect programming could occur within the DS1982. The Write Memory command sequence can be exited at any point by issuing a Reset Pulse.

2.1.5 WRITE STATUS [55h] The Write Status command is used to program the EPROM Status data field. The bus master will follow the command byte with a 2-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of status data (D7:D0). An 8-bit CRC of the command byte, address bytes, and data byte is computed by the DS1982 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1-Wire bus for 480 s) is issued by the bus master. Prior to programming, the first 7 bytes of the EPROM Status data field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the EPROM Status data field will be programmed to a logical 0 after the programming pulse has been applied at that byte location. The 8th byte of the EPROM status byte data field is factoryprogrammed to contain 00h. After the 480 s programming pulse is applied and the data line returns to a 5-volt level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS1982 responds with the data from the selected EPROM Status address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM Status Byte address. If the EPROM Status Byte contains 1s in bit positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current byte address should be programmed again. If the DS1982 EPROM Status Byte contains 0s in the same bit positions as the data byte, the programming was successful and the DS1982 will automatically increment its address counter to select the next byte in the EPROM Status data field. The least significant byte of the new 2-byte address will also be loaded into the 8-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS1982 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address and the result is an 8-bit CRC of the new data byte and the LSB of the new address. After supplying the data byte, the bus master will read this 8-bit CRC from the DS1982 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Status flow chart will generate an 8-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the 2 address bytes, and finally the data byte. Subsequent passes through the Write Status flow chart due to the DS1982 automatically incrementing its address counter will generate an 8-bit CRC that is the result of loading (not shifting) the LSB of the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a program pulse to the DS1982) is made entirely by the bus master, since the DS1982 will not be able to determine if the 8-bit CRC calculated by the bus master agrees with the 8-bit CRC calculated by the DS1982. If an incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS1982. Also note that the DS1982 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the bus master, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Status command, incorrect programming could occur within the DS1982. The Write Status command sequence can be ended at any point by issuing a Reset Pulse. 2.1.6 Read ROM [33h] This command allows the bus master to read the DS1982s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS1982 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). 2.1.7 Match ROM [55h] The match ROM command, followed by a 64bit ROM sequence, allows the bus master to address a specific DS1982 on a multidrop bus. Only the DS1982 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the bus.

2.1.8 Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). 2.1.9 Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual example. 2.1.10 TRANSACTION SEQUENCE The sequence for accessing the DS1982 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Read/Write Memory/Status 2.2 DS1985 2.2.1 READ MEMORY [F0H] The Read Memory command is used to read data from the 16384-bits EPROM data field. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With every subsequent read data time slot the bus master receives data from the DS1985 starting at the initial address and continuing until the end of the 16384bits data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus master may issue sixteen additional read time slots and the DS1985 will respond with a 16-bit CRC of the command, address bytes and all data bytes read from the initial starting byte through the last byte of memory. This CRC is the result of clearing the CRC generator and then shifting in the command byte followed by the two address bytes and the data bytes beginning at the first addressed memory location and continuing through to the last byte of the EPROM data memory. After the CRC is received by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 16bit CRC available. Typically a 16-bit CRC would be stored with each page of data to ensure rapid, errorfree data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-Wire environment.) If CRC values are imbedded within the data, a Reset Pulse may be issued at the end of memory space during a Read Memory command. 2.2.2 READ STATUS [AAH] The Read Status command is used to read data from the EPROM Status data field. The bus master follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With every subsequent read data time slot the bus master receives data from the DS1985 starting at the supplied address and continuing until the end of an 8-byte page of the EPROM Status data field is reached. At that point the bus master will receive a 16-bit CRC of the command byte, address bytes and status data bytes. This CRC is computed by the DS1985 and read back by the bus master to check if the command word, starting address and data were received correctly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. Note that the initial pass through the Read Status flow chart will generate a 16-bit CRC value that is the result of clearing the CRC generator and then shifting in the command byte followed by the two address bytes, and finally the data bytes beginning at the first addressed memory location and continuing through to the last byte of the addressed EPROM Status data page. The last byte of a Status data page always has an ending address of xx7 or xxFH. Subsequent passes

through the Read Status flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the new data bytes starting at the first byte of the next page of the EPROM Status data field. This feature is provided since the EPROM Status information may change over time making it impossible to program the data once and include an accompanying CRC that will always be valid. Therefore, the Read Status command supplies a 16-bit CRC that is based on and always is consistent with the current data stored in the EPROM Status data field. After the 16-bit CRC of the last EPROM Status data page is read, the bus master will receive logical 1s from the DS1985 until a Reset Pulse is issued. The Read Status command sequence can be ended at any point by issuing a Reset Pulse. 2.2.3 EXTENDED READ MEMORY [A5H] The Extended Read Memory command supports page redirection when reading data from the 16384-bit EPROM data field. One major difference between the Extended Read Memory and the basic Read Memory command is that the bus master receives the Redirection Byte first before investing time in reading data from the addressed memory location. This allows the bus master to quickly decide whether to continue and access the data at the selected starting page or to terminate and restart the reading process at the redirected page address. A non-redirected page is identified by a Redirection Byte with a value of FFH (see description of EPROM Status Bytes). If the Redirection Byte is different than this, the master has to complement it to obtain the new page number. Multiplying the page number by 32 (20H) results in the new address the master has to send to the DS1985 to read the updated data replacing the old data. There is no logical limitation in the number of redirections of any page. The only limit is the number of available memory pages within the DS1985. In addition to page redirection, the Extended Read Memory command also supports bit-oriented applications where the user cannot store a 16-bit CRC with the data itself. With bit-oriented applications the EPROM information may change over time within a page boundary making it impossible to include an accompanying CRC that will always be valid. Therefore, the Extended Read Memory command concludes each page with the DS1985 generating and supplying a 16-bit CRC that is based on and therefore always consistent with the current data stored in each page of the 16384-bit EPROM data field. After having sent the command code of the Extended Read Memory command, the bus master follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. By sending eight read data time slots, the master receives the Redirection Byte associated with the page given by the starting address. With the next sixteen read data time slots, the bus master receives a 16-bit CRC of the command byte, address bytes and the Redirection Byte. This CRC is computed by the DS1985 and read back by the bus master to check if the command word, starting address and Redirection Byte were received correctly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and receives data from the DS1985 starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send 16 additional read time slots and receive a 16-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. With the next 24 read data time slots the master will receive the Redirection Byte of the next page followed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 16384-bit EPROM data field starting at the beginning of the new page. This sequence will continue until the final page and its accompanying CRC are read by the bus master. The Extended Read Memory command provides a 16-bit CRC at two locations within the transaction flow chart: 1) after the Redirection Byte and 2) at the end of each memory page. The CRC at the end of the memory page is always the result of clearing the CRC generator and shifting in the data bytes beginning at the first addressed memory location of the EPROM data page until the last byte of this page. The CRC received by the bus master directly following the Redirection Byte, is calculated in two different ways. With the initial pass through the Extended Read Memory flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memory flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the Redirection Byte only. 2.2.4 WRITE MEMORY [0FH] The Write Memory command is used to program the 16384bit EPROM data field. The bus master will follow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of data (D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the DS1985 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. The highest starting address within the DS1985 is 07FFH. If the bus master sends a starting address higher than this, the five most significant address bits are set to 0 by

the internal circuitry of the chip. This will result in a mismatch between the CRC calculated by the DS1985 and the CRC calculated by the bus master, indicating an error condition. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1-Wire bus for 480 ms) is issued by the bus master. Prior to programming, the entire unprogrammed 16384-bit EPROM data field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the 16384-bit EPROM will be programmed to a logical 0 after the programming pulse has been applied at that byte location. After the 480 ms programming pulse is applied and the data line returns to the idle level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS1985 responds with the data from the selected EPROM address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s in bit positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current byte address should be programmed again. If the DS1985 EPROM data byte contains 0s in the same bit positions as the data byte, the programming was successful and the DS1985 will automatically increment its address counter to select the next byte in the 16384-bit EPROM data field. The new 2byte address will also be loaded into the 16-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS1985 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS1985 with 16 read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Memory command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS1985 automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading (not shifting) the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a Program Pulse to the DS1985) is made entirely by the bus master, since the DS1985 will not be able to determine if the 16-bit CRC calculated by the bus master agrees with the 16-bit CRC calculated by the DS1985. If an incorrect CRC is ignored and a Program Pulse is applied by the bus master, incorrect programming could occur within the DS1985. Also note that the DS1985 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the bus master, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Memory command, incorrect programming could occur within the DS1985. The Write Memory command sequence can be ended at any point by issuing a Reset Pulse. To save time when writing more than one consecutive byte of the DS1985s data memory it is possible to omit reading the 16-bit CRC, which allows verification of data and address before the data is copied to the EPROM memory. This saves 16 time slots or 976 ms for every byte to be programmed. This speedprogramming mode is accessed with the command code F3H instead of 0FH. It follows basically the same flow chart as the Write Memory command, but skips sending the CRC immediately preceding the Program Pulse. This command should only be used if the electrical contact between bus master and the DS1985 is firm since a poor contact may result in corrupted data inside the EPROM memory. 2.2.5 WRITE STATUS [55H] The Write Status command is used to program the EPROM Status data field. The bus master will follow the command byte with a 2-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of status data (D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the DS1985 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1-Wire bus for 480 ms) is issued by the bus master. Prior to programming, the EPROM Status data field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the EPROM Status data field will be programmed to a logical 0 after the programming pulse has been applied at that byte location. After the 480ms programming pulse is applied and the data line returns to the idle level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS1985 responds with the data from the selected EPROM Status address sent least

significant bit first. This byte contains the logical AND of all bytes written to this EPROM Status Byte address. If the EPROM Status Byte contains 1s in bit positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current byte address should be programmed again. If the DS1985 EPROM Status byte contains 0s in the same bit positions as the data byte, the programming was successful and the DS1985 will automatically increment its address counter to select the next byte in the EPROM Status data field. The new two-byte address will also be loaded into the 16bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS1985 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the current address, and the result is a 16-bit CRC of the new data byte and the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS1985 with 16 read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Status flow chart will generate a 16-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the 2 address bytes, and finally the data byte. Subsequent passes through the Write Status flow chart due to the DS1985 automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading (not shifting) the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a Program Pulse to the DS1985) is made entirely by the bus master, since the DS1985 will not be able to determine if the 16-bit CRC calculated by the bus master agrees with the 16-bit CRC calculated by the DS1985. If an incorrect CRC is ignored and a Program Pulse is applied by the bus master, incorrect programming could occur within the DS1985. Also note that the DS1985 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the bus master, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Status command, incorrect programming could occur within the DS1985. The Write Status command sequence can be ended at any point by issuing a Reset Pulse. To save time when writing more than one consecutive byte of the DS1985s status memory it is possible to omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the EPROM memory. This saves 16 time slots or 976 ms for every byte to be programmed. This speedprogramming mode is accessed with the command code F5H instead of 55H. It follows basically the same flow chart as the Write Status command, but skips sending the CRC immediately preceding the Program Pulse. This command should only be used if the electrical contact between bus master and the DS1985 is firm since a poor contact may result in corrupted data inside the EPROM status memory. 2.2.6 Read ROM [33H] This command allows the bus master to read the DS1985s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS1985 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). 2.2.7 Match ROM [55H] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1985 on a multidrop bus. Only the DS1985 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the bus. 2.2.8 Skip ROM [CCH] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). 2.2.9 Search ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple three-step routine: read a bit, read the complement of the

bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual example. 2.2.10 Transaction Sequence The sequence for accessing the DS1985 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Read/Write Memory/Status 2.3 DS1986 2.3.1 READ MEMORY [F0H] The Read Memory command is used to read data from the 65536-bits EPROM data field. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With every subsequent read data time slot the bus master receives data from the DS1986 starting at the initial address and continuing until the end of the 65536bits data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus master may issue sixteen additional read time slots and the DS1986 will respond with a 16-bit CRC of the command, address bytes and all data bytes read from the initial starting byte through the last byte of memory. This CRC is the result of clearing the CRC generator and then shifting in the command byte followed by the two address bytes and the data bytes beginning at the first addressed memory location and continuing through to the last byte of the EPROM data memory. After the CRC is received by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 16bit CRC available. Typically a 16-bit CRC would be stored with each page of data to ensure rapid, errorfree data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-Wire environment.) If CRC values are imbedded within the data, a Reset Pulse may be issued at the end of memory space during a Read Memory command. 2.3.2 READ STATUS [AAH] The Read Status command is used to read data from the EPROM Status data field. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With every subsequent read data time slot the bus master receives data from the DS1986 starting at the supplied address and continuing until the end of an eightbyte page of the EPROM Status data field is reached. At that point the bus master will receive a 16-bit CRC of the command byte, address bytes and status data bytes. This CRC is computed by the DS1986 and read back by the bus master to check if the command word, starting address and data were received correctly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. Note that the initial pass through the Read Status flow chart will generate a 16-bit CRC value that is the result of clearing the CRC generator and then shifting in the command byte followed by the two address bytes, and finally the data bytes beginning at the first addressed memory location and continuing through to the last byte of the addressed EPROM Status data page. The last byte of a Status data page always has an ending address of xx7 or xxFH. Subsequent passes through the Read Status flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the new data bytes starting at the first byte of the next page of the EPROM Status data field. This feature is provided since the EPROM Status information may change over time making it impossible to program the data once and include an accompanying CRC that will always be valid. Therefore, the Read Status command supplies a 16-bit CRC that is based on and always is consistent with the current data stored in the EPROM Status data field. After the 16-bit CRC of the last EPROM Status data page is read, the bus master will receive logical 1s from the DS1986 until a Reset Pulse is issued. The Read Status command sequence can be ended at any point by issuing a Reset Pulse.

2.2.3 EXTENDED READ MEMORY [A5H] The Extended Read Memory command supports page redirection when reading data from the 65536-bit EPROM data field. One major difference between the Extended Read Memory and the basic Read Memory command is that the bus master receives the Redirection Byte first before investing time in reading data from the addressed memory location. This allows the bus master to quickly decide whether to continue and access the data at the selected starting page or to terminate and restart the reading process at the redirected page address. A non-redirected page is identified by a Redirection Byte with a value of FFH (see description of EPROM Status Bytes). If the Redirection Byte is different than this, the master has to complement it to obtain the new page number. Multiplying the page number by 32 (20H) results in the new address the master has to send to the DS1986 to read the updated data replacing the old data. There is no logical limitation in the number of redirections of any page. The only limit is the number of available memory pages within the DS1986. In addition to page redirection, the Extended Read Memory command also supports bit-oriented applications where the user cannot store a 16-bit CRC with the data itself. With bit-oriented applications the EPROM information may change over time within a page boundary making it impossible to include an accompanying CRC that will always be valid. Therefore, the Extended Read Memory command concludes each page with the DS1986 generating and supplying a 16-bit CRC that is based on and therefore always consistent with the current data stored in each page of the 65536-bit EPROM data field. After having sent the command code of the Extended Read Memory command, the bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. By sending eight read data time slots, the master receives the Redirection Byte associated with the page given by the starting address. With the next sixteen read data time slots, the bus master receives a 16-bit CRC of the command byte, address bytes and the Redirection Byte. This CRC is computed by the DS1986 and read back by the bus master to check if the command word, starting address and Redirection Byte were received correctly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and receives data from the DS1986 starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send sixteen additional read time slots and receive a 16- bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. With the next 24 read data time slots the master will receive the Redirection Byte of the next page followed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 65536-bit EPROM data field starting at the beginning of the new page. This sequence will continue until the final page and its accompanying CRC are read by the bus master. The Extended Read Memory command provides a 16-bit CRC at two locations within the transaction flow chart: 1) after the Redirection Byte and 2) at the end of each memory page. The CRC at the end of the memory page is always the result of clearing the CRC generator and shifting in the data bytes beginning at the first addressed memory location of the EPROM data page until the last byte of this page. With the initial pass through the Extended Read Memory flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memory flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the Redirection Byte only. fter the 16-bit CRC of the last page is read, the bus master will receive logical 1s from the DS1986 until a Reset Pulse is issued. The Extended Read Memory command sequence can be exited at any point by issuing a Reset Pulse. 2.2.4 WRITE MEMORY [0FH]/SPEED WRITE MEMORY [F3H] The Write Memory command is used to program the 65536-bit EPROM data field. The details of the functional flow chart are described in the section WRITING EPROM MEMORY. The data memory address range is 0000H to 1FFFH. If the bus master sends a starting address higher than this, the three most significant address bits are set to zeros by the internal circuitry of the chip. This will result in a mismatch between the CRC calculated by the DS1986 and the CRC calculated by the bus master, indicating an error condition. To save time when writing more than one consecutive byte of the DS1986s data memory it is possible to omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the EPROM memory. At regular speed this saves 16 time slots or 976 s for every byte to be programmed. This speed programming mode is accessed with the command code F3H instead of 0FH. It follows basically the same flow chart as the Write Memory command, but skips sending the CRC immediately preceding the program pulse. This command should only be used if the electrical contact between bus master and the DS1986 is firm since a poor contact may result in corrupted data inside the EPROM memory.

2.2.5 WRITE STATUS [55H]/ SPEED WRITE STATUS [F5H] The Write Status command is used to program the 2816-bit EPROM Status Memory field. The details of the functional flow chart are described in the section WRITING EPROM MEMORY. The Status Memory address range is 0000H to 01FFH. Attempts to write to the not implemented status memory locations will be ignored. If the bus master sends a starting address higher than 1FFFH, the three most significant address bits are set to zeros by the internal circuitry of the chip. This will result in a mismatch between the CRC calculated by the DS1986 and the CRC calculated by the bus master, indicating an error condition. To save time when writing more than one consecutive byte of the DS1986s status memory it is possible to omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the EPROM memory. At regular speed this saves 16 time slots or 976 s for every byte to be programmed. This speed-programming mode is accessed with the command code F5H instead of 55H. It follows basically the same flow chart as the Write Status command, but skips sending the CRC immediately preceding the program pulse. This command should only be used if the electrical contact between bus master and the DS1986 is firm since a poor contact may result in corrupted data inside the EPROM status memory. 2.2.6 Read ROM [33H] This command allows the bus master to read the DS1986s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS1986 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will usually result in a mismatch of the CRC. 2.2.8 Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1986 on a multidrop bus. Only the DS1986 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 2.2.9 Skip ROM [CCH] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-AND result). 2.2.10 Search ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual example. 2.2.11 Overdrive Skip ROM [3CH] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive Skip ROM sets the DS1986 in the Overdrive Mode (OD=1). All communication following this command has to occur at Overdrive Speed until a reset pulse of minimum 480 s duration resets all devices on the bus to regular speed (OD=0). When issued on a multidrop bus this command will set all Overdrivecapable devices into Overdrive mode. To subsequently address a specific Overdrive-capable device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will shorten the time for the search process. If more than one slave supporting Overdrive is present on the bus and the overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-AND result).

2.2.12 Overdrive Match ROM [69H] The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive Speed, allows the bus master to address a specific DS1986 on a multidrop bus and to simultaneously set it in Overdrive Mode. Only the DS1986 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive Skip or Match command will remain in Overdrive mode. All other slaves that do not match the 64-bit ROM sequence or do not support Overdrive will return to or remain at regular speed and wait for a reset pulse of minimum 480 s duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 2.2.13 Transaction Sequence The sequence for accessing the DS1986 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Read/Write Memory/Status 3.0 iButton with EEROM 3.1 DS1920 3.1.1 Read ROM [33h] This command allows the bus master to read the DS1920s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1920 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired AND result). 3.1.2 Match ROM [55h] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1920 on a multidrop bus. Only the DS1920 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 3.1.3 Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired AND result). The Skip ROM command is useful to address all DS1920s on the bus to do a temperature conversion. Since the DS1920 uses a special command set, other device types will not respond to these commands. 3.1.4 Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM Search, including an actual example. 3.1.5 Alarm Search [ECh] The flowchart of this command is identical to the Search ROM command; however, the DS1920 will respond to this command only if an alarm condition has been encountered at the last temperature measurement. An alarm condition is defined as a temperature higher than TH or lower than TL. The alarm condition remains set as long as the DS1920 is powered up or until another temperature

measurement reveals a non-alarming value. For alarming, the trigger values stored in EEPROM are taken into account. If an alarm condition exists and the TH or TL settings are changed, another temperature conversion should be done to validate any alarm conditions. 3.1.6 Write Scratchpad [4Eh] This command writes to the scratchpad of the DS1920, starting at address 2. The next 2 bytes written will be saved in scratchpad memory, at address locations 2 and 3. Writing may be terminated at any point by issuing a reset. However, if a reset occurs before both bytes have been completely sent, the contents of these bytes will be indeterminate. Bytes 2 and 3 can be read and written; all other bytes are read only. 3.1.7 Read Scratchpad [BEh] This command reads the complete scratchpad. After the last byte of the scratchpad is read, the bus master will receive an 8-bit CRC of all scratchpad bytes. If not all locations are to be read, the master may issue a reset to terminate reading at any time. 3.1.8 Copy Scratchpad [48h] This command copies from the scratchpad into the EEPROM of the DS1920, storing the temperature trigger bytes in nonvolatile memory. The bus master has to enable a strong pullup for at least 10 ms immediately after issuing this command. 3.1.9 Convert Temperature [44h] This command begins a temperature conversion. No further data is required. The bus master has to enable a strong pullup for 0.5 seconds immediately after issuing this command. 3.1.10 Recall [B8h] This command recalls the temperature trigger values stored in EEPROM to the scratchpad. This recall operation happens automatically upon power-up to the DS1920 as well, so valid data is available in the scratchpad as soon as the device has power applied. 3.1.11 TRANSACTION SEQUENCE The protocol for accessing the DS1920 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory/Control Function Command _ Transaction/Data 3.2 DS1961 3.2.1 Write Scratchpad [0Fh] The write scratchpad command applies to the data memory, the secret and the writeable addresses in the register page. If the bus master sends a target address higher than 90h, the command is not executed. After issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the beginning of the scratchpad. Note that the ending offset is always 111b regardless of the number of bytes that the master has transmitted. For this reason the master should always send eight bytes, especially if the data is to be loaded as a secret. If the master sends less than eight data bytes and does not read back the scratchpad for verification, parts of the new secret can be random data that is unknown to the master. Only full data bytes are accepted. If the last data byte is incomplete its content is ignored and the partial byte flag (PF) is set. When executing the write scratchpad command the CRC generator inside the DS1961S (see Figure 12) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0Fh) of the write scratchpad command, the target addresses (TA1 and TA2), and all the data bytes. Note that the CRC16 calculation is performed with the actual TA1 sent by the master even though the DS1961S sets TA1 bits T2..T0 to 000b for the actual write scratchpad command. The master can end the write scratchpad command at any time. However, if the scratchpad is filled to its capacity, the master can send 16 read-time slots and receives the CRC generated by the DS1961S. If the master continues reading after the CRC all data is be FFh. After receiving the target addresses (TA1 and TA2), the DS1961S clears the EN_LFS flag. If EPROM mode is active and a write scratchpad

is attempted within page 1 (0020h003Fh), the scratchpad is loaded with the logical AND of the scratchpad data sent by the master and the current content of the target memory location. If a write scratchpad is attempted to the register page (0088h008Fh), any bytes that are write-protected overwrite the corresponding scratchpad data byte sent by the master with the existing value. In all other cases, the data sent by the master is written to the scratchpad unaltered. 3.2.2 Read Scratchpad [AAh] The read scratchpad command allows verifying the target address and the integrity of the scratchpad data. After issuing the command code, the master begins reading. The first two bytes is the target address with T2 to T0 = 0. The next byte is the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the master has originally sent. This is of particular importance if the target address is the secret, the register page, page 1 (in EPROM mode), or if refresh was used to load the scratchpad. In these cases, the scratchpad can contain data other than that which was sent during either the write scratchpad or refresh scratchpad commands. The master should read through the end of the scratchpad after which it receives the inverted CRC that is computed with the data as sent by the DS1961S. If the master continues reading after the CRC all data is FFh. The scratchpad can be loaded using the write scratchpad or refresh scratchpad command. The data found in the scratchpad depends on the command used, the target address, and whether or not EPROM mode is active. See the descriptions of write scratchpad and refresh scratchpad for clarification. 3.2.3 Load First Secret [5Ah] The load first secret command has two modes of operation, which are controlled by the EN_LFS flag. With EN_LFS = 0, the command replaces the devices current secret with the contents of the scratchpad, provided that the secret is not write-protected. With EN_LFS = 1, the command allows to rewrite memory data (addresses 0000h to 007Fh), bypassing the SHA-1 computation that is required when doing the same through the copy scratchpad command. The EN_LFS flag is 0 unless it has been set to 1 by executing the refresh scratchpad command prior to load first secret. 3.2.3.1 Case EN_LFS = 0 Before the load first secret command can be used in this mode, the master must have written the new secret to the scratchpad using the starting address of the secret (0080h). After issuing the load first secret command, the master must provide a 3-byte authorization pattern (TA1, TA2, E/S, in that order), that should have been obtained by an immediately preceding read scratchpad command. This 3-byte pattern must exactly match the data contained in the three address registers (see Figure 6). If the pattern matches and the secret is not write-protected, the AA flag is set and the copy begins. All eight bytes of scratchpad contents are copied to the secrets memory location. 3.2.3.2 Case EN_LFS = 1 To use the load first secret command in this mode, the refresh scratchpad command must have been executed to load eight bytes of memory data (address range 0000h to 007Fh) into the scratchpad, which sets the EN_LFS flag to 1. After issuing the load first secret command, the master must provide a 3-byte authorization pattern (TA1, TA2, E/S, in that order), that can be obtained by an immediately preceding read scratchpad command without affecting the EN_LFS flag. This 3-byte pattern must exactly match the data contained in the three address registers (see Figure 6). If the pattern matches and the memory is not write-protected, the AA flag is set and the copy begins. All eight bytes of scratchpad contents are copied to the memory location. Regardless of the mode used, the duration of the copy operation is tPROG during which the voltage on the 1-Wire bus must not fall below 2.8V. The master should read at least one byte at the conclusion of the copy delay. Reading AAh indicates that the copy was successful, while reading FFh indicates that the copy was not successful. Instead of using load first secret with EN_LFS = 0, a new secret can alternatively be loaded with the copy scratchpad command. However, this approach requires the knowledge of the current secret and the computation of a 160-bit MAC. 3.2.4 Compute Next Secret [33h] Some applications may require a higher level of security than can be achieved by a single, directly written secret. For additional security the DS1961S can compute a new secret based on the current secret, the contents of a selected memory page, and a partial secret that consists of all data in the scratchpad. To install a computed secret the master issues the compute next secret command, which activates the 512-bit SHA-1 engine, provided that the secret is not write-protected. Table 1 shows how the various data components involved enter the SHA engine and how a portion of the SHA result is loaded into the secret's memory location. The SHA computation algorithm itself is explained later in this

document. The compute next secret command can be applied as often as desired to increase the level of security. The bus master does not need to know the devices current secret in order to successfully compute a new one and then overwrite the existing secret. After issuing the compute next secret command the master must provide a 2-byte target address to select the memory page that contributes 256 bits of the SHA input data. After receiving the target addresses (TA1 and TA2), the DS1961S clears the EN_LFS flag. The lower five bits of the target address TA1 are ignored because only the page number is relevant. If the target address as sent by the master is valid (i.e., in the range of 0000h and 007Fh), and the secret is not write-protected, the SHA engine starts. The master must wait for tCSHA during which the new secret is computed. Immediately following the SHA delay, the master must wait for tPROG during which the new secret is copied to the secret register. During the tCSHA and tPROG the voltage on the 1-Wire bus must not fall below 2.8V. The DS1961S fills the scratchpad with AAh if the copy was successful, but does not modify the scratchpad if the SHA engine did not start because of an incorrect address or because of write protection. The master should read at least one byte at the conclusion of the copy delay. Reading AAh indicates that the copy was successful. Reading FFh indicates that the copy was not successful because of an incorrect address or because of write protection. Since the content of the scratchpad is used as a partial secret, the master must fill the scratchpad with a known 8-byte data pattern using the write scratchpad command before it issues the compute next secret command. Otherwise the new secret depends on data that was unintentionally left in the scratchpad from previous commands. 3.2.5 Copy Scratchpad [55h] The data memory of the DS1961S can be read without any restrictions. Executing the copy scratchpad command to write new data to the memory or register page, however, requires the knowledge of the devices secret and the ability to perform an SHA-1 computation to generate the 160-bit MAC to start the data transfer from the scratchpad to the memory. The master can perform the MAC computation in software or use a DS1963S as a coprocessor. The coprocessor approach has the benefit that the secret remains hidden in the coprocessor iButton. The sequence in which the resulting MAC needs to be sent to the DS1961S is shown in Table 2. Tables 3A and 3B show how the various data components are entered into the SHA engine. The SHA computation algorithm is explained later in this document. After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern, which should have been obtained by an immediately preceding read scratchpad command. This 3-byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the authorization code matches and the target memory is not write-protected, the DS1961S starts its SHA engine to compute a 160-bit MAC that is based on the current secret, all of the scratchpad data, the first 28 bytes of the addressed memory page, and the first seven bytes of the identity register (the byte at address 0097h is not used; see Table 3A). The duration of this computation is tCSHA, during which the voltage on the 1-Wire line must not drop below 2.8V. Simultaneously the master computes a MAC from the same data and, after tCSHA is expired, sends it to the DS1961S as evidence that it is authorized to write to the EEPROM. Now the master waits for tPROG during which the voltage on the 1-Wire bus must not fall below 2.8V. If the MAC generated by the DS1961S matches the MAC that the master computed, the DS1961S sets its AA flag, and copy the entire scratchpad contents to the data EEPROM. The master should read at least one byte at the conclusion of the copy delay. Reading AAh indicates that the copy was successful. Reading 00h indicates that the copy was not successful because the computed MAC did not match the MAC sent by the master. Reading FFh indicates that the copy was not successful because of write protection or because of an incorrect authorization pattern. Special attention is required when copying data to the register page. In order to prevent unintentional locking of a special function register or user byte it is recommended to first read the register page and then write it with all intended modifications to the scratchpad. When copying data to the register page (or the secret using copy scratchpad), the input data for M1 to M7 of the SHA engine is the current secret (M1, M2), the current content of the register page (M3, M4), the full content of the identity register (M5, M6), and 4 bytes FFh (M7), as shown in Table 3B. As a consequence, when using a DS1963S as coprocessor to compute the MAC to transfer data from the scratchpad to the register page, the secret must be used as page data. This precludes the use of partial (computed) secrets if writing to the register page is required. For practical use of the DS1961S as a monetary token, partial secrets are more critical than being able to write-protect the secret or other areas of the device. 3.2.6 Read Authenticated Page [A5h] The read authenticated page command provides the master with the data of a full or partial memory page plus a MAC. The MAC allows the master to determine whether the secret stored in the DS1961S is valid within the application. The DS1961S computes the MAC from its secret, all the data of the selected memory page, the first seven bytes of the identity register and a 3-byte challenge, which the

master should write to the scratchpad prior to issuing the read authenticated page command. To do this, the master can use the write scratchpad command with any target address within the data memory. The relevant portions of the challenge are the 5th, 6th, and 7th bytes. Alternatively, the master can accept the data that happens to reside in the scratchpad from a previous command as a challenge. The 160-bit MAC is transmitted in the same way as with the copy scratchpad command, Table 2, but the data flows from the DS1961S to the master. The data input to the SHA engine as it applies to the read authenticated page command is shown in Table 4. After the master has issued the command code and specified the target addresses (TA1 and TA2), the DS1961S first clears the EN_LFS flag. If the target address is valid (< 0080h), the master receives the page data beginning at the target address through the end of the data page, one byte FFh and the inverted CRC of the command code, target address, transmitted page data and FFh byte. If the target address is invalid (_ 0080h), the master receives FFh bytes rather than page data. Immediately after the CRC is received, the master waits for tCSHA during which the voltage on the 1-Wire bus must not fall below 2.8V. During this time the SHA engine of the DS1961S computes the message authentication code over the secret, all 32 data bytes of the selected page, the devices registration number (without the CRC) and the 3-byte challenge. Now the master reads the 160-bit MAC, which is followed by an inverted CRC as a means to safeguard the data transfer. If the master continues reading after the CRC it receives AAh. 3.2.7 Refresh Scratchpad [A3h] Refresh scratchpad loads memory data to the scratchpad and sets the EN_LFS flag, which enables the use of the load first secret command to re-write the data that was just read from the memory, bypassing the MAC computation of copy scratchpad. The command flow chart of refresh scratchpad is very similar to write scratchpad. If the target address is between 0000h007Fh, there are two primary differences. 1) The data bytes that the master transmits following the target address are discarded; instead, the scratchpad is loaded with the unaltered memory data located at the target address, even if the memory page is in EPROM mode. 2) After the master has transmitted the eight dummy bytes, the EN_LFS flag is set to 1. The EN_LFS flag is cleared to 0 after receiving TA1 and TA2 during a write scratchpad, compute next secret, read authenticated page, refresh scratch, read memory, or by a power-on reset, because these commands can change the target address and/or the data in the scratchpad. When applied to addresses 0080h008Fh, the refresh scratchpad command behaves the same way as write scratchpad. This protects the secret from being exposed by a subsequent read scratchpad command. 3.2.8 Read Memory [F0h] The read memory command can be used to read all memory except for the secret. Attempting to read the secret results in FFh bytes instead of the actual secret. After the master has issued the command code and specified the target addresses (TA1 and TA2), the DS1961S first clears the EN_LFS flag. If the target address is valid, the master reads data beginning from the target address and can continue until address 0097h. If the master continues reading, the result is logic 1s. It is important to realize that the target address registers point to the last byte read. The ending offset/data status byte and the scratchpad are unaffected. The hardware of the DS1961S provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet typically stores a master-calculated 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (Refer to Application Note 114 for the recommended file structure, which is also referred to as TMEX Format.) 3.2.9 Read ROM [33h] This command allows the bus master to read the DS1961Ss 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number read by the master are invalid. 3.2.10 Match ROM [55h] The match ROM command, followed by a 64-bit registration number, allows the bus master to address a specific DS1961S on a multidrop bus. Only the DS1961S that exactly matches the 64-bit registration number responds to the following memory function command. All other slaves wait for a reset pulse. This command can be used with single or multiple devices on the bus.

3.2.11 Search ROM [F0h] When a system is initially brought up, the bus master may not know the number of devices on the 1Wire bus or their 64-bit registration numbers. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit numbers of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this 3-step routine on each bit of the registration number. After one complete pass, the bus master knows the 64-bit number of one device. Additional passes will identify the registration numbers of the remaining devices. Refer to Chapter 5 of The Book of DS19xx iButton Standards for a detailed discussion of a search ROM, including an actual example. 3.2.12 Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the memory and SHA functions without providing the 64-bit registration number. If more than one slave is present on the bus and, for example, a read command is issued following the skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). 3.2.13 Resume Command [A5h] In a typical application the DS1961S needs to be accessed several times to write a full 32-byte page. In a multidrop environment this means that the 64-bit registration number of a match ROM command has to be repeated for every access. To maximize the data throughput in a multidrop environment the resume command function was implemented. This function checks the status of the RC bit and, if it is set, directly transfers control to the memory and SHA functions, similar to a skip ROM command. The only way to set the RC bit is through successfully executing the match ROM, search ROM, or overdrive match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the resume command function. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the resume command function. 3.2.14 Overdrive Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory and SHA functions without providing the 64-bit registration number. Unlike the normal skip ROM command the overdrive skip ROM sets the DS1961S in the overdrive mode (OD = 1). All communication following this command code has to occur at overdrive speed until a reset pulse of minimum 480s duration resets all devices on the bus to regular speed (OD = 0). When issued on a multidrop bus this command sets all overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrivesupporting device, a reset pulse at overdrive speed has to be issued followed by a match ROM or search ROM command sequence. This speeds up the search process. If more than one slave supporting overdrive is present on the bus and the overdrive skip ROM command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). 3.2.15 Overdrive Match ROM [69h] The overdrive match ROM command, followed by a 64-bit registration number transmitted at overdrive speed, allows the bus master to address a specific DS1961S on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS1961S that exactly matches the 64-bit number responds to the subsequent memory or SHA function command. Slaves already in overdrive mode from a previous overdrive skip or a successful overdrive match command will remain in overdrive mode. All overdrivecapable slaves return to regular speed at the next reset pulse of minimum 480s duration. The overdrive match ROM command can be used with single or multiple devices on the bus. 3.2.16 TRANSACTION SEQUENCE The protocol for accessing the DS1961S through the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory or SHA Function Command _ Transaction/Data

3.3 DS1971 3.3.1 WRITE SCRATCHPAD [0Fh] After issuing the Write Scratchpad command, the master must first provide a 1-byte address, followed by the data to be written to the scratchpad for the data memory. The DS1971A will automatically increment the address after every byte it received. After having received a data byte for address 1Fh, the address counter will wrap around to 00h for the next byte and writing continues until the master sends a Reset Pulse. 3.3.2 READ SCRATCHPAD [AAh] This command is used to verify data previously written to the scratchpad before it is copied into the final storage EEPROM memory. After issuing the Read Scratchpad command, the master must provide the 1-byte starting address from where data is to be read. The DS1971A will automatically increment the address after every byte read by the master. After the data of address 1Fh has been read, the address counter will wrap around to 00h for the next byte and reading continues until the master sends a Reset Pulse. 3.3.3 COPY SCRATCHPAD [55h] After the data stored in the scratchpad has been verified the master may send the Copy Scratchpad command followed by a validation key of A5h to transfer data from the scratchpad to the EEPROM memory. This command will always copy the data of the entire scratchpad. Therefore, if one desires to change only a few bytes of the EEPROM data, the scratchpad should contain a copy of the latest EEPROM data before the Write Scratchpad and Copy Scratchpad commands are issued. After this command is issued, the data line must be held at logic high level for at least 10ms. 3.3.4 READ MEMORY [F0h] The Read Memory command is used to read a portion or all of the EEPROM data memory and to copy the entire data memory into the scratchpad to prepare for changing a few bytes. To copy data from the data memory to the scratchpad and to read it, the master must issue the read memory command followed by the 1-byte starting address from where data is to be read from the scratchpad. The DS1971 will automatically increment the address after every byte read by the master. After the data of address 1Fh has been read, the address counter will wrap around to 00h for the next byte and reading continues until the master sends a Reset Pulse. If one intends to copy the entire data memory to the scratchpad without reading data, a starting address is not required; the master may send a Reset Pulse immediately following the command code. 3.3.5 WRITE APPLICATION REGISTER [99h] This command is essentially the same as the Write Scratchpad command, but it addresses the 64-bit register scratchpad. After issuing the command code, the master must provide a 1-byte address, followed by the data to be written. The DS1971 will automatically increment the address after every byte it received. After having received a data byte for address 07h, the address counter will wrap around to 00h for the next byte and writing continues until the master sends a Reset Pulse. The Write Application Register command can be used as long as the application register has not yet been locked. If issued for a device with the application register locked, the data written to the register scratchpad will be lost. 3.3.6 READ STATUS REGISTER [66h] The status register is a means for the master to find out if the application register has been programmed and locked. After issuing the read status register command, the master must provide the validation key 00h before receiving status information. The two least significant bits of the 8-bit status register will be 0 if the application register was programmed and locked; all other bits will always read 1. The master may finish the read status command by sending a Reset Pulse at any time. 3.3.7 READ APPLICATION REGISTER [C3h] This command is used to read the application register or the register scratchpad. As long as the application register is not yet locked, one will receive data from the register scratchpad. After the application register is locked the DS1971 will transmit data from the application register, making the register scratchpad inaccessible for reading. The contents of the status register indicates where the data received with this command came from. After issuing the Read Application Register command, the master must provide the 1-byte starting address from where data is to be read. The DS1971 will

automatically increment the address after every byte read by the master. After the data of address 07h has been read, the address counter will wrap around to 00h for the next byte and reading continues until the master sends a Reset Pulse. 3.3.8 COPY & LOCK APPLICATION REGISTER [5Ah] After the data stored in the register scratchpad has been verified the master may send the Copy & Lock Application Register command followed by a validation key of A5h to transfer the contents of the entire register scratchpad to the application register and to simultaneously write-protect it. The master may cancel this command by sending a Reset Pulse instead of the validation key. After the validation key was transmitted, the application register will contain the data of the register scratchpad. Further write accesses to the application register will be denied. The Copy & Lock Application Register command can only be executed once. 3.3.9 Read ROM [33h] This command allows the bus master to read the DS1971s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS1971 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will usually result in a mismatch of the CRC. 3.3.10 Match ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1971 on a multidrop bus. Only the DS1971 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the bus. 3.3.11 Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). 3.3.12 Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The Search ROM process is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 3.3.13 Transaction Sequence The sequence for accessing the DS1971 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Transaction/Data 3.4 DS1972 3.4.1 WRITE SCRATCHPAD COMMAND [0Fh] The Write Scratchpad command applies to the data memory, and the writable addresses in the register page. In order for the scratchpad data to be valid for copying to the array, the user must perform a Write Scratchpad command of 8 bytes starting at a valid row boundary. The Write Scratchpad command accepts invalid addresses, and partial rows, but subsequent Copy Scratchpad commands are blocked. After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T2:T0. The E/S bits E2:E0 are loaded with the starting byte offset, and increment with each susequent byte. Effectively, E2:E0 is the byte offset of the last full byte written to the scratchpad.

Only full data bytes are accepted. When executing the Write Scratchpad command, the CRC generator inside the DS1972 (Figure 13) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the Target Addresses (TA1 and TA2), and all the data bytes. Note that the CRC16 calculation is performed with the actual TA1 and TA2 and data sent by the master. The master may end the Write Scratchpad command at any time. However, if the end of the scratchpad is reached (E2:E0 = 111b), the master may send 16 read-time slots and receive the CRC generated by the DS1972. If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad is loaded with the bitwise logical AND of the transmitted data and data already in memory. 3.4.2 READ SCRATCHPAD COMMAND [AAh] The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After issuing the command code, the master begins reading. The first two bytes are the target address. The next byte is the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the master originally sent. This is of particular importance if the target address is within the register page or a page in either Write Protection or EPROM modes. See the Write Scratchpad description for details. The master should read through the scratchpad (E2:E0 - T2:T0 + 1 bytes), after which it will receive the inverted CRC, based on data as it was sent by the DS1972. If the master continues reading after the CRC, all data will be logic 1s. 3.4.3 COPY SCRATCHPAD [55h] The Copy Scratchpad command is used to copy data from the scratchpad to writable memory sections. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which should have been obtained by an immediately preceding Read Scratchpad command. This 3byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the target address is valid, the PF flag is not set, and the target memory is not copy-protected, the AA (Authorization Accepted) flag is set and the copy begins. All eight bytes of scratchpad contents are copied to the target memory location. The duration of the devices internal data transfer is tPROG during which the voltage on the 1-Wire bus must not fall below 2.8V. A pattern of alternating 0s and 1s are transmitted after the data has been copied until the master issues a Reset Pulse. If the PF flag is set or the target memory is copy-protected, the copy will not begin and the AA flag will not be set. If the copy command was disturbed due to lack of power or for other reasons, the master will read a constant stream of FFh bytes until it sends a 1-Wire Reset Pulse. In this case the destination memory may be incompletely programmed requiring a write scratchpad and copy scratchpad be repeated to ensure proper programming of the EEPROM. This requires careful consideration when designing application software that writes to the DS1972 in an intermittent contact environment. 3.4.4 READ MEMORY [F0h] The Read Memory command is the general function to read data from the DS1972. After issuing the command, the master must provide the 2-byte target address. After these two bytes, the master reads data beginning from the target address and may continue until address 008Fh. If the master continues reading, the result will be logic 1s. The device's internal TA1, TA2, E/S, and scratchpad contents are not affected by a Read Memory command. 3.4.5 READ ROM [33h] This command allows the bus master to read the DS1972s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC. 3.4.6 MATCH ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1972 on a multidrop bus. Only the DS1972 that exactly matches the 64-bit ROM sequence responds to the following memory function command. All other slaves wait for a Reset Pulse. This command can be used with a single or multiple devices on the bus.

3.4.7 SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. 3.4.8 SKIP ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a Read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). 3.4.9 RESUME [A5h] To maximize the data throughput in a multidrop environment, the Resume function is available. This function checks the status of the RC bit and, if it is set, directly transfers control to the memory functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive-Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume Command function. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume Command function. 3.4.10 OVERDRIVE-SKIP ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive-Skip ROM sets the DS1972 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a Reset Pulse of minimum 480s duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrivesupporting device, a Reset Pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive-Skip ROM command is followed by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (opendrainpulldowns produce a wired-AND result). 3.4.11 OVERDRIVE-MATCH ROM [69h] The Overdrive-Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive Speed allows the bus master to address a specific DS1972 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS1972 that exactly matches the 64-bit ROM sequence responds to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive-Skip or successful Overdrive-Match command remain in Overdrive mode. All overdrivecapable slaves return to standard speed at the next Reset Pulse of minimum 480s duration. The Overdrive-Match ROM command can be used with a single or multiple devices on the bus. 3.4.12 TRANSACTION SEQUENCE The protocol for accessing the DS1972 through the 1-Wire port is as follows: __ Initialization __ ROM Function Command __ Memory Function Command __ Transaction/Data

3.5 DS1973 3.5.1 WRITE SCRATCHPAD COMMAND [0FH] After issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4:E0) will be the byte offset at which the master stops writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be ignored and the partial byte flag PF will be set. When executing the Write Scratchpad command the CRC generator inside the DS1973 (see Figure 12) calculates a CRC over the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read time slots and will receive the CRC generated by the DS1973. The memory address range of the DS1973 is 0000H to 01FFH. If the bus master sends a target address higher than this, the internal circuitry of the chip will set the seven most significant address bits to zero as they are shifted into the internal address register. The Read Scratchpad command will reveal the target address as it will be used by the DS1973. The master will identify such address modifications by comparing the target address read back to the target address transmitted. If the master does not read the scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the target address the master sends will not match the value the DS1973 expects. 3.5.2 READ SCRATCHPAD COMMAND [AAH] This command is used to verify scratchpad data and target address. After issuing the read scratchpad command, the master begins reading. The first two bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4:T0). The master may read data until the end of the scratchpad after which the data read will be all logic 1s. 3.5.3 COPY SCRATCHPAD [55H] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern which can be obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin. Copy takes 5 ms maximum during which the voltage on the 1-Wire bus must not fall below 2.8V. A pattern of alternating 1s and 0s will be received after the data has been copied until a Reset Pulse is issued by the master. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset, will be copied to memory, starting at the target address. Anywhere from 1 to 32 bytes may be copied to memory with this command. 3.5.4 READ MEMORY [F0H] The read memory command may be used to read the entire memory. After issuing the command, the master must provide the 2-byte target address. After the two bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS1973 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to insure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See the Book of DS19xx iButton Standards, Chapter 7 or Application Note 114 for the recommended file structure.) 3.5.5 READ ROM [33H] This command allows the bus master to read the DS1973s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1973 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will result in a mismatch of the CRC.

3.5.6 MATCH ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1973 on a multidrop bus. Only the DS1973 that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the bus. 3.5.7 SKIP ROM [CCH] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). 3.5.8 SEARCH ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 3.5.9 OVERDRIVE SKIP ROM [3CH] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive Skip ROM sets the DS1973 in the Overdrive Mode (OD = 1). All communication following this command has to occur at Overdrive Speed until a Reset Pulse of minimum 480_s duration resets all devices on the bus to regular speed (OD = 0). When issued on a multidrop bus this command will set all Overdrivesupporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a Reset Pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wire-AND result). 3.5.10 OVERDRIVE MATCH ROM [69H] The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive Speed, allows the bus master to address a specific DS1973 on a multidrop bus and to simultaneously set it in Overdrive Mode. Only the DS1973 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive Skip or Match command will remain in Overdrive mode. All overdrive-capable slaves will return to regular speed at the next Reset Pulse of minimum 480_s duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 3.5.11 TRANSACTION SEQUENCE The protocol for accessing the DS1973 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Transaction/Data 3.6 DS1977 3.6.1 Write Scratchpad Command [0Fh] This command is used to specify the target address and to write data to the scratchpad for verification before the transfer to the EEPROM can be initiated. After issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad.

The data will be written to the scratchpad starting at the byte offset (T5:T0). The ending offset (E5: E0) will be the byte offset at which the master stops writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be ignored and the partial byte flag PF will be set. When writing to a password address, internal circuitry of the chip will force the 3 least significant address bits to 0. Only full 8-byte passwords are accepted. The ending offset will be 07 or 0F, depending on the password(s) to be changed. When executing the Write Scratchpad command the CRC generator inside the DS1977 (Figure 13) calculates an inverted CRC over the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write Scratchpad command at any time. However, if the ending offset is 3Fh, the master may send 16 read-time slots and will receive the CRC generated by the DS1977 . The memory address range of the DS1977 is 0000h to 7FFFh (Figure 5). There is no user-access to the address range 7FD1h to 7FFFh. If the master sends a target address higher than this, the internal circuitry of the chip will set the most significant address bit to zero as it is shifted into the internal address register. The Read Scratchpad command will reveal the target address as it will be used by the DS1977 . The master will identify such address modifications by comparing the target address read back to the target address transmitted. If the master does not read the scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the target address the master sends will not match the value the DS1977 expects. 3.6.2 Read Scratchpad Command [AAh] This command is used to verify scratchpad data and target address. After issuing the Read Scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T5:T0), as shown in Figure 6. Regardless of the actual ending offset the master may continue reading data until the end of the scratchpad after which it will receive an inverted CRC16 of the command code, Target Addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the byte offset, which is determined by the target address. After the CRC is read, the bus master will read logical 1s from the DS1977 until a reset pulse is issued. 3.6.3 Copy Scratchpad with Password [99h] This command is used to transfer data from the scratchpad to the memory. After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern, which can be obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). Next the master must send a valid full-access password, or, if passwords are not enabled, 8 dummy bytes. Now the master must provide power by bypassing the 1-Wire pullup resistor with an electronic switch, generating a "strong pullup". If authorization pattern and password are accepted, the AA (Authorization Accepted) flag will be set and the copy will begin. Copy takes 10ms maximum during which the voltage on the 1- Wire bus must not fall below 2.8V. After the copy is completed, the master turns off the strong pullup and begins reading from the 1-Wire. A pattern of alternating 1s and 0s will indicate that the copy command was executed successfully. If the copy command was disturbed due to lack of power or for other reasons (see Figure 7-2, "strong pullup valid?"), the master will read a constant stream of FFh bytes until it sends a 1-Wire reset pulse. In this case the destination memory may be incompletely programmed requiring a write scratchpad and copy scratchpad be repeated to ensure proper programming of the EEPROM. This requires careful consideration when designing application software that writes to the DS1977 in an intermittent contact environment. The data to be copied is determined by the three address registers (TA1, TA2, E/S). The scratchpad data from the beginning offset through the ending offset will be copied to memory, starting at the target address. Anywhere from 1 to 64 bytes may be copied to memory with this command. 3.6.4 Read Memory with Password [69h] This command is used to read the entire memory, except for the passwords. After issuing the command, the master must provide the 2-byte target address. Next the master must send a valid read access password, or, if passwords are not enabled, 8 dummy bytes. Now the master must provide power by bypassing the 1-Wire pullup resistor with an electronic switch, generating a "strong pullup". If the password was accepted, EEPROM data beginning at the specified target address and ending at the page boundary will be loaded into the scratchpad starting at the beginning offset. This transfer takes 5 ms maximum during which the voltage on the 1-Wire bus must not fall below 2.8V. After the transfer is completed, the master turns off the strong pullup and begins reading from the 1-Wire. When the end of

the memory page (end of scratchpad) is reached, the master will receive an inverted CRC16 of the command, target address and page data. If the master wants to read more data and the end of the memory is not yet reached, it again has to activate the strong pullup. This will transfer a full 64-byte page of memory data to the scratchpad from where the master can read it by issuing read-time slots. This transfer only takes place if the DS1977 receives enough power through the 1-Wire line (see Figure 7-3, "strong pullup valid?"). The loop of strong pullup and reading 64 bytes can be repeated until the end of the memory is reached, at which point the master will read logic 1's. 3.6.5 Verify Password [C3h] This command allows the user to verify whether the process of updating a password was successful, eliminating the risk of a weak programming of the memory cells that actually store the password. The command allows verifying one password at a time. After issuing the command code, the master must send the memory address of the password to be verified. Next the master transmits the password itself and generates a strong pullup to provide the power for the password comparison. This takes 5ms maximum, during which the voltage on the 1-Wire bus must not fall below 2.8V. After the comparison is completed, the master turns off the strong pullup and begins reading from the 1-Wire line. A pattern of alternating 1's and 0's indicates that the verification was successful, i. e., the password supplied by the master matches the one stored in the DS1977. If the passwords do not match, the master will read a constant stream of FFh bytes until it sends a reset pulse. Before changing a password, first disable the use of passwords. Then using Write Scratchpad, Read Scratchpad and Copy Scratchpad, write the new password to its respective memory location. Now use Verify Password to double-check whether the password reads correctly from the EEPROM memory. If the verification is successful, it is safe to again enable passwords. 3.6.6 Read Version Command [CCh] This command allows the master to read the chip revision code of the DS1977. After issuing the command code, the master sends two 00h-bytes to access the version register. With the next 16 time slots the master receives two copies of the content of the version register. Additional read-time slots will read logic 1's. Only the upper 3 bits of the version register are valid. The lower 5 bits will all read 0. 3.6.7 READ ROM [33H] This command allows the bus master to read the DS1977s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1977 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will result in a mismatch of the CRC. 3.6.8 MATCH ROM [55H] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specificDS1977 on a multidrop bus. Only the DS1977 that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 3.6.9 SEARCH ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Application Note 187 for a comprehensive discussion of the 1-Wire search algorithm. 3.6.10 SKIP ROM [CCH] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a Read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).

3.6.11 RESUME COMMAND [A5h] The Resume Command function maximizes the data throughput in a multidrop environment. This function checks the status of the RC bit and, if it is set, directly transfers control to the Memory/Control functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM or Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume Command function. Accessing another device on the bus will clear the RC bit, preventing two or more devices from simultaneously responding to the Resume Command function. 3.6.12 OVERDRIVE SKIP ROM [3CH] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS1977 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480s duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus this command will set all Overdrivesupporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). 3.6.13 OVERDRIVE MATCH ROM [69H] The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive Speed allows the bus master to address a specific DS1977 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS1977 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive Skip or Match command will remain in Overdrive mode. All overdrive-capable slaves will return to standard speed at the next Reset Pulse of minimum 480s duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 3.6.14 TRANSACTION SEQUENCE The protocol for accessing the DS1977 through the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Transaction/Data

4.0 iButton with NVRAM 4.1 DS1921 4.1.1 Write Scratchpad Command [0Fh] After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4:E0) will be the byte offset at which the master stops writing data. Only full data bytes are accepted. If the last data byte is incomplete, its content will be ignored and the partial byte flag (PF) will be set. When executing the Write Scratchpad command, the CRC generator inside the DS1921G (see Figure 16) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read time slots and will receive an inverted CRC16 generated by the DS1921G. The range 200h to 213h of the register page is protected during a mission. See Figure 6, Register Page Map, for the access type of the individual registers between and during missions. 4.1.2 Read Scratchpad Command [AAh] This command is used to verify scratchpad data and target address. After issuing the Read Scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4:T0), as shown in Figure 9. Regardless of the actual ending offset, the master may read data until the end of the scratchpad after which it will receive an inverted CRC16 of the command code, Target Addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the target address. After the CRC is read, the bus master will read logical 1s from the DS1921G until a reset pulse is issued. 4.1.3 Copy Scratchpad [55h] This command is used to copy data from the scratchpad to the writable memory sections. Applying Copy Scratchpad to the Sample Rate Register can start a mission provided that several preconditions are met. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which can be obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin. A pattern of alternating 1s and 0s will be transmitted after the data has been copied until the master issues a reset pulse. While the copy is in progress any attempt to reset the part will be ignored. Copy typically takes 2s per byte. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset will be copied, starting at the target address. Anywhere from 1 to 32 bytes may be copied to memory with this command. The AA flag will remain at logic 1 until it is cleared by the next Write Scratchpad command. Note that Copy Scratchpad when applied to the address range 200h to 213h during a mission will end the mission. 4.1.4 Read Memory [F0h] The Read Memory command may be used to read the entire memory. After issuing the command, the master must provide the 2-byte target address. After the 2 bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 0s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS1921G provides a means to accomplish error-free writing to the memory section. To safeguard data in the 1-Wire environment when reading and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to verify whether if the received data is correct. (See Application Note 114 for the recommended file structure.)

4.1.5 Read Memory with CRC [A5h] The Read Memory with CRC command is used to read memory data that cannot be packetized, such as the register page and the data recorded by the device during a mission. The command works essentially the same way as the simple Read Memory, except for the 16-bit CRC that the DS1921G generates and transmits following the last data byte of a memory page. After having sent the command code of the Read Memory with CRC command, the bus master sends a 2-byte address (TA1 = T7:T0, TA2 = T15:T8) that indicates a starting byte location. With the subsequent read data time slots the master receives data from the DS1921G starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send 16 additional read data time slots and receive an inverted 16-bit CRC. With subsequent read data time slots the master will receive data starting at the beginning of the next page followed again by the inverted CRC for that page. This sequence will continue until the bus master resets the device. With the initial pass through the Read Memory with CRC flow, the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator followed by the 2 address bytes and the contents of the data memory. Subsequent passes through the Read Memory with CRC flow will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the contents of the data memory page. After the 16-bit CRC of the last page is read, the bus master will receive logical 0s from the DS1921G and inverted CRC16s at page boundaries until a reset pulse is issued. The Read Memory with CRC command sequence can be ended at any point by issuing a reset pulse. 4.1.6 Clear Memory [3Ch] The Clear Memory command is used to clear the Sample Rate, Mission Start Delay, Mission Time Stamp, and Mission Samples Counter in the register page and the Temperature Alarm Memory and the Temperature Histogram Memory. These memory areas must be cleared for the device to be set up for another mission. The Clear Memory command does not clear the datalog memory or the temperature and timer alarm flags in the Status Register. The RTC oscillator must be on and have counted at least 1 second, before issuing the command. For the Clear Memory command to function the EMCLR bit in Control Register must be set to 1, and the Clear Memory command must be issued with the very next access to the devices memory functions. Issuing any other memory function command will reset the EMCLR bit. The Clear Memory process takes 500s. When the command is completed the MEMCLR bit in the Status Register will read 1 and the EMCLR bit will be 0. 4.1.7 Convert Temperature [44h] If a mission is not in progress (MIP = 0) the Convert Temperature command can be issued to measure the current temperature of the device. The result of the temperature conversion will be found at memory address 211h in the register page. This command takes maximum 90ms to complete. During this time the device remains fully accessible for memory/control and ROM function commands. 4.1.8 Read ROM [33h] This command allows the bus master to read the DS1921G's 8-bit family code, unique 48-bit serial number and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will result in a mismatch of the CRC. 4.1.9 Match ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1921G on a multidrop bus. Only the DS1921G that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All other slaves will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 4.1.10 Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating

in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to App Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. 4.1.11 Conditional Search [ECh] The Conditional Search ROM command operates similarly to the Search ROM command except that only devices fulfilling the specified condition will participate in the search. The condition is specified by the bit functions TAS, THS, and TLS in the Control Register, address 20Eh. The Conditional Search ROM provides an efficient means for the bus master to determine devices on a multidrop system that have to signal an important event, such as a temperature leaving the tolerance band. After each pass of the conditional search that successfully determined the 64-bit ROM code for a specific device on the multidrop bus, that particular device can be individually accessed as if a Match ROM had been issued, since all other devices will have dropped out of the search process and will be waiting for a reset pulse. For the conditional search, one can select any combination of the three search conditions by writing the associated bit to a logical 1. These bits correspond directly to the flags in the Status Register of the device. If the flag in the status register reads 1 and the corresponding bit in the Control Register is a logical 1 too, the device will respond to the Conditional Search command. If more than one bit search condition is selected, the first event occurring will make the device respond to the Conditional Search command. 4.1.12 Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a Read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wiredAND result). 4.1.13 Overdrive Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory/control functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS1921G in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480s duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus this command will set all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). 4.1.14 Overdrive Match ROM [69h] The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive Speed allows the bus master to address a specific DS1921G on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS1921G that exactly matches the 64-bit ROM sequence will respond to the subsequent memory/control function command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match command will remain in Overdrive mode. All overdrivecapable slaves will return to standard speed at the next Reset Pulse of minimum 480s duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 4.1.15 TRANSACTION SEQUENCE The protocol for accessing the DS1921G via the 1-Wire port is as follows: __Initialization __ROM Function Command __Memory/Control Function Command __Transaction/Data

4.2 DS1922 4.2.1 WRITE SCRATCHPAD COMMAND [0FH] After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset (T4:T0). The master has to send as many bytes as are needed to reach the Ending Offset of 1Fh. If a data byte is incomplete, its content is ignored and the partial byte flag PF is set. When executing the Write Scratchpad command the CRC generator inside the DS1922L/T (see Figure 15) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the target addresses TA1 and TA2 as supplied by the master and all the data bytes. If the ending offset is 11111b, the master may send 16 read time slots and receive the inverted CRC16 generated by the DS1922L/T. Note that both register pages are write-protected during a mission. Although the Write Scratchpad command works normally at any time, the subsequent copy scratchpad to a register page will fail during a mission. 4.2.2 READ SCRATCHPAD COMMAND [AAH] This command is used to verify scratchpad data and target address. After issuing the Read Scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte is the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4:T0), as shown in Figure 8. The master may continue reading data until the end of the scratchpad after which it receives an inverted CRC16 of the command code, Target Addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the target address. After the CRC is read, the bus master reads logical 1s from the DS1922L/T until a reset pulse is issued. 4.2.3 COPY SCRATCHPAD WITH PASSWORD [99H] This command is used to copy data from the scratchpad to the writable memory sections. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which can be obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). Next the master must transmit the 64-bit full-access password. If passwords are enabled and the transmitted password is different from the stored full-access password, the Copy Scratchpad with Password command will fail. The device will stop communicating and will wait for a reset pulse. If the password was correct or if passwords were not enabled, the device will test the 3-byte authorization code. If the authorization code pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin. A pattern of alternating 1s and 0s will be transmitted after the data has been copied until the master issues a reset pulse. While the copy is in progress any attempt to reset the part will be ignored. Copy typically takes 2s per byte. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset will be copied, starting at the target address. The AA flag will remain at logic 1 until it is cleared by the next Write Scratchpad command. With suitable password, the copy scratchpad always functions for the 16 pages of data memory and the 2 pages of calibration memory. While a mission is in prog??ress, write attempts to the register pages are not successful. The AA bit (Authorization Accepted) remaining at 0 indicates this. 4.2.4 READ MEMORY WITH PASSWORD AND CRC [69H] The Read Memory with CRC command is the general function to read from the device. This command generates and transmits a 16-bit CRC following the last data byte of a memory page. After having sent the command code of the Read Memory with CRC command, the bus master sends a 2-byte address that indicates a starting byte location. Next the master must transmit one of the 64-bit passwords. If passwords are enabled and the transmitted password does not match one of the stored passwords, the Read Memory with Password and CRC command will fail. The device will stop communicating and will wait for a reset pulse. If the password was correct or if passwords were not enabled, the master reads data from the DS1922L/T beginning from the starting address and continuing until the end of a 32-byte page is reached. At that point the bus master will send 16 additional read data time slots and receive the inverted 16-bit CRC. With subsequent read data time slots the master will receive data starting at the beginning of the next memory page followed again by the CRC for that page. This sequence will continue until the bus master resets the device. When trying to read the passwords or memory areas that are marked as "reserved", the DS1922L/T will transmit 00h or FFh bytes respectively. The CRC at the end of a 32-byte memory page is based on the data as it was transmitted. With the initial pass

through the Read Memory with CRC flow, the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator followed by the 2 address bytes and the contents of the data memory. Subsequent passes through the Read Memory with CRC flow will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the contents of the data memory page. After the 16-bit CRC of the last page is read, the bus master will receive logical 1s from the DS1922L/T until a reset pulse is issued. The Read Memory with CRC command sequence can be ended at any point by issuing a reset pulse. 4.2.5 CLEAR MEMORY WITH PASSWORD [96H] The Clear Memory with Password command is used to prepare the device for another mission. This command is only executed if no mission is in progress. After the command code the master must transmit the 64-bit full-access password followed by a FFh dummy byte. If passwords are enabled and the transmitted password is different from the stored full-access password or a mission is in progress, the Clear Memory with Password command will fail. The device will stop communicating and will wait for a reset pulse. If the password was correct or if passwords were not enabled, the device will clear the Mission Time Stamp, Mission Samples Counter, and all alarm flags of the Alarm Status Register. After these cells are cleared, the MEMCLR bit of the General Status Register will read 1 to indicate the successful execution of the Clear Memory with Password command. Clearing of the datalog memory is not necessary because the Mission Samples Counter indicates how many entries in the datalog memory are valid. 4.2.6 FORCED CONVERSION [55H] The Forced Conversion command can be used to measure the temperature without starting a mission. After the command code the master has to send one FFh byte to get the conversion started. The conversion result is found as 16-bit value in the Latest Temperature Conversion Result register. This command is only executed if no mission is in progress (MIP = 0). It cannot be interrupted and takes maximum 600 ms to complete. During this time memory access through the 1-Wire interface is blocked. The device will behave the same way as during a mission when the sampling interferes with a memory/control function command. A forced conversion must not be attempted while the RTC oscillator is stopped. This will cause the device to enter into an unrecoverable state. 4.2.7 START MISSION WITH PASSWORD [CCH] The DS1922L/T uses a control function command to start a mission. A new mission can only be started if the previous mission has been ended and the memory has been cleared. After the command code, the master must transmit the 64-bit full-access password followed by a FFh dummy byte. If passwords are enabled and the transmitted password is different from the stored full-access password or a mission is in progress, the Start Mission with Password command will fail. The device will stop communicating and will wait for a reset pulse. If the password was correct or if passwords were not enabled, the device will start a mission. If SUTA = 0, the sampling begins as soon as the mission start delay is over. If SUTA = 1, the first sample is written to the data log memory at the time the temperature alarm occurred. However, the Mission Sample Counter does not increment. One sample period later, the Mission Time Stamp will be set and the regular sampling and logging begins. While the device is waiting for a temperature alarm to occur, the WFTA flag in the general status register will read 1. During a mission there is only read access to the Register Pages. 4.2.8 STOP MISSION WITH PASSWORD [33H] The DS1922L/T uses a control function command to stop a mission. Only a mission that is in progress can be stopped. After the command code, the master must transmit the 64-bit full-access password followed by a FFh dummy byte. If passwords are enabled and the transmitted password is different from the stored full-access password or a mission is not in progress, the Stop Mission with Password command will fail. The device will stop communicating and will wait for a reset pulse. If the password was correct or if passwords were not enabled, the device will clear the MIP bit in the General Status Register and restore write access to the Register Pages. The WFTA bit is not cleared. See the description of the General Status Register for a method to clear the WFTA bit. 4.2.9 READ ROM [33H] This command allows the bus master to read the DS1922L/Ts 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same

time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number results in a mismatch of the CRC. 4.2.10 MATCH ROM [55H] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1922L/T on a multidrop bus. Only the DS1922L/T that exactly matches the 64-bit ROM sequence responds to the following memory function command. All other slaves wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 4.2.11 SEARCH ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both sates of the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to App Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. 4.2.12 CONDITIONAL SEARCH [ECH] The Conditional Search ROM command operates similarly to the Search ROM command except that only those devices, which fulfill certain conditions, participates in the search. This function provides an efficient means for the bus master to identify devices on a multidrop system that have to signal an important event. After each pass of the conditional search that successfully determined the 64-bit ROM code for a specific device on the multidrop bus, that particular device can be individually accessed as if a Match ROM had been issued, since all other devices will have dropped out of the search process and will be waiting for a reset pulse. The DS1922L/T will respond to the conditional search if one of the three alarm flags of the Alarm Status Register (address 0214h) reads 1. The temperature alarm will only occur if enabled. The BOR alarm is always enabled. The first alarm that occurs will make the device respond to the Conditional Search command. 4.2.13 SKIP ROM [CCH] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a Read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open-drain pulldowns will produce a wiredAND result). 4.2.14 RESUME COMMAND [A5h] The DS1922L/T needs to be accessed several times before a mission will start. In a multidrop environment this means that the 64-bit ROM code after a Match ROM command has to be repeated for every access. To maximize the data throughput in a multidrop environment, the Resume function was implemented. This function checks the status of the RC bit and, if it is set, directly transfers control to the Memory/Control functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume Command function. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume Command function. 4.2.15 OVERDRIVE SKIP ROM [3CH] On a single-drop bus this command can save time by allowing the bus master to access the memory/control functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS1922L/T in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 690s duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus this command sets all Overdrive-supporting devices into Overdrive mode. To subsequently address

a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). 4.2.16 OVERDRIVE MATCH ROM [69H] The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive speed allows the bus master to address a specific DS1922L/T on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS1922L/T that exactly matches the 64-bit ROM sequence responds to the subsequent memory/control function command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match command remain in Overdrive mode. All overdrive-capable slaves will return to standard speed at the next reset pulse of minimum 690s duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 4.2.17 TRANSACTION SEQUENCE The protocol for accessing the DS1922L/T through the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory/Control Function Command _ Transaction/Data 4.3 DS1923 4.3.1 Write Scratchpad Command [0Fh] After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The master has to send as many bytes as are needed to reach the Ending Offset of 1Fh. If a data byte is incomplete, its content is ignored and the partial byte flag PF is set. When executing the Write Scratchpad command the CRC generator inside the DS1923 (see Figure 15) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the master and all the data bytes. If the ending offset is 11111b, the master may send 16 read time slots and will receive the inverted CRC16 generated by the DS1923. Note that both register pages are write-protected during a mission. Although the Write Scratchpad command will work normally at any time, the subsequent copy scratchpad to a register page will fail during a mission. 4.3.2 Read Scratchpad Command [AAh] This command is used to verify scratchpad data and target address. After issuing the Read Scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4:T0), as shown in Figure 8. The master may continue reading data until the end of the scratchpad after which it will receive an inverted CRC16 of the command code, Target Addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the target address. After the CRC is read, the bus master will read logical 1s from the DS1923 until a reset pulse is issued. 4.3.3 Copy Scratchpad with Password [99h] This command is used to copy data from the scratchpad to the writable memory sections. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which can be obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). Next the master must transmit the 64-bit full-access password. If passwords are enabled and the transmitted password is different from the stored full-access password, the Copy Scratchpad with Password command will fail. Then the device stops communicating and waits for a reset pulse. If the password was correct or if passwords were not enabled, the device tests the 3-byte authorization code. If the authorization code pattern matches, the AA (Authorization Accepted) flag is set and the copy begins. A pattern of alternating 1s and 0s are transmitted after the data has been copied until the master issues a reset pulse. While the copy is in

progress any attempt to reset the part is ignored. Copy typically takes 2s per byte. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset will be copied, starting at the target address. The AA flag remains at logic 1 until it is cleared by the next Write Scratchpad command. With suitable password, the copy scratchpad always functions for the 16 pages of data memory and the 2 pages of calibration memory. While a mission is in progress, write attempts to the register pages will not be successful. The AA bit (Authorization Accepted) remaining at 0 will indicate this. 4.3.4 Read Memory with Password and CRC [69h] The Read Memory with CRC command is the general function to read from the device. This command generates and transmits a 16-bit CRC following the last data byte of a memory page. After having sent the command code of the Read Memory with CRC command, the bus master sends a 2-byte address that indicates a starting byte location. Next the master must transmit one of the 64-bit passwords. If passwords are enabled and the transmitted password does not match one of the stored passwords, the Read Memory with Password and CRC command fails. The device will stop communicating and will wait for a reset pulse. If the password was correct or if passwords were not enabled, the master reads data from the DS1923 beginning from the starting address and continuing until the end of a 32-byte page is reached. At that point the bus master sends 16 additional read data time slots and receive the inverted 16-bit CRC. With subsequent read-data time slots the master will receive data starting at the beginning of the next memory page followed again by the CRC for that page. This sequence continues until the bus master resets the device. When trying to read the passwords or memory areas that are marked as "reserved", the DS1923 transmits 00h or FFh bytes, respectively. The CRC at the end of a 32-byte memory page is based on the data as it was transmitted. With the initial pass through the Read Memory with CRC flow, the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator followed by the 2 address bytes and the contents of the data memory. Subsequent passes through the Read Memory with CRC flow will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the contents of the data memory page. After the 16-bit CRC of the last page is read, the bus master receives logical 1s from the DS1923 until a reset pulse is issued. The Read Memory with CRC command sequence can be ended at any point by issuing a reset pulse. 4.3.5 Clear Memory with Password [96h] The Clear Memory with Password command is used to prepare the device for another mission. This command is only executed if no mission is in progress. After the command code the master must transmit the 64-bit full-access password followed by a FFh dummy byte. If passwords are enabled and the transmitted password is different from the stored full-access password or a mission is in progress, the Clear Memory with Password command will fail. The device will stop communicating and will wait for a reset pulse. If the password was correct or if passwords were not enabled, the device will clear the Mission Time Stamp, Mission Sample Counter, and all alarm flags of the Alarm Status Register. After these cells are cleared, the MEMCLR bit of the General Status Register reads 1 to indicate the successful execution of the Clear Memory with Password command. Clearing of the data log memory is not necessary because the Mission Sample Counter indicates how many entries in the data log memory are valid. 4.3.6 Forced Conversion [55h] The Forced Conversion command can be used to measure the temperature and humidity without starting a mission. After the command code the master has to send one FFh byte to get the conversion started. The conversion result is found as 16-bit value in the Latest Temperature Conversion Result and Latest Humidity Conversion Result registers. This command is only executed if no mission is in progress (MIP = 0). It cannot be interrupted and takes maximum 666ms to complete. During this time memory access through the 1-Wire interface is blocked. The device behaves the same way as during a mission when the sampling interferes with a memory/control function command. See Memory Access Conflicts for details. A forced conversion must not be attempted while the RTC oscillator is stopped. This causes the device to enter into an unrecoverable state. 4.3.7 Start Mission with Password [CCh] The DS1923 uses a control function command to start a mission. A new mission can only be started if the previous mission has been ended and the memory has been cleared. After the command code, the master must transmit the 64-bit full-access password followed by a FFh dummy byte. If passwords are enabled and the transmitted password is different from the stored full-access password or a mission is in progress, the Start Mission with Password command will fail. The device stops communicating and waits for a reset pulse. If the password was correct or if passwords were not enabled, the device starts

a mission. If SUTA = 0, the sampling begins as soon as the mission start delay is over. If SUTA = 1, the first sample is written to the data log memory at the time the temperature alarm occurred. However, the Mission Sample Counter does not increment. One sample period later, the Mission Time Stamp will be set and the regular sampling and logging begins. While the device is waiting for a temperature alarm to occur, the WFTA flag in the general status register will read 1. During a mission there is only read access to the Register Pages. 4.3.8 Stop Mission with Password [33h] The DS1923 uses a control function command to stop a mission. Only a mission that is in progress can be stopped. After the command code, the master must transmit the 64-bit full-access password followed by a FFh dummy byte. If passwords are enabled and the transmitted password is different from the stored full-access password or a mission is not in progress, the Stop Mission with Password command will fail. The device stops communicating and waits for a reset pulse. If the password was correct or if passwords were not enabled, the device clears the MIP bit in the General Status Register and restore write access to the Register Pages. The WFTA bit is not cleared. See the description of the General Status Register for a method to clear the WFTA bit. 4.3.9 Read ROM [33h] This command allows the bus master to read the DS1923s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open-drain produces a wired-AND result). The resultant family code and 48-bit serial number results in a mismatch of the CRC. 4.3.10 Match ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1923 on a multidrop bus. Only the DS1923 that exactly matches the 64-bit ROM sequence responds to the following memory function command. All other slaves will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 4.3.11 Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to App Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. 4.3.12 Conditional Search [ECh] The Conditional Search ROM command operates similarly to the Search ROM command except that only those devices, which fulfill certain conditions, participate in the search. This function provides an efficient means for the bus master to identify devices on a multidrop system that have to signal an important event. After each pass of the conditional search that successfully determined the 64-bit ROM code for a specific device on the multidrop bus, that particular device can be individually accessed as if a Match ROM had been issued, since all other devices have dropped out of the search process and will be waiting for a reset pulse. The DS1923 responds to the conditional search if one of the five alarm flags of the Alarm Status Register (address 0214h) reads 1. The humidity and temperature alarm only occurs if enabled (see Temperature Sensor Alarm and Humidity Alarm). The BOR alarm is always enabled. The first alarm that occurs makes the device respond to the Conditional Search command. 4.3.13 Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a Read command is issued following the Skip ROM command, data collision occurs

on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). 4.3.14 Resume Command [A5h] The DS1923 needs to be accessed several times before a mission starts. In a multidrop environment this means that the 64-bit ROM code after a Match ROM command has to be repeated for every access. To maximize the data throughput in a multidrop environment, the Resume function was implemented. This function checks the status of the RC bit and, if it is set, directly transfers control to the Memory/Control functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM or Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume Command function. Accessing another device on the bus will clear the RC bit, preventing two or more devices from simultaneously responding to the Resume Command function. 4.3.15 Overdrive Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory/control functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS1923 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 690s duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus this command will set all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns will produce a wired-AND result). 4.3.16 Overdrive Match ROM [69h] The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive Speed allows the bus master to address a specific DS1923 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS1923 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory/control function command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match command remains in Overdrive mode. All overdrive-capable slaves return to standard speed at the next Reset Pulse of minimum 690s duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 4.3.17 TRANSACTION SEQUENCE The protocol for accessing the DS1923 through the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory/Control Function Command _ Transaction/Data 4.4 DS1963 4.4.1 Write Scratchpad Command [0FH] After issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the master stops writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be ignored and the partial byte flag PF will be set. When executing the Write Scratchpad command the CRC generator inside the DS1963L (see Figure 12) calculates a CRC over the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read time slots and will receive the CRC generated by the DS1963L. The memory address range of the DS1963L is 0000H to 01FFH. If the bus master sends a target address higher than this, the internal circuitry of the chip will set the seven most significant address bits to 0 as they are shifted into the internal address register.

The Read Scratchpad command will reveal the target address as it will be used by the DS1963L. The master will identify such address modifications by comparing the target address read back to the target address transmitted. If the master does not read the scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the target address the master sends will not match the value the DS1963L expects. 4.4.2 Read Scratchpad Command [AAH] This command is used to verify scratchpad data and target address. After issuing the read scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4: T0). The master may read data until the end of the scratchpad after which the data read will be all logic 1s. 4.4.3 Copy Scratchpad [5AH] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern which can be obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin. A pattern of alternating 1s and 0s will be transmitted after the data has been copied until a reset pulse is issued by the master. Any attempt to reset the part will be ignored while the copy is in progress. Copy typically takes 30 ms. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset, will be copied to memory, starting at the target address. Anywhere from 1 to 32 bytes may be copied to memory with this command. The AA flag will be cleared only by executing a write scratchpad command. 4.4.4 Read Memory [F0H] The read memory command may be used to read the entire memory. After issuing the command, the master must provide the 2-byte target address. After the 2 bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS1963L provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See the Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure.) 4.4.5 Read Memory + Counter [A5H] The Read Memory + Counter command is used to read memory data together with the write cycle counter associated with the addressed page of data memory. The additional information is transmitted by the DS1963L as the end of a memory page is encountered. Following the current value of the page write cycle counter the DS1963L transmits 32 tamper-detect bits and a 16-bit CRC generated by the DS1963L. The tamper-detect bits are factory-preset to 55555555H and locked. Tampering with the device will change this data pattern. After having sent the command code of the Read Memory + Counter command, the bus master sends a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With the subsequent read data time slots the master receives data from the DS1963L starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send 80 additional read data time slots and receive the contents of the 32-bit write cycle counter associated with the addressed page, the status of the 32 tamper-detect bits and a 16-bit CRC. With subsequent read data time slots the master will receive data starting at the beginning of the next page followed again by the contents of the page write cycle counter, tamper-detect bits and CRC for that page. This sequence will continue until the final page and its accompanying data are read by the bus master. When applying the Read Memory + Counter command to a page that does not have a page write cycle counter associated, the master will read FFFFFFFFH instead of a valid cycle count. With the initial pass through the Read Memory + Counter flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the 2 address bytes, the contents of the data memory, the write page cycle counter and the tamper-detect bits. Subsequent passes through the Read Memory + Counter flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the contents of the data memory page, its associated page write cycle counter and tamper-detect bits. After

the 16-bit CRC of the last page is read, the bus master will receive logical 1s from the DS1963L until a Reset Pulse is issued. The Read Memory + Counter command sequence can be ended at any point by issuing a Reset Pulse. 4.4.6 Read ROM [33H] This command allows the bus master to read the DS1963Ls 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1963L on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will result in a mismatch of the CRC. 4.4.7 Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1963L on a multidrop bus. Only the DS1963L that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 4.4.8 Skip ROM [CCH] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-AND result). 4.4.9 Search ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 4.4.10 Overdrive Skip ROM [3CH] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive Skip ROM sets the DS1963L in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480 ms duration resets all devices on the bus to regular speed (OD = 0). When issued on a multidrop bus this command will set all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrivesupporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). 4.4.11 Overdrive Match ROM [69H] The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive speed, allows the bus master to address a specific DS1963L on a multidrop bus and to simultaneously set it in Overdrive Mode. Only the DS1963L that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive Skip or Match command will remain in Overdrive mode. All other slaves that do not match the 64-bit ROM sequence or do not support Overdrive will return to or remain at regular speed and wait for a reset pulse of minimum 480 ms duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus.

4.4.12 TRANSACTION SEQUENCE The protocol for accessing the DS1963L via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Transaction/Data 4.5 DS1991 4.5.1 Write Scratchpad [96H] The Write Scratchpad command is used to enter data into the scratchpad. The starting address for the write sequence is specified in the command. Data can be continuously written until the end of the scratchpad is reached or until the DS1991 is reset. The command sequence is shown in Figure 5, first page, left column. 4.5.2 Read Scratchpad [69H] The Read Scratchpad command is used to retrieve data from the scratchpad. The starting address is specified in the command word. Data can be continuously read until the end of the scratchpad is reached or until the DS1991 is reset. The command sequence is shown in Figure 5, first page, center column. 4.5.3 Copy Scratchpad [3CH] The Copy Scratchpad command is used to transfer specified data blocks from the scratchpad to a selected subkey. This command should be used when data verification is required before storage in a secure subkey. Data can be transferred in single 8-byte blocks or in one large 64-byte block. There are nine valid block selector codes that are used to specify which block is to be transferred (Figure 6). As a further precaution against accidental erasure of secure data, the 8-byte password of the destination subkey must be entered. If the password does not match, the operation is terminated. After the block of data is transferred to the secure subkey, the original data in the corresponding block of the scratchpad is erased. The command sequence is shown in Figure 5, first page, right column. 4.5.4 Write Password [5AH] The Write Password command is used to enter the ID and password of the selected subkey. This command will erase all of the data stored in the secure area as well as overwriting the ID and password fields with the new data. The DS1991 has a built-in check to ensure that the proper subkey was selected. The sequence begins by reading the ID field of the selected subkey; the ID of the subkey to be changed is then written into the part. If the IDs do not match, the sequence is terminated. Otherwise, the subkey contents are erased and 64 bits of new ID data are written followed by a new 64-bit password. The command sequence is shown in Figure 5, 2nd page, right column. 4.5.5 Write SubKey [99H] The Write Subkey command is used to enter data into the selected subkey. Since the subkeys are secure, the correct password is required to access them. The sequence begins by reading the ID field; the password is then written back. If the password is incorrect, the transaction is terminated. Otherwise, the data following is written into the secure area. The starting address for the write sequence is specified in the command word. Data can be continuously written until the end of the secure subkey is reached or until the DS1991 is reset. The command sequence is shown in Figure 5, 2nd page, center column. 4.5.6 Read SubKey [66H] The Read Subkey command is used to retrieve data from the selected subkey. Since the subkeys are secure, the correct password is required to access them. The sequence begins by reading the ID field; the password is then written back. If the password is incorrect, the DS1991 will transmit random data. Otherwise the data can be read from the subkey. The starting address is specified in the command. Data can be continuously read until the end of the subkey is reached or until the DS1991 is reset. The command sequence is shown in Figure 5, 2nd page, left column.

4.5.7 Read ROM [33H] This command allows the bus master to read the DS1991s 8-bit family code, unique 48-bit serial number and 8-bit CRC. This command should only be used if there is a single DS1991 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number read by the master will be invalid. 4.5.8 Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1991 on a multidrop bus. Only the DS1991 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 4.5.9 Skip ROM [CCH] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain will produce a wired-AND result). 4.5.10 Search ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. Additional passes will identify the ROM codes of the remaining devices.. 4.5.11 TRANSACTION SEQUENCE The protocol for accessing the DS1991 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory or SHA Function Command _ Transaction/Data 4.6 DS1992 /3 4.,6.1 Write Scratchpad Command [0Fh] After issuing the write scratchpad command, the user must first provide the 2-Byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4:E0) is the Byte offset at which the host stops writing data. The maximum ending offset is 11111b (31d). If the host attempts to write data past this maximum offset, the overflow flag (OF) is set and the remaining data is ignored. If the user writes an incomplete Byte and an overflow has not occurred, the partial Byte flag (PF) is set. 4.6.2 Read Scratchpad Command [AAh] This command can be used to verify scratchpad data and target address. After issuing the read scratchpad command, the user can begin reading. The first two Bytes are the target address. The next Byte is the ending offset/data status Byte (E/S) followed by the scratchpad data beginning at the Byte offset (T4: T0). The user can read data until the end of the scratchpad, after which the data read is all logic 1s. 4.6.3 Copy Scratchpad [55h] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the user must provide a 3-byte authorization pattern. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag is set and the copy begins. A logic 0 is transmitted after the data has been copied until the user issues a reset pulse. Any attempt to reset the part is ignored while the copy

is in progress. Copy typically takes 30_s. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset is copied to memory, starting at the target address. Anywhere from 1 to 32 Bytes can be copied to memory with this command. Whole Bytes are copied even if only partially written. The AA flag is cleared only by executing a write scratchpad command. 4.6.4 Read Memory [F0h] The read memory command can be used to read the entire memory. After issuing the command, the user must provide the 2-Byte target address. After the two Bytes, the user reads data beginning from the target address and may continue until the end of memory, at which point logic 1s are read. It is important to realize that the target address registers contains the address provided. The ending offset/data status Byte is unaffected. The hardware of the DS1992/DS1993 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See Application Note 114 for the recommended file structure to be used with the 1-Wire environment.) 4.6.5 Read ROM [33h] This command allows the bus master to read the DS199_s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if there is a single DS199_ on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number usually result in a mismatch of the CRC. 4.6.6 Match ROM [55h] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS199_ on a multidrop bus. Only the DS199_ that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64-bit ROM sequence wait for a reset pulse. This command can be used with single or multiple devices on the bus. 4.6.7 Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). 4.6.8 Search ROM [F0h] When a system is initially brought up, the bus master may not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify the ROM codes of the remaining devices. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 4.6.9 TRANSACTION SEQUENCE The protocol for accessing the DS199_ through the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Transaction/Data

4.7 DS1993 /4 4.7.1 Write Scratchpad Command [0Fh] After issuing the write scratchpad command, the user must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the host stops writing data. The maximum ending offset is 11111b (31d). If the host attempts to write data past this maximum offset, the overflow flag (OF) will be set and the remaining data will be ignored. If the user writes an incomplete byte and an overflow has not occurred, the partial byte flag (PF) will be set. 4.7.2 Read Scratchpad Command [AAh] This command may be used to verify scratchpad data and target address. After issuing the read scratchpad command, the user may begin reading. The first two bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4: T0). The user may read data until the end of the scratchpad after which the data read will be all logic 1s. 4.7.3 Copy Scratchpad [55h] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the user must provide a 3-byte authorization pattern. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin. A logic 0 will be transmitted after the data has been copied until a reset pulse is issued by the user. Any attempt to reset the part will be ignored while the copy is in progress. Copy typically takes 30 ms. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset, will be copied to memory, starting at the target address. Anywhere from 1 to 32 bytes may be copied to memory with this command. Whole bytes are copied even if only partially written. The AA flag will be cleared only by executing a write scratchpad command. 4.7.4 Read Memory [F0h] The read memory command may be used to read the entire memory. After issuing the command, the user must provide the 2-byte target address. After the two bytes, the user reads data beginning from the target address and may continue until the end of memory, at which point logic 1s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS1992/DS1993/DS1994 provides a means to accomplish errorfree writing to the memory section. To safeguard reading data in the 1Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16bit CRC with each page of data to ensure rapid, errorfree data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See the Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1Wire environment.) 4.7.5 Read ROM [33h] This command allows the bus master to read the DS199Xs 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS199X on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48bit serial number will usually result in a mismatch of the CRC. 4.7.6 Match ROM [55h] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS199X on a multidrop bus. Only the DS199X that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 4.7.7 Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus

and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-AND result). 4.7.8 Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1 Wire bus or their 64bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 4.7.9 Search Interrupt [ECh] (DS1994) This ROM command works exactly as the normal ROM Search, but it will identify only devices with interrupts that have not yet been acknowledged. 4.7.10 TRANSACTION SEQUENCE The protocol for accessing the DS199X via the 1-wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Transaction/Data 4.8 DS1995 /6 4.8.1 Write Scratchpad Command [0FH] After issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the bus master has stopped writing data. 4.8.2 Read Scratchpad Command [AAH] This command is used to verify scratchpad data and target address. After issuing the read scratchpad command, the master begins reading. The first two bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4: T0). The master may read data until the end of the scratchpad after which the data read will be all logic 1s. 4.8.3 Copy Scratchpad [55H] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern which is obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin. A logic 0 will be transmitted after the data has been copied until a reset pulse is issued by the master. Any attempt to reset the part will be ignored while the copy is in progress. Copy typically takes 30 s. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset, will be copied to memory, starting at the target address. Anywhere from 1 to 32 bytes may be copied to memory with this command. Whole bytes are copied even if only partially written. The AA flag will be cleared only by executing a write scratchpad command. 4.8.4 Read Memory [F0H] The read memory command may be used to read the entire memory. After issuing the command, the master must provide the 2-byte target address. After the two bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS1996 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to

simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See the Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-Wire environment.) 4.8.5 Read ROM [33H] This command allows the bus master to read the DS1996s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1996 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will usually result in a mismatch of the CRC. 4.8.6 Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1996 on a multidrop bus. Only the DS1996 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 4.8.7 Skip ROM [CCH] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wiredAND result). 4.8.8 Search ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 4.8.9 Overdrive Skip ROM [3CH] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive Skip ROM sets the DS1996 in the Overdrive Mode (OD=1). All communication following this command has to occur at Overdrive Speed until a reset pulse of minimum 480 s duration resets all devices on the bus to regular speed (OD=0). When issued on a multidrop bus this command will set all Overdrivecapable devices into Overdrive mode. To subsequently address a specific Overdrive-capable device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will shorten the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). 4.8.10 Overdrive Match ROM [69H] The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive Speed, allows the bus master to address a specific DS1996 on a multidrop bus and to simultaneously set it in Overdrive Mode. Only the DS1996 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive Skip or Match command will remain in Overdrive mode. All other slaves that do not match the 64-bit ROM sequence or do not support Overdrive will return to or remain at regular speed and wait for a reset pulse of minimum 480 s duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus.

4.8.11 TRANSACTION SEQUENCE The protocol for accessing the DS1996 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Transaction/Data