Email: project@tripleninfotech.

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IEEE 2013-2014 PROJECTS TITLES VLSI

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PROJECT TITLE Distance Analysis Of ATM And Cyber Security in Financial Sector Using FPGA Implementation Mobile Avoidance For Safe Driving using Field Programmable Gate Array Advanced Rescue system for industrial monitoring using Zigbee, GSM and FPGA Design of ETC Violation Enforcement System for Non-payment Vehicle Searching using FPGA Advanced Terminal Founding And New Passport Security System Using Passive RF Control For Carbon Monoxide Leakage,Multi-sensor tracking and lane estimation in highly automated vehicles Anti-Theft and smart Car control system Using Multi Media Service Design Of Milk Analysis Embedded System For Dairy Farmers using FPGA Solid Waste Management control system through zigbee And FPGA Multi-Function System Through Hand Fly Signal And Control Of FPGA The Monitoring System of Smoke Images Based on Embedded System and GPRS Human Health Monitoring mobile Phone Application By Using The wireless nano sensor based System Passenger Alert System And Advanced Control Over Existing System Using MMS Response Surface Method In-Cooperating Embedded System For Bus Route Optimization Hardwareefficient path planning for a mobile robot and FPGA realization RFID based Navigation System for Unmanned Material Handling Vehicles using FPGA Tracking System, Preventing Trees Extinction and Deforestation Using RF and FPGA A Zigbee SMS Alert System With Trust Mechanism In Wireless Sensor Networks
Triple N Infotech No 33 (Old No 14/1), 1st Floor, T.Nagar, Chennai-17 Ph: 044-42868371, Mob: 9566234284 www.tripleninfotech.com

Email: project@tripleninfotech.com
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Indoor Localization System based on Fingerprint Technique using RFID Passive Tag A Directional-Edge-Based Real-Time Object Tracking System Employing Multiple Candidate-Location Generation Building Control, Monitoring, Safety and Security using Collaborative Systems Extended Wireless Monitoring through Intelligent Hybrid Energy Supply Passenger BUS Alert System for Easy Navigation of Blind Wireless Technologies for Distributed Sensor Networks Used in Measurement and Automation Systems Migration From Legacy Wireless Technology to Zigbee For Home Automation FPGA Based Tracking System For Railways Transportation Tourist Management ,Monitoring and Control System using Wireless Communication. FPGA-based Modern Sailing Robot RFID Library Management System And Control Through Alert Signal. Realization of Intelligent Traffic Light Monitor and Control System Based on Wireless Control Authentication and Authorization Technique For Smart Card System Speech Recognition Based Wireless Automation Of Home Loads With Fault Identification For Physically Challenged The design and implementation of fire smoke detection system based on FPGA Improve quality of care with remote activity and fall detection using ultrasonic sensors Intelligent wireless communication devices for efficient data transfer and machine control Web-based Student Attendance System using RFID Technology Design and implementation of Direct Torque Control of Induction Machine on FPGA Design and energetic analysis of an advanced control existing lighting systems Analysis of an Indoor Biomedical Radar-Based System for Health Monitoring

Triple N Infotech No 33 (Old No 14/1), 1st Floor, T.Nagar, Chennai-17 Ph: 044-42868371, Mob: 9566234284 www.tripleninfotech.com

Email: project@tripleninfotech.com
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A Wireless Irradiance-Temperature-Humidity Sensor for Photovoltaic Plant Monitoring Applications Dual Edge triggered Sense-Amplifier Flip Flop For Low Power systems Folding ADC with Nano metric Compatible Architecture by Using a High Dynamic Input/output Folding Amplifier A CMOS Magnitude/Phase Measurement Chip for Impedance Spectroscopy A Low Power CMOS Voltage Mode SRAM Cell for High Speed VLSI Design A Low Power Discreet Time Sigma Delta Modulator in 50nm CMOS A Low-Power Dual-Mode Continuous-Time Delta-Sigma Modulator with a A Low-Power, Area Efficient Design for Wide Fan-in Domino Logic based Folded Quantizer Comparators An 18.7mW 10-GHz Phase-Locked Loop Circuit in 0.13-m CMOS A Sub-1V 32nA Process, Voltage and Temperature Invariant Voltage Reference Circuit Average-8T Differential-Sensing Sub threshold SRAM With Bit Interleaving and 1k Bits Per Bit line Comparative Study & Analysis 0132nm FD-SOI/SON and CNFET based 4x4 SRAM Cell Array Defect-Oriented Non-Intrusive RF Test Using On-Chip Temperature Sensors Design and Implementation of a High-Speed, Power-Efficient, Modified HybridMode Sense Amplifier for SRAM Applications Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in Efficiency of Oscillation-based BIST in 90nm CMOS Active Analogy Filters 40-nm CMOS Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive ChargeRecovery Logic Reconfigurable low power noise Amplifier Using MEMS Varactor Stochastic degradation modelling and simulation for analog integrated circuits in nano meter CMOS Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors Self controllable voltage level circuit for low level power, High speed 7T SRAM cell

Triple N Infotech No 33 (Old No 14/1), 1st Floor, T.Nagar, Chennai-17 Ph: 044-42868371, Mob: 9566234284 www.tripleninfotech.com

Email: project@tripleninfotech.com

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Optical Receiver Using Noise Cancelling With an Integrated Photodiode in 40 nm CMOS Technology Hardware Hardware Implementations of efficiency comparison of AES A Secure Software Implementation of Nonlinear AES S-Box with the Enhancement of Biometrics. An efficient FPGA implementation of the Advanced Encryption Standard algorithm. Low Power FPGA Implementation of Digital FIR Filter Based on Low Power Multiplexer Base Shift/Add Multiplier. Design and Implementation of Area-optimized AES Based on FPGA. Construction of Optimum Composite Field Architecture for Compact HighThroughput AES S-Boxes. Scalable 128-bit AES-CM Crypto-Core Reconfigurable Implementation for Secure Communications Advanced FPGA Design of A Novel low power fir filter. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm. VLSI Design and Implementation of Low Power MAC for Digital FIR Filter. Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation. A Reconfigurable FIR Filter Architecture to Trade off Filter Performance for Dynamic Power Consumption FPGA Design and Implementation of Vedic multiplier. Design of Area and Speed wise superior Vedic multiplier for FPGA based arithmetic circuits. FPGA Design of High Speed and Area Efficient Vedic Multiplier New Recongurable Architectures for Implementing FIR Filters with Low Complexity. Vedic Mathematics for Fast Multiplication in DSP applications. Advanced FPGA Design for 32-bit MAC unit using Vedic multiplier.

Triple N Infotech No 33 (Old No 14/1), 1st Floor, T.Nagar, Chennai-17 Ph: 044-42868371, Mob: 9566234284 www.tripleninfotech.com

Email: project@tripleninfotech.com
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Design and Analysis of Low Power Multipliers and 4:2 Compressor Using Adiabatic Logic. VLSI Design of Testable Reversible Sequential Circuits. Performance Analysis of Sequential Circuits using reversible logic. An Optimized Design of Reversible Sequential Digital Circuits. Design of Asynchronous Sequential Circuits using Reversible Logic Gates. Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation. High Performance DCT Implementation Using Reduced Complexity Wallace Multiplier. High performance DADDA Multiplier implementation using high speed carry select adder. VLSI Design of Wallace Tree Multiplier by Sklansky Adder. Improvement of Wallace multipliers using Parallel prefix adders. FPGA Design Of 128 Bit Low Power and Area Efficient Carry Select Adder. Carry Bypass & Carry Select Adder Using Reversible Logic Gates. A Scalable Memory-Based Reconfigurable Computing Framework for Nano scale Crossbar. Hardware-Efficient Low-Power Image Processing System for Wireless Capsule Endoscopy. VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing. A High-Speed Low-Complexity Modified Radix-25 FFT Processor for High Rate WPAN Applications.

Triple N Infotech No 33 (Old No 14/1), 1st Floor, T.Nagar, Chennai-17 Ph: 044-42868371, Mob: 9566234284 www.tripleninfotech.com