EE 42/43/100 Introduction to Digital Electronics

Lecture 19 8/7/13 Instructors: Prof. Connie Chang-Hasnain Dr. Wenbin Hsu

Lecture 19
More on MOSFET and Regions of Operation CMOS Logic Gates
Combinational circuits Sequential circuits

Integrated Circuit Fabrication Process

I-V and Regions of Operation

iD

v= vGS Vt 0 DS
Triode region Saturation region

Cutoff

vDS

Example 1
Compute W /L of M 1 such that the device operates at the edge of saturation.
KP = 200 A/V 2 Vt 0 = 0.4V

1 0.4 = 0.6 M 1 at the edge of saturation vDS = vGS Vt 0 = iD = 1.8 vDS 1.8 0.6 = = 1.2mA 1k 1k W KP 2 iD = K ( vGS Vt 0 ) = ( ) (1 0.4) 2 L 2 W KP 200= = A/V 2 0.2mA/V 2 = 33 L

Example 2
Using the value of W /L=33, what happens if KP is doubled due to a manufacturing error?
KP = 400 A/V 2 Vt 0 = 0.4V As KP iD vDS M 1 will be in triode region. 0.4mA/V 2 W KP K= ( ) 33 6.6mA/V 2 = = 2 L 2

1.8 vDS = 1.8 vDS 1k iD (mA) = K [2( vGS Vt 0 )vDS vDS 2 ] = 6.6 [2 0.6 vDS vDS 2 ] = 7.92vDS 6.6vDS 2 iD (mA) =
2 v v 1.8 v= 7.92 6.6 DS DS DS

v = = 0.247V vGS V 0.6V (M 1 is indeed in triode) DS t0 iD (mA) =1.8 vDS =1.553mA

Example 3
(W /L)1 =10/0.18, I D1 = 0.5mA,
KP = 200 A/V 2 Vt 0 = 0.4V

determine (W /L) 2 such that M 1 operates at the edge of saturation.

M 1 at the edge of saturation Vout = Vin 0.4 (1) 0.5mA = K1 (Vin 0.4) 2 (2) M 2 in saturation 0.5mA = K 2 (1.8 Vout 0.4) 2 (3)

K1 = (W /L)1 ( KP / 2) = From (2), Vin

10 0.2 = 5.56mA/V 2 0.18 2 0.7V From (1), Vout 0.3V =

2 From (3), K 2 0.413mA/V (W /L) 2 ( KP / 2) = =

(W /L) 2 0.413 / 0.1 4.13 = =

Design Abstraction in Digital Circuits

Combinational Circuits
Combinations of gates implement Boolean functions.

Combinational logic circuits produce a specified output at the instant when input values are applied. The three simplest gates are NOT, NAND, and NOR.

An NMOS Inverter
VDD RD iD + + vIN vDS = vOUT

vOUT VDD

VOL 0 VT VDD

vIN

When v IN V= vDS is low. The transistor is in triode. = DD , vout VDD vDS iD = = K [2( vGS Vt 0 )vDS vDS 2 ] RD VDD VOL = K [2(VDD Vt 0 )VOL VOL 2 ] RD VOL ( RD ); VOL ( K ); VOL (W /L)

Disadvantages of NMOS Logic Gates

VOL depends on the relative sizes of RD and the transistor. Large values of RD are required in order to
achieve a low value of VOL keep power consumption low

But large resistors take up lots of space.

CMOS Inverter

Vin

Vout

Vin high

Vin low

Voltage Transfer Characteristic

Vout VDD
N: off P: tri N: sat P: tri N: sat P: sat

D
N: tri P: sat

0 0

N: tri P: off

VDD

Vin

Features of CMOS Digital Circuits

The output is always connected to VDD or GND in steady state.
Full logic swing; large noise margins Logic levels are not dependent upon the relative sizes of the devices ("ratioless")

There is no direct path between VDD and GND in steady state.

no static power dissipation

Current Flow During Switching

VOUT
V DD N: sat P: sat

VDD
G S D

N: off P: lin N: sat P: lin

VIN
G

i
D S

VOUT

D
N: lin P: sat

0 0

N: lin P: off

VDD

VIN

Inverter Switching Threshold Voltage

Vout = f (Vin ) Nominal voltages VOH = f (VOL ) VOL = f (VOH ) 1 VOH 0 VOL VOH = high logic level VOL = low logic level Switching threshold voltage VM = f (VM )

VIH and VIL

The regions of acceptable high and low voltages delimited by the VIH and VIL

Noise Margins

NM H = noise margin high NM L = noise margin low

CMOS NAND Gate

CMOS NAND Gate

A Low Low High High

B Low High Low High

Vout High High High Low

CMOS NOR Gate

CMOS NOR Gate

A Low Low High High

B Low High Low High

Vout High Low Low Low

Exclusive OR (XOR)
A B AB
AB 0 1 1 0

A 0 0

B 0 1 0 1

A AB B

1 1

Full Adder
X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Carry-in 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1 Carry-out 0 0 0 1 0 1 1 1

Full Adder

X Y

Sum

Carry In Carry Out

Sequential Circuits
Combinational logic circuits provide immediate evaluation of a Boolean function to a set of inputs. There are situations when we need a circuit to change its value with the consideration of its current state and its inputs.
A counter An accumulator

Sequential logic circuits provide this functionality by using various flip-flops.

SR Flip-Flop

Use positive feedback to create a bistable circuit.

JK Flip-Flop

Clocked JK Flip-Flop

Clocked D Flip-Flop

D 1 0

Q(t+1) 1 0

4-bit Register

Fan-In and Fan-Out

Increasing the fan-in can result in inferior static and dynamic properties due to complexity.

Increasing the fan-out of a gate can affect its logic output levels.

Propagation Delay and Rise / Fall Time

Digital circuit design must take into consideration of the physical behaviors of circuits to include propagation delays between when a circuit's inputs are available and when the output is accurate and stable.

Integrated Circuits (IC) and Wafer

Basic IC Fabrication Processes

Deposition - Atoms (or molecules) accumulate on the surface in thin films.
CVD, sputtering, MBE

Etching - Removal of silicon (or other material) from the surface.

Dry etch, wet etch

Implantation - High-energy ions are driven into the silicon.

Lithography
Lithography - Defining spatial pattern Photoresist - Polymer material that does not allow etching or deposition of areas underneath it.

Process in Defined Area

Fabrication of PN Junction