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Sai charan malineni


Operational Amplifiers:
The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MH Z to which feedback is added to control its overall response characteristic i.e. gain and bandwidth. The op-amp exhibits the gain down to zero frequency. Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass) capacitors since these would reduce the amplification to zero at zero frequency. Large by pass capacitors may be used but it is not possible to fabricate large capacitors on a IC chip. The capacitors fabricated are usually less than 20 pf. Transistor, diodes and resistors are also fabricated on the same chip.

Differential Amplifiers:
Differential amplifier is a basic building block of an op-amp. The function of a differential amplifier is to amplify the difference between two input signals.

How the differential amplifier is developed? Let us consider two emitter-biased circuits as shown in fig.1

Fig. 1 The two transistors Q1 and Q2 have identical characteristics. The resistances of the circuits are equal, i.e. R E1 = R E2, RC1 = R C2 and the magnitude of +VCC is equal to the magnitude of VEE. These voltages are measured with respect to ground. To make a differential amplifier, the two circuits are connected as shown in fig. 1. The two +VCC and VEE supply terminals are made common because they are same. The two emitters are also connected and the parallel combination of RE1 and RE2 is replaced by a resistance RE. The two input signals v1 & v2 are applied at the base of Q1


and at the base of Q2. The output voltage is taken between two collectors. The collector resistances are equal and therefore denoted by RC = RC1 = RC2. Ideally, the output voltage is zero when the two inputs are equal. When v 1 is greater then v2 the output voltage with the polarity shown appears. When v1 is less than v2, the output voltage has the opposite polarity. The differential amplifiers are of different configurations. The four differential amplifier configurations are following: 1. 2. 3. 4. Dual input, balanced output differential amplifier. Dual input, unbalanced output differential amplifier. Single input balanced output differential amplifier. Single input unbalanced output differential amplifier.

Fig. 2 These configurations are shown in fig. 2, and are defined by number of input signals used and the way an output voltage is measured. If use two input signals, the configuration is said to be dual input, otherwise it is a single input configuration. On the other hand, if the output voltage is measured between two collectors, it is referred to as a balanced output because both the collectors are at the same dc potential w.r.t. ground. If the output is measured at one of the collectors w.r.t. ground, the configuration is called an unbalanced output. A multistage amplifier with a desired gain can be obtained using direct connection between successive stages of differential amplifiers. The advantage of direct coupling is that it removes the lower cut off frequency imposed by the coupling capacitors, and they are therefore, capable of amplifying dc as well as ac input signals.

Dual Input, Balanced Output Differential Amplifier:

The circuit is shown in fig. 1, v1 and v2 are the two inputs, applied to the bases of Q1 and Q2 transistors. The output voltage is measured between the two collectors C1 and C2 , which are at same dc potentials.


D.C. Analysis:

To obtain the operating point (ICC and VCEQ) for differential amplifier dc equivalent circuit is drawn by reducing the input voltages v1 and v2 to zero as shown in fig. 3.


The internal resistances of the input signals are denoted by RS because RS1= RS2. Since both emitter biased sections of the different amplifier are symmetrical in all respects, therefore, the operating point for only one section need to be determined. The same values of ICQ and VCEQ can be used for second transistor Q2.


Applying KVL to the base emitter loop of the transistor Q1.

The value of RE sets up the emitter current in transistors Q1 and Q2 for a given value of VEE. The emitter current in Q1 and Q2 are independent of collector resistance RC. The voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop across R is negligible. Knowing the value of IC the voltage at the collector VCis given by VC =VCC IC RC and VCE = VC VE = VCC IC RC + VBE VCE = VCC + VBE ICRC (E-2)

From the two equations VCEQ and ICQ can be determined. This dc analysis applicable for all types of differential amplifier.

Example - 1
The following specifications are given for the dual input, balanced-output differential amplifier of fig.1: RC = 2.2 k, RB = 4.7 k, Rin 1 = Rin 2 = 50 , +VCC = 10V, -VEE = -10 V, dc =100 and VBE = 0.715V. Determine the operating points (ICQ and VCEQ) of the two transistors. Solution: The value of ICQ can be obtained from equation (E-1).

The voltage VCEQ can be obtained from equation (E-2).


The values of ICQ and VCEQ are same for both the transistors.

Dual Input, Balanced Output Difference Amplifier:

The circuit is shown in fig. 4 v1 and v2 are the two inputs, applied to the bases of Q1 and Q2 transistors. The output voltage is measured between the two collectors C1 and C2, which are at same dc potentials.

Fig. 4

A.C. Analysis :
In previous lecture dc analysis has been done to obtain the operatiing point of the two transistors. To find the voltage gain Ad and the input resistance Ri of the differential amplifier, the ac equivalent circuit is drawn using r-parameters as shown in fig.5 . The dc voltages are reduced to zero and the ac equivalent of CE configuration is used.


Fig. 5 Since the two dc emitter currents are equal. Therefore, resistance r'e1 and r'e2 are also equal and designated by r'e . This voltage across each collector resistance is shown 180 out of phase with respect to the input voltages v 1 and v2. This is same as in CE configuration. The polarity of the output voltage is shown in Figure. The collector C 2 is assumed to be more positive with respect to collector C1 even though both are negative with respect to to ground. Applying KVL in two loops 1 & 2.

Substituting current relations,

Again, assuming RS1 / and RS2 / are very small in comparison with RE and re' and therefore neglecting these terms,

Solving these two equations, ie1 and ie2 can be calculated.


The output voltage VO is given by VO = VC2 - VC1 = -RC iC2 - (-RC iC1) = RC (iC1 - iC2) = RC (ie1 - ie2) Substituting ie1, & ie2 in the above expression

Thus a differential amplifier amplifies the difference between two input signals. Defining the difference of input signals as vd = v1 v2 the voltage gain of the dual input balanced output differential amplifier can be given by

Differential Input Resistance:
Differential input resistance is defined as the equivalent resistance that would be measured at either input terminal with the other terminal grounded. This means that the input resistance Ri1 seen from the input signal source v1 is determined with the signal source v2 set at zero. Similarly, the input signal v1 is set at zero to determine the input resistance Ri2 seen from the input signal source v2. Resistance RS1 and RS2 are ignored because they are very small.

Substituting ie1,



The factor of 2 arises because the re' of each transistor is in series. To get very high input impedance with differential amplifier is to use Darlington transistors. Another ways is to use FET.

Output Resistance:
Output resistance is defined as the equivalent resistance that would be measured at output terminal with respect to ground. Therefore, the output resistance RO1 measured between collector C1 and ground is equal to that of the collector resistance RC. Similarly the output resistance RO2 measured at C2 with respect to ground is equal to that of the collector resistor RC. RO1 = RO2 = RC (E-5)

The current gain of the differential amplifier is undefined. Like CE amplifier the differential amplifier is a small signal amplifier. It is generally used as a voltage amplifier and not as current or power amplifier.
Example - 1
The following specifications are given for the dual input, balanced-output differential amplifier: RC = 2.2 k, RB = 4.7 k, Rin 1 = Rin 2 = 50, +VCC= 10V, -VEE = -10 V, dc =100 and VBE = 0.715V. a. b. c. Solution: (a). The parameters of the amplifiers are same as discussed in example-1 of lecture-1. The operating point of the two transistors obtained in lecture-1 are given below ICQ = 0.988 mA VCEQ=8.54V Determine the voltage gain. Determine the input resistance Determine the output resistance.


The ac emitter resistance

Therefore, substituting the known values in voltage gain equation (E-2), we obtain

b). The input resistance seen from each input source is given by (E-3) and (E-4):

(c) The output resistance seen looking back into the circuit from each of the two output terminals is given by (E-5) Ro1 = Ro2 = 2.2 k

Example - 2
For the dual input, balanced output differential amplifier of Example-1: a. b. Solution: (a) In Example-1 we have determined the voltage gain of the dual input, balanced output differential amplifier. Substituting this voltage gain (Ad = 86.96) and given values of input voltages in (E-1), we get Determine the output voltage (vo) if vin 1 = 50mV peak to peak (pp) at 1 kHz and vin 2 = 20 mV pp at 1 kHz. What is the maximum peal to peak output voltage without clipping?

(b) Note that in case of dual input, balanced output difference amplifier, the output voltage v o is measured across the collector. Therefore, to calculate the maximum peak to peak output voltage, we need to determine the voltage drop across each collector resistor:

Substituting IC = ICQ = 0.988 mA, we get

This means that the maximum change in voltage across each collector resistor is 2.17 (ideally) or 4.34 VPP. In other words, the maximum peak to peak output voltage without clipping is (2) (4.34) = 8.68 VPP.

A dual input, balanced output difference amplifier circuit is shown in fig.6 .

Fig. 6

Inverting & Non inverting Inputs:

In differential amplifier the output voltage vO is given by VO = Ad (v1 v2) When v2 = 0, vO = Ad v1 & when v1 = 0, vO = - Ad v2 Therefore the input voltage v1 is called the non inventing input because a positive voltage v1 acting alone produces a positive output voltage vO. Similarly, the positive voltage v2 acting alone produces a negative output voltage hence v2 is called inverting input. Consequently B1 is called noninverting input terminal and B2 is called inverting input terminal.

Common mode Gain:

A common mode signal is one that drives both inputs of a differential amplifier equally. The common mode signal is interference, static and other kinds of undesirable pickup etc. The connecting wires on the input bases act like small antennas. If a differential amplifier is operating in an environment with lot of electromagnetic interference, each base picks up an unwanted interference voltage. If both the transistors were matched in all respects then the balanced output would be theoretically zero. This is the important characteristic of a differential amplifier. It discriminates against common mode input signals. In other words, it refuses to amplify the common mode signals. The practical effectiveness of rejecting the common signal depends on the degree of matching between the two CE stages forming the differential amplifier. In other words, more closely are the currents in the input transistors, the better is the common mode signal rejection e.g. If v1 and v2 are the two input signals, then the output of a practical op-amp cannot be described by simply v0 = Ad (v1 v2 ) In practical differential amplifier, the output depends not only on difference signal but also upon the common mode signal (average).


vd = (v1 vd ) and vC =

(v1 + v2 )

The output voltage, therefore can be expressed as vO = A1 v1 + A2 v2 Where A1 & A2 are the voltage amplification from input 1(2) to output under the condition that input 2 (1) is grounded.

The voltage gain for the difference signal is Ad and for the common mode signal is AC. The ability of a differential amplifier to reject a common mode signal is expressed by its common mode rejection ratio (CMRR). It is the ratio of differential gain Ad to the common mode gain AC.

Date sheet always specify CMRR in decibels CMRR = 20 log CMRR. Therefore, the differential amplifier should be designed so that is large compared with the ratio of the common mode signal to the difference signal. If = 1000, vC = 1mV, vd = 1 V, then

It is equal to first term. Hence for an amplifier with = 1000, a 1 V difference of potential between two inputs gives the same output as 1mV signal applied with the same polarity to both inputs.
Dual Input, Unbalanced Output Differential Amplifier:
In this case, two input signals are given however the output is measured at only one of the two-collector w.r.t. ground as shown in fig.7. The output is referred to as an unbalanced output because the collector at which the output voltage is measured is at some finite dc potential with respect to ground..


Fig. 7 In other words, there is some dc voltage at the output terminal without any input signal applied. DC analysis is exactly same as that of first case.

AC Analysis:
The output voltage gain in this case is given by

The voltage gain is half the gain of the dual input, balanced output differential amplifier. Since at the output there is a dc error voltage, therefore, to reduce the voltage to zero, this configuration is normally followed by a level translator circuit.

Differential amplifier with swamping resistors:

By using external resistors R'E in series with each emitter, the dependence of voltage gain on variations of r'e can be reduced. It also increases the linearity range of the differential amplifier. Fig. 8, shows the differential amplifier with swamping resistor R'E. The value of R'E is usually large enough to swamp the effect of r'e.


Fig. 8

Consider example-1 of lecture-2. The specifications are given again for the dual input, unbalanced-output differential amplifier: RC = 2.2 k, RB= 4.7 k, Rin1 = Rin2= 50, +VCC = 10V, -VEE= -10 V, dc =100 and VBE= 0.715V. Determine the voltage gain, input resistance and the output resistance. Solution: Since the component values remain unchanged and the biasing arrangement is same, the ICQ and VCEQ values as well as input and output resistance values for the dual input, unbalanced output configuration must be the same as those for the dual input, balanced output configuration. Thus, ICQ = 0.988 mA VCEQ = 8.54 V


Ri1 = Ri2 = 5.06 k Ro = 2.2 k The voltage gain of the dual input, unbalanced output differential amplifier is given by

Repeat Example-1 for single input, balanced output differential amplifier. Solution: Because the same biasing arrangement and same component values are used in both configurations, the results obtained in Example-1 for the dual input, balanced output configuration are also valid for the single input, balanced output configuration. That is,

ICQ= 0.988 mA VCEQ = 8.54 V Vd = 86.96 Ri = 5.06 k Ro1 = Ro2 = 2.2 k

Constant Current Bias:
In the dc analysis of differential amplifier, we have seen that the emitter current I E depends upon the value of dc. To make operating point stable IE current should be constant irrespective value of dc. For constant IE, RE should be very large. This also increases the value of CMRR but if R E value is increased to very large value, IE (quiescent operating current) decreases. To maintain same value of I E, the emitter supply VEE must be increased. To get very high value of resistance RE and constant IE, current, current bias is used.


Figure 9 Fig. 9, shows the dual input balanced output differential amplifier using a constant current bias. The resistance R E is replace by constant current transistor Q3. The dc collector current in Q3 is established by R1, R2, & RE. Applying the voltage divider rule, the voltage at the base of Q3 is

Because the two halves of the differential amplifiers are symmetrical, each has half of the current IC3.

The collector current, IC3 in transistor Q3 is fixed because no signal is injected into either the emitter or the base of Q 3.


Besides supplying constant emitter current, the constant current bias also provides a very high source resistance since the ac equivalent or the dc source is ideally an open circuit. Therefore, all the performance equations obtained for differential amplifier using emitter bias are also valid. As seen in IE expressions, the current depends upon VBE3. If temperature changes, VBE changes and current IE also changes. To improve thermal stability, a diode is placed in series with resistance R 1as shown in fig.10.

Fig. 10 This helps to hold the current IE3 constant even though the temperature changes. Applying KVL to the base circuit of Q3.

Therefore, the current IE3 is constant and independent of temperature because of the added diode D. Without D the current would vary with temperature because VBE3 decreases approximately by 2mV/ C. The diode has same temperature dependence and hence the two variations cancel each other and IE3 does not vary appreciably with temperature. Since the cut in voltage VD of diode approximately the same value as the base to emitter voltage VBE3 of a transistor the above condition cannot be satisfied with one diode. Hence two diodes are used in series for VD. In this case the common mode gain reduces to zero.


Biasing of Differential Amplifiers

Some times zener diode may be used in place of diodes and resistance as shown in fig. 11. Zeners are available over a wide range of voltages and can have matching temperature coefficient The voltage at the base of transistor QB is

Fig. 11 The value of R2 is selected so that I2 1.2 IZ(min) where IZ is the minimum current required to cause the zener diode to conduct in the reverse region, that is to block the rated voltage V Z.

Current Mirror:
The circuit in which the output current is forced to equal the input current is said to be a current mirror circuit. Thus in a current mirror circuit, the output current is a mirror image of the input current. The current mirror circuit is shown in fig. 12.

Fig. 12 Once the current I2 is set up, the current IC3 is automatically established to be nearly equal to I2. The current mirror is a special case of constant current bias and the current mirror bias requires of constant current bias and therefore can be used to set up currents in differential amplifier stages. The current mirror bias requires fewer components than


constant current bias circuits. Since Q3 and Q4 are identical transistors the current and voltage are approximately same

For satisfactory operation two identical transistors are necessary.

Example - 1

Design a zener constant current bias circuit as shown in fig. 13 according to the following specifications. (a). Emitter current -IE = 5 mA (b). Zener diode with Vz = 4.7 V and Iz = 53 mA. (c). ac = dc = 100, VBE = 0.715V (d). Supply voltage - VEE = - 9 V. Solution: From fig. 14 using KVL we get

Fig. 13


Practically we use RE = 820 k

Practically we use R2 = 68 The designed component values are: RE = 860 R2 = 68

Example - 2

Fig. 14

Design the dual-input balanced output differential amplifier using the diode constant current bias to meet the following specifications.
1. supply voltage = 12 V. 2. Emitter current IE in each differential amplifier transistor = 1.5 mA. 3. Voltage gain 60.

Solution: The voltage at the base of transistor Q3 is

Assuming that the transistor Q3 has the same characteristics as diode D1 and D2 that is VD = VBE3, then

Practically we take RE = 240 .


Fig. 15

Practically we take R2 = 3.6 k.

To obtain the differential gain of 60, the required value of the collector resistor is

The following fig. 15 shows the dual input, balanced output differential amplifier with the designed component values as RC = 1K, RE = 240 , and R2 = 3.6K.
The operation amplifier:
An operational amplifier is a direct coupled high gain amplifier consisting of one or more differential (OPAMP) amplifiers and followed by a level translator and an output stage. An operational amplifier is available as a single integrated circuit package. The block diagram of OPAMP is shown in fig. 16.

Fig. 16 The input stage is a dual input balanced output differential amplifier. This stage provides most of the voltage gain of the amplifier and also establishes the input resistance of the OPAMP.The intermediate stage of OPAMP is another differential amplifier which is driven by the output of the first stage. This is usually dual input unbalanced output. Because direct coupling is used, the dc voltage level at the output of intermediate stage is well above ground potential. Therefore level shifting circuit is used to shift the dc level at the output downward to zero with respect to ground. The output stage is generally a push pull complementary amplifier. The output stage increases the output voltage swing and raises the current


supplying capability of the OPAMP. It also provides low output resistance.

Level Translator:
Because of the direct coupling the dc level at the emitter rises from stages to stage. This increase in dc level tends to shift the operating point of the succeeding stages and therefore limits the output voltage swing and may even distort the output signal. To shift the output dc level to zero, level translator circuits are used. An emitter follower with voltage divider is the simplest form of level translator as shown in fig.17. Thus a dc voltage at the base of Q produces 0V dc at the output. It is decided by R1 and R2. Instead of voltage divider emitter follower either with diode current bias or current mirror bias as shown in fig. 18 may be used to get better results. In this case, level shifter, which is common collector amplifier, shifts the level by 0.7V. If this shift is not sufficient, the output may be taken at the junction of two resistors in the emitter leg. Fig. 17

Fig. 18 Fig. 19, shows a complete OPAMP circuit having input different amplifiers with balanced output, intermediate stage with unbalanced output, level shifter and an output amplifier.


Fig. 19
Example-1: For the cascaded differential amplifier shown in fig.20 , determine:

The collector current and collector to emitter voltage for each transistor. The overall voltage gain. The input resistance. The output resistance.

Assume that for the transistors used hFE = 100 and VBE = 0.715V


Fig. 20 Solution: (a). To determine the collector current and collector to emitter voltage of transistors Q1 and Q2, we assume that the inverting and non-inverting inputs are grounded. The collector currents (IC IE) in Q1 and Q2 are obtained as below:

That is, IC1 = IC2 =0.988 mA. Now, we can calculate the voltage between collector and emitter for Q 1 and Q2 using the collector current as follows: VC1 = VCC = -RC1 IC1 = 10 (2.2k) (0.988 mA) = 7.83 V = VC2 Since the voltage at the emitter of Q1 and Q2 is -0.715 V, VCE1 = VCE2 = VC1 -VE1 = 7.83 + 0715 = 8.545 V Next, we will determine the collector current in Q3 and Q4 by writing the Kirchhoff's voltage equation for the base emitter loop of the transistor Q 3: VCC RC2 IC2 = VBE3 - R'E IC3 - RE2 (2 IE3) + VBE= 0 10 (2.2k) (0.988mA) - 0.715 - (100) (IE3) (30k) IE3 + 10=0 10 - 2.17 - 0.715 + 10 - (30.1k) IE3 = 0


Hence the voltage at the collector of Q3 and Q4 is VC3 = VC4= VCC RC3 IC3 = 10 (1.2k) (0.569 mA) = 9.32 V Therefore, VCE3 = VVCE4 = VC3 VE3 = 9.32 7.12 = 2.2 V Thus, for Q1 and Q2: ICQ = 0.988 mA VCEQ = 8.545 V and for Q3 and Q4: ICQ = 0.569 mA VCEQ = 2.2 V [Note that the output terminal (VC4) is at 9.32 V and not at zero volts.] (b). First, we calculate the ac emitter resistance r'e of each stage and then its voltage gain.

The first stage is a dual input, balanced output differential amplifier, therefore, its voltage gain is

Where Ri2 = input resistance of the second stage

The second stage is dual input, unbalanced output differential amplifier with swamping resistor R'E, the voltage gain of which is

Hence the overall voltage gain is Ad= (Ad1) (Ad2) = (80.78) (4.17) = 336.85


Thus we can obtain a higher voltage gain by cascading differential amplifier stages. (c).The input resistance of the cascaded differential amplifier is the same as the input resistance of the first stage, that is Ri = 2ac(re1) = (200) (25.3) = 5.06 k (d). The output resistance of the cascaded differential amplifier is the same as the output resistance of the last stage. Hence,

RO = RC = 1.2 k
Example-2: For the circuit show in fig.21, it is given that =100, VBE =0715V. Determine

The dc conditions for each state The overall voltage gain The maximum peak to peak output voltage swing.

Fig. 21 Solution: (a). The base currents of transistors are neglected and VBE drops of all transistors are assumed same.


From the dc equivalent circuit,


b) The overall voltage gain of the amplifier can be obtained as below:

Therefore, voltage gain of second stage

The input impedance of second stage is

The effective load resistance for first stage is

Therefore, the voltage gain of first stage is

The overall voltge gain is AV = AV1 AV2


(c). The maximum peak to peak output votage swing = Vopp = 2 (VC7 - VE7) =2 x (5.52 - 3.325) = 4.39 V

Practical Operational Amplifier

The symbolic diagram of an OPAMP is shown in fig. 1.

741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP chip.

Parameters of OPAMP:
The various important parameters of OPAMP are follows: 1.Input Offset Voltage: Input offset voltage is defined as the voltage that must be applied between the two input terminals of an OPAMP to null or zero the output fig. 2, shows that two dc voltages are applied to input terminals to make the output zero. Vio = Vdc1

Fig. 2


Vdc2 Vdc1 and Vdc2 are dc voltages and RS represents the source resistance. Vio is the difference of Vdc1 and Vdc2. It may be positive or negative. For a 741C OPAMP the maximum value of Vio is 6mV. It means a voltage 6 mV is required to one of the input to reduce the output offset voltage to zero. The smaller the input offset voltage the better the differential amplifier, because its transistors are more closely matched. 2. Input offset Current: The input offset current Iio is the difference between the currents into inverting and non-inverting terminals of a balanced amplifier. Iio = | IB1 IB2 | The Iio for the 741C is 200nA maximum. As the matching between two input terminals is improved, the difference between IB1 and IB2 becomes smaller, i.e. the Iio value decreases further.For a precision OPAMP 741C, I io is 6 nA 3.Input Bias Current: The input bias current IB is the average of the current entering the input terminals of a balanced amplifier i.e.


IB = (IB1 + IB2 ) / 2 For 741C IB(max) = 700 nA and for precision 741C IB = 7 nA 4. Differential Input Resistance: (Ri) Ri is the equivalent resistance that can be measured at either the inverting or non-inverting input terminal with the other terminal grounded. For the 741C the input resistance is relatively high 2 M. For some OPAMP it may be up to 1000 G ohm. 5. Input Capacitance: (Ci) Ci is the equivalent capacitance that can be measured at either the inverting and noninverting terminal with the other terminal connected to ground. A typical value of Ci is 1.4 pf for the 741C. 6. Offset Voltage Adjustment Range: 741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null for this purpose. It can be done by connecting 10 K ohm pot between 1 and 5 as shown in fig. 3.

Fig. 3 By varying the potentiometer, output offset voltage (with inputs grounded) can be reduced to zero volts. Thus the offset voltage adjustment range is the range through which the input offset voltage can be adjusted by varying 10 K pot. For the 741C the offset voltage adjustment range is 15 mV

Parameters of OPAMP:
7. Input Voltage Range :


Input voltage range is the range of a common mode input signal for which a differential amplifier remains linear. It is used to determine the degree of matching between the inverting and noninverting input terminals. For the 741C, the range of the input common mode voltage is 13V maximum. This means that the common mode voltage applied at both input terminals can be as high as +13V or as low as 13V. 8. Common Mode Rejection Ratio (CMRR). CMRR is defined as the ratio of the differential voltage gain Ad to the common mode voltage gain ACM CMRR = Ad / ACM. For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is the matching between two input terminals and the smaller is the output common mode voltage. 9. Supply voltage Rejection Ratio: (SVRR) SVRR is the ratio of the change in the input offset voltage to the corresponding change in power supply voltages. This is expressed in V / V or in decibels, SVRR can be defined as SVRR = Vio / V Where V is the change in the input supply voltage and Vio is the corresponding change in the offset voltage. For the 741C, SVRR = 150 V / V. For 741C, SVRR is measured for both supply magnitudes increasing or decreasing simultaneously, with R3 10K. For same OPAMPS, SVRR is separately specified as positive SVRR and negative SVRR. 10. Large Signal Voltage Gain: Since the OPAMP amplifies difference voltage between two input terminals, the voltage gain of the amplifier is defined as

Because output signal amplitude is much large than the input signal the voltage gain is commonly called large signal voltage gain. For 741C is voltage gain is 200,000 typically. 11. Output voltage Swing: The ac output compliance PP is the maximum unclipped peak to peak output voltage that an OPAMP can produce. Since the quiescent output is ideally


zero, the ac output voltage can swing positive or negative. This also indicates the values of positive and negative saturation voltages of the OPAMP. The output voltage never exceeds these limits for a given supply voltages +V CC and VEE. For a 741C it is 13 V. 12. Output Resistance: (RO) RO is the equivalent resistance that can be measured between the output terminal of the OPAMP and the ground. It is 75 ohm for the 741C OPAMP. Example - 1 Determine the output voltage in each of the following cases for the open loop differential amplifier of fig. 4: a. b. vin 1 = 5 m V dc, vin 2 = -7 Vdc vin 1 = 10 mV rms, vin 2= 20 mV rms

Fig. 4 Specifications of the OPAMP are given below: A = 200,000, Ri = 2 M , R O = 75, + VCC = + 15 V, - VEE = - 15 V, and output voltage swing = 14V. Solution: (a). The output voltage of an OPAMP is given by

Remember that vo = 2.4 V dc with the assumption that the dc output voltage is zero when the input signals are zero. (b). The output voltage equation is valid for both ac and dc input signals. The output voltage is given by

Thus the theoretical value of output voltage vo = -2000 V rms. However, the


OPAMP saturates at 14 V. Therefore, the actual output waveform will be clipped as shown fig. 5. This non-sinusoidal waveform is unacceptable in amplifier applications.

Fig. 5 13. Output Short circuit Current : In some applications, an OPAMP may drive a load resistance that is approximately zero. Even its output impedance is 75 ohm but cannot supply large currents. Since OPAMP is low power device and so its output current is limited. The 741C can supply a maximum short circuit output current of only 25mA. 14. Supply Current : IS is the current drawn by the OPAMP from the supply. For the 741C OPAMP the supply current is 2.8 m A. 15. Power Consumption: Power consumption (PC) is the amount of quiescent power (vin= 0V) that must be consumed by the OPAMP in order to operate properly. The amount of power consumed by the 741C is 85 m W. 16. Gain Bandwidth Product: The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage gain is reduced to 1. From open loop gain vs frequency graph At


1 MHz shown in. fig. 6, It can be found 1 MHz for the 741C OPAMP frequency the gain reduces to 1. The mid band voltage gain is 100, 000 and cut off frequency is 10Hz.

Fig. 6 17. Slew Rate: Slew rate is defined as the maximum rate of change of output voltage per unit of time under large signal conditions and is expressed in volts / secs.

To understand this, consider a charging current of a capacitor shown in fig. 7.


Fig. 6 If 'i' is more, capacitor charges quickly. If 'i' is limited to I max, then rate of change is also limited. Slew rate indicates how rapidly the output of an OPAMP can change in response to changes in the input frequency with input amplitude constant. The slew rate changes with change in voltage gain and is normally specified at unity gain. If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the slew rate is low 0.5 V / S. which limits its use in higher frequency applications. 18. Input Offset Voltage and Current Drift: It is also called average temperature coefficient of input offset voltage or input offset current. The input offset voltage drift is the ratio of the change in input offset voltage to change in temperature and expressed in V / C. Input offset voltage drift = ( Vio /T). Similarly, input offset current drift is the ratio of the change in input offset current to the change in temperature. Input offset current drift = ( Iio / T). For 741C, Vio / T = 0.5 V / C. Iio/ T = 12 pA / C.

Example - 1
A 100 PF capacitor has a maximum charging current of 150 A. What is the slew rate? Solution: C = 100 PF=100 x 10 F -6 I = 150 A = 150 x 10 A

Slew rate is 1.5 V / s.

Example - 2


An operational amplifier has a slew rate of 2 V / s. If the peak output is 12 V, what is the power bandwidth? Solution: The slew rate of an operational amplifier is

As for output free of distribution, the slews determines the maximum frequency of operation fmax for a desired output swing.

so So bandwidth = 26.5 kHz.

Example - 3
For the given circuit in fig. 1. Iin(off) = 20 nA. If Vin(off) = 0, what is the differential 5 input voltage?. If A = 10 , what does the output offset voltage equal?

Fig. 1 Solutin: Iin(off) = 20 nA Vin(off) = 0 (i) The differential input voltage = Iin(off) x 1k = 20 nA x 1 k = 20 V (ii) If A = 10 then the output offset voltage Vin(off) = 20 V x 10 = 2 volt Output offset voltage = 2 volts.
5 5

The ideal OPAMP :

An ideal OPAMP would exhibit the following electrical characteristic.


1. 2. 3. 4. 5. 6. 7.

Infinite voltage gain Ad Infinite input resistance Ri, so that almost any signal source can drive it and there is no loading of the input source. Zero output resistance RO, so that output can drive an infinite number of other devices. Zero output voltage when input voltage is zero. Infinite bandwidth so that any frequency signal from 0 to infinite Hz can be amplified without attenuation. Infinite common mode rejection ratio so that the output common mode noise voltage is zero. Infinite slew rate, so that output voltage changes occur simultaneously with input voltage changes.

There are practical OPAMPs that can be made to approximate some of these characters using a negative feedback arrangement.

Equivalent Circuit of an OPAMP:

Fig. 5, shows an equivalent circuit of an OPAMP. v1 and v2are the two input voltage voltages. Ri is the input impedance of OPAMP. Ad Vd is an equivalent Thevenin voltage source and RO is the Thevenin equivalent impedance looking back into the terminal of an OPAMP.

Fig. 5 This equivalent circuit is useful in analyzing the basic operating principles of OPAMP and in observing the effects of standard feedback arrangements vO = Ad (v1 v2) = Ad vd. This equation indicates that the output voltage vO is directly proportional to the algebraic difference between the two input voltages. In other words the OPAMP amplifies the difference between the two input voltages. It does not amplify the input voltages themselves. The polarity of the output voltage depends on the polarity of the difference voltage vd.


Ideal Voltage Transfer Curve:

The graphic representation of the output equation is shown in fig. 6 in which

the output voltage vO is plotted against differential input voltage vd, keeping gain Ad constant.

Fig. 6 The output voltage cannot exceed the positive and negative saturation voltages. These saturation voltages are specified for given values of supply voltages. This means that the output voltage is directly proportional to the input difference voltage only until it reaches the saturation voltages and thereafter the output voltage remains constant. Thus curve is called an ideal voltage transfer curve, ideal because output offset voltage is assumed to be zero. If the curve is drawn to scale, the curve would be almost vertical because of very large values of Ad.

Open loop OPAMP Configuration:

In the case of amplifiers the term open loop indicates that no connection, exists between input and output terminals of any type. That is, the output signal is not feedback in any form as part of the input signal. In open loop configuration, The OPAMP functions as a high gain amplifier. There are three open loop OPAMP configurations.

The Differential Amplifier:

Fig. 1, shows the open loop differential amplifier in which input signals vin1 and vin2 are applied to the positive and negative input terminals.


Fig. 1 Since the OPAMP amplifies the difference the between the two input signals, this configuration is called the differential amplifier. The OPAMP amplifies both ac and dc input signals. The source resistance Rin1 and Rin2 are normally negligible compared to the input resistance Ri. Therefore voltage drop across these resistances can be assumed to be zero. Therefore v1 = vin1 and v2 = vin2. vo = Ad (vin1 vin2 ) where, Ad is the open loop gain.

The Inverting Amplifier:

If the input is applied to only inverting terminal and non-inverting terminal is grounded then it is called inverting amplifier.This configuration is shown in fig. 2. v1= 0, v2 = vin. vo = -Ad vin


Fig. 2 The negative sign indicates that the output voltage is out of phase with respect to input 180 or is of opposite polarity. Thus the input signal is amplified and inverted also.

The non-inverting amplifier:

In this configuration, the input voltage is applied to non-inverting terminals and inverting terminal is ground as shown in fig. 3. v1 = +vin vo = +Ad vin This means that the input voltage is amplified by Ad and there is no phase reversal at the output. v2 = 0

Fig. 3 In all there configurations any input signal slightly greater than zero drive the output to saturation level. This is because of very high gain. Thus when operated in open-loop, the output of the OPAMP is either negative or positive saturation or switches between positive and negative saturation levels. Therefore open loop op-amp is not used in linear applications.


Output Offset Voltage:

In an OPAMP even if the input voltage is zero an output voltage can exist. There are three cause of this unwanted offset voltage. 1. 2. 3. Input offset voltage. Input bias voltage. Input offset current.

Fig. 4, shows a feedback amplifier with an output offset voltage source in series with the open loop output AVd. The actual output offset voltage with negative feedback is smaller. The reasoning is similar to that given for distortion. Some of the output offset voltage is fed back to the inverting input. After amplification an out of phase voltage arrives at the output canceling most of the original output offset voltage.

When loop gain AB is much greater than 1, the closed loop output offset voltage is much smaller than the open loop output offset voltage.

Fig. 4

Voltage Follower:
The lowest gain that can be obtained from a non-inverting amplifier with feedback is 1. When the non-inverting amplifier gives unity gain, it is called voltage follower because the output voltage is equal to the input voltage and in phase with the input voltage. In other words the output voltage follows the input voltage. To obtain voltage follower, R1 is open circuited and Rf is shorted in a negative feedback amplifier of fig. 4. The resultant circuit is shown in fig. 5.


vout = Avd= A (v1 v2) v1 = vin v2 =vout v1 = v2 if A >> 1 vout = vin. The gain of the feedback circuit (B) is 1. Therefore Af = 1 / B = 1 Fig. 5