9/2/13

What's the function of Ripple Blanking I/O and LT pin on the 7447 BCD decoder IC?
User Name Password Log in

Register

Lost password?

Resend activation?

Remember Me?

Forum
New Posts

Activity Stream
Unansw ered Posts

Search
FAQ

Help

Rules
Com m unity

Groups
Quick Links

Albums

Blogs

What's New?
Advanced Search

Forum Actions

Forum

EDA Theory

Electronic Elementary Questions

What's the function of Ripple Blanking I/O and LT pin on the 7447 BCD decoder IC?

+ Post New Thread

What's the function of Ripple Blanking I/O and LT pin on the 7447 BCD decoder IC?
LinkBack Thread Tools

Results 1 to 9 of 9

Search Thread

08-08-08, 09:35

#1

darrenbkl
Member level 2

What's the function of Ripple Blanking I/O and LT pin on the 7447 BCD decoder IC?
Hi all,have a question here is that,what is the function RBI,RBO and LT pin on the 7447 BCD7segent decoder IC? It seems to suppressed zero on the 7 segment display,but I don't know how it works. About the LT, I only know has to connect to VCC, can anyone explain me? thx : )

Join Date: Posts: Helped: Points: Level:

Jul 2008 45 1/1 1,230 7

Reply With Quote

08-08-08, 10:42

#2

Arkham00
Newbie level 5

ripple blanking
LT is a LAMP TEST input. It's active low so when at logic level 1, it has no effect; when at logic level 0, every output is active so you can check if a segment or an output is broken. RBI is RIPPLE BLANKING INPUT is used in multi-digit display and should be connected to the RBO of the previous digit (the digit to the left). In this way, you may avoid showing trailing "0" if not needed as you do in manual number writing. In this way, for example, the multidigit number "00123" will show as "__123" while "02034" will show as "_ 2034" (where "_" is to be intended as an off digit). This trick was in use when digital circuits were not so intelligent as now with microcontrollers.

Join Date: Location: Posts: Helped: Points: Level:

Aug 2008 Italy 10 2/2 981 7

Reply With Quote

08-08-08, 10:42

Design and verification

www.DVTEclipse.com

Modern programming environment for e, SystemVerilog, Verilog and VHDL.

08-08-08, 13:00

#3

darrenbkl
Member level 2

ripple blanking output

cool,thx. I m a newbie in electronic stuff,currently still doing flip flop and counter : ( I try to connect a 7490 counter --- 7447 --- 7 segment display using multisim,it works. But why when i switch on the circuit, the display appear unstable? I mean when the display change from a number to the other, let's say from 4 to 5, in between transition there is some unstable state of the display. is it cause by propagation delay of the serial ripple counter connection?

Join Date: Posts: Helped: Points:

Jul 2008 45 1/1 1,230

www.edaboard.com/thread132006.html

1/3

9/2/13
Level: 7

What's the function of Ripple Blanking I/O and LT pin on the 7447 BCD decoder IC?

Reply With Quote

08-08-08, 14:17

#4

Arkham00
Newbie level 5

ripple-blanking
Don't think so. Propagation time in standard TTL is very fast. Maybe some pin left open even if in TTL logic, an unconnect pin should be read as '1'. Try posting the schematic.

Join Date: Location: Posts: Helped: Points: Level:

Aug 2008 Italy 10 2/2 981 7

Reply With Quote

08-08-08, 14:17

100% Free DataSheet (PDF)

www.AllDataSheet.com

Over 20000000 DataSheet. It's Free. Multi Fast Search System.

09-08-08, 07:37

#5

darrenbkl
Member level 2

rippleblanking input

Join Date: Posts: Helped: Points: Level:

Jul 2008 45 1/1 1,230 7

Added after 35 minutes: http://pdf1.alldatasheet.com/datashe...LD/74LS90.html this is the DM74LS90 datasheet, where i was confuse by the 7490 schematic diagram. the clock input B is into 2nd and 4th flip flop only ,and 2nd FF's J input is determine by 4th FF's Q bar output. and 4th FF K input is determine by its Q output. how does this work basically i dun understand. thx for guiding :D

Reply With Quote

09-08-08, 08:56

#6

Arkham00
Newbie level 5

ripple-blanking input
The circuit seems basically correct. Just some note: * the clock frequency of 1kHz is very high for a display. You'll be unable to see the number changing. Try with much lower frequency like 1 or 2 Hz * the BI/RBO pin is a strange input/output pin. Leave it unconnected

Join Date: Location: Posts: Helped: Points: Level:

Aug 2008 Italy 10 2/2 981 7

* try the same with LT and RBI. In TTL logic (like LS family), an unconnected pin is equivalent to a logic "1" (but this is not true for CMOS logic where every pin mus be connected to a secure digital level) * in the real circuit, put a 0.1uF bypass ceramic capacitor as near as possible to the poer pins of the device
1 members found this post helpful.

www.edaboard.com/thread132006.html

2/3

9/2/13

What's the function of Ripple Blanking I/O and LT pin on the 7447 BCD decoder IC?
Reply With Quote

09-08-08, 17:57

#7

darrenbkl
Member level 2

7490 schematic
wat does the 0.1uF cap do? u mean place it near "power" pin?

Join Date: Posts: Helped: Points: Level:

Jul 2008 45 1/1 1,230 7

Reply With Quote

09-08-08, 21:18

#8

Arkham00
Newbie level 5

7447 multisim example vcc pin

Yes, sorry ... I meant "power" pins. In real-world circuits, it's suggested to put a 0.1uF capacitor between VDD and VSS of a device every few device to filter high frequency noise generated by fast switching logic devices.

Join Date: Location: Posts: Helped: Points: Level:

Aug 2008 Italy 10 2/2 981 7

Reply With Quote

12-08-08, 05:40

#9

darrenbkl
Member level 2

ripple blanking
A clock pulse with 1kHz frequency,which is a 50% duty cycle square, that means the period of the wave is 1ms right? But 1 pulse is consist of a high and low , or high and low are consider as a pulse separately?

Join Date: Posts: Helped: Points: Level:

Jul 2008 45 1/1 1,230 7

Reply With Quote

+ Post New Thread

Flip-Flop initial value at startup? | What does FO4 stand for ?
Similar Threads
how can ı design a bcd to decimal decoder usin the (2) K-mapping of 7447 - does anybody have? (2) VERILOG CODE FOR BCD TO DECODER???? (1) 7447 display(seven segment) (1) 7-seg to BCD decoder 74C915 info request (7)

-- Edaboard Classic

Contact Us Forum for Electronics Privacy Statement Terms of Service Top

All times are GMT +1. The time now is 17:14. Powered by vBulletin Copyright 2010 vBulletin Solutions, Inc. All rights reserved. SEO by vBSEO 2011, Crawlability, Inc.

www.edaboard.com/thread132006.html

3/3