Modelsim Altera Starter Edition Tutorial

In this lab, Modelsim Altera Starter Edition is chosen as the software to edit, compile, and simulate the Verilog HDL for a single cycle MIPS processor project. Please note that only Windows and Linux OS are supported by Altera.

Installation
After downloading this installer, follow the step by step tutorial to install the Modelsim Altera Starter Edition. 1. After downloading the installer, double click it, you will see this. Click Next.

2. Agree with the license agreement and Click Next:

3. Choose Download Installation Files from the Internet and Next

4. Choose the destination directory and the temporary directory. You can use the default directory.

5. In the Component Select page, select the ModelSim-Altera Starter Edition. Click Next to check the summary and then Next to start the Installation.

Demo
After successfully installing the software, lets run a simple demo to illustrate how to use Modelsim simulator. First download the demo design on the website. The demo design is a simple verilog 32 bit adder and its testbench. It includes two files: ADDER.v: The Verilog HDL file of the adder. Adder_tb.v: The testbench of the adder, used for the simulation. Now lets start a project in Modelsim with the demo design. If you are using the windows OS, you will find a shortcut of ModelSim on your desktop. If not, you can find the executable for the software at the following location (\modelsim_ase\win32aloem \modelsim.exe). 1. Open the software. You will see:

2. Start a new project. Click File->New->Project, you will see a small window:

Name your project, and set the project location. Here, I use the name demo and set the location to the folder that contains the demo files ADDER.v and Adder_tb.v. The Default Library Name indicates where all your project files would store in the library. Here we use the default name: work. Click OK to complete the project setup. 3. Add files to your project. In the pop-up window, choose Add Exiting File to add ADDER.v and Adder_tb.v to the project.

4. Compile the Verilog files in the project. The two demo files are included in your project. Right click in the main window, choose Compile->Compile all to compile all the files. After compilation, the ? in the Status would change to . If there is any problem with the code, a red cross will show in the status and there will be an error message in the Transcript command line window. In this case, you can double click the file to debug the Verilog code and fix the errors.

5. Change to the library view. After successfully compiling all your files, change the Project view to Library view by click the Library bar on the bottom of the main window.

6. Start simulation window. Under the work directory, double click adder_tb, the simulation window starts.

7. Here is the general view of the simulation window. Make sure the connections between your modules are correct, or you will have problems to get this window. In the left window, all your modules are shown. When you choose a module, all the signals in this module would show in the right window.

8. Setup the waveform window. In the left window, right click the adder_tb and choose Add->To Wave->All items in region to add signals to the waveform window. You can also choose the particular signals you want to add to the waveform window.

9. Here is the Waveform window. On the tool bar, you can change the simulation time, and run the simulation. In this demo, we set the simulation time as 100ns. Click the Run button to run the simulation. After the simulation, you will see the waveforms for all the signals.

10. Use the Zoom In to check the details of the waveforms. In this demo, you will see that: every 1000ps, dataa and datab signals would increase by 1 and result signal is the sum of these two signals.

Resources:
Here are some useful websites about Verilog HDL:
http://www.asic-world.com/verilog/ http://www.ece.umd.edu/courses/enee359a/verilog_tutorial.pdf http://www.verilogtutorial.info/ Here are some tutorials about ModelSim tool: http://doc.union.edu/118/se_tutor.pdf http://ee.sharif.edu/~digitalvlsi/Docs/modelsim_tut.pdf http://cseweb.ucsd.edu/classes/sp10/cse141L/lab1/modelsim_tut.pdf