EL 511 VLSI Design

Instructor: Mazad S. Zaveri Faculty Block 4, Room 4206 Email: mazad_zaveri@daiict.ac.in http://intranet.daiict.ac.in/~mazad_zaveri/

EL 511 VLSI Design

Amdahls law
Important in todays world of multi-core chips According to Amdahls law, the performance increase (speed-up) is limited by the sequential part of the code Speed-up is S = 1/[ops +(opp /p)],
where = ops the fraction of serial operations, opp = the fraction of parallel operations, p = number of parallel processors

Hence, as the number of parallel processors p increase, S becomes more dependent on the serial portion of the data
i.e. S (1/ops), when p is very large

The improvement in terms of performance, by adding more processors (operating in parallel) will gradually diminish
Economics - Law of diminishing returns

EL 511 Intro. VLSI Design

PN junction formation
General functional form of the electrostatic variables in a PN junction (under equilibrium)
Electrostatic potential (V)
Built-in potential (Vbi)

Electric-Field Charge density

Where does the charge come from? Static charge?

How to draw these plots manually?

Look at their equations
E= 1 dEc 1 dEv 1 dEi = = q dx q dx q dx
EL 511 VLSI Design

E=

dV dx

dE = dx K S 0
3

Built-in Potential
Built-in potential
Definition:
Voltage drop that occurs across the depletion region under equilibrium conditions

Its a function of the doping concentrations of P and N side both Acts as an opposition to flow of carriers
How much energy does a hole need to travel from p-side to n-side How much energy does an electron need to travel from n-side to p-side

1 Vbi = ( Ei EF ) p side + ( EF Ei )n side q

ND ln = E E kT ( F i )n side ni

( Ei EF ) p side = kT ln

NA ni

kT N A N D ln Vbi = q ni2
EL 511 VLSI Design

Depletion width
How to calculate depletion region width? We can separately calculate the depletion regions on the n-side and pside Function of the doping concentrations, the built-in potentials, and applied voltage
1/ 2

N D xn 2 K S 0 ND = xp = (Vbi VA ) NA q N A (N A + ND )

2KS 0 NA xn = (Vbi VA ) q ND (N A + ND )

1/ 2

2K S 0 N A + N D W = (Vbi VA ) q N A ND

1/ 2

Depletion capacitance

KS 0 A CJ = W
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EL 511 VLSI Design

Depletion Width
Depletion width is a function of applied (external) voltage
If applied voltage (VA>0)
qND

-qNA

Depletion width decreases Space charge decreases Electric field (max value) decreases Electro-static potential effectively reduces Depletion width increases Space charge increases Electric field (max value) increases Electro-static potential effectively increases

If applied voltage (VA<0)

Max value of electric field

EL 511 VLSI Design

qN D xn qN A x p E max = = KS 0 KS 0

Possible (Ideal) MS Contacts

Workfunction N-type relation semiconductor

M > S
S > M

P-type semiconductor Ohmic Rectifying

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Rectifying Ohmic
EL 511 VLSI Design

Metal-Semiconductor contacts
Equations:
Depletion region Electric field Built-in potential Workfunction of semiconductor
2K S 0 1 W = (Vbi VA ) q ND/ A qN D / A W E= KS 0 1 Vbi = [ M S ] q E S = + G + Ei EFp 2 EG S = + ( EFn Ei ) 2
1/ 2

EL 511 VLSI Design

MOS Capacitor with N-type substrate - Under Various Bias Conditions

N-type substrate (or body)

In P-channel MOSFET

Depending on the applied gate-voltage

MOS Cap could exhibit the following conditions:
Flat band (VG = 0) Accumulation (VG > 0) Depletion (VG < 0) Onset of inversion (VG = VT) Inversion (VG < VT)
Flat band Accumulation 0

(VG < 0)

Onset of Inversion Inversion

(VG < 0)

Depletion VT

Applied Volt. VG
VLSI systems work at 0 to +ve Volts. How do we give ve voltages to P-MOSFET?

N-type substrate: Flat band

When VG = 0 (No applied bias)
Metal Fermi-level and substrate Fermi-level are aligned No band bending
Assuming that the workfunction of metal and semiconductor are equal (ideal condition) The characteristics of the substrate (concentration of electrons) is the same everywhere (in the bulk and near the surface)

Block charge diagram

No generated charges The substrate has many electrons (Even then, why is there no charge?)
Surface (Oxide-Semiconductor interface) Bulk

VG
Surface Bulk Gate Oxide

Oxide

Gate Substrate Substrate

GND

 When VG>0
Relatively

N-type substrate: Accumulation

Metal Fermi-level goes down (relatively to substrate Fermi-level)

For simplicity, assume that substrate Fermi-level remains in a fixed position, because substrate is grounded.

Band bending will be such that (near the surface)

Ei moves away from the semiconductor Fermi-level
The concentration of electrons increases at/near the surface as compared to the bulk

Notice, oxide bands also bend, but with constant slope

Block charge diagram

Positive charge on the gate
Leads to a negative charge (accumulation of electrons) near the surface region in the semiconductor substrate
Oxide Surface (Oxide-Semiconductor interface) Bulk

VG

Gate Oxide

Gate Substrate Substrate

GND

 When VT< VG<0

Relatively

N-type substrate: Depletion

Band bending will be such that

Metal Fermi-level goes up slightly (relatively to substrate EF) Ei (surface) moves closer to EF The concentration of electrons decreases at/near the surface
How? Electrons near the surface are repelled (due to applied ve bias on gate), Electron will move further deep into the bulk region But, these electrons will leave behind +ve charged ionized donor atoms (fixed charges), which will create a depletion region.

Block charge diagram

-ve charge on the gate
Leads to a +ve charge (ionized donors in depletion region) near the surface
Surface (Oxide-Semiconductor interface) Oxide Bulk Gate Oxide

VG

Gate Substrate Gate Oxide Substrate

Substrate

GND

When VG = VT (VG<0)
Relatively Band continue to bend (same direction as VT< VG<0)

Metal Fermi-level continues to go up (relatively to substrate EF)

N-type substrate: Onset of Inversion

Onset of channel formation

Ei (surface) crosses the EF level, and continues to move up Electrons concentration continues to decrease near the surface Hole concentration continues to increase near the surface

Block charge diagram

When Ei(surface) = EF, we have p(surface) = n(surface) = ni When Ei(surface) > EF, we have p(surface) > n(surface), and p(surface) < n(bulk) When Ei(surface) - EF = EF - Ei(bulk), we have inversion of the surface We have p(surface) = n(bulk), majority carriers at surface are now holes Also, in other words, Ei(surface) - Ei(bulk) = 2[EF - Ei(bulk)], at inversion

More -ve charge on the gate

Leads to a +ve charge (ionized donors in depletion region) near the surface Depletion region width grows (max. at inversion) Leads to increase in +ve charged holes at surface
Oxide

VG
Surface (Oxide-Semiconductor interface) Bulk Gate Oxide

Gate Substrate

Substrate

Gate

Oxide Substrate

GND

N-type substrate: Strong Inversion

When VG < VT (VG<0)
Relatively Band continue to bend (same direction as VT< VG<0)
Ei(surface) - EF > EF - Ei(bulk) We have p(surface) > n(bulk)

Metal Fermi-level continues to go up (relatively to substrate EF) Hole concentration continues to increase near the surface (in the channel)

Block charge diagram

More -ve charge on the gate
Depletion region width assumed to be stuck at max. (i.e. same as that during onset of inversion) Leads to increase in +ve charged holes at surface
VG
Oxide Surface (Oxide-Semiconductor interface) Bulk Gate Substrate Gate Oxide

Substrate

Gate

Oxide Substrate

GND

Equations (according to Pierrets book)

Numerical Examples
Consider NA = 1018 cm-3
What is surface potential at inversion? What is surface potential at inversion?

Consider ND = 1018 cm-3

Draw the approx. band diagram ?

1 [ Ei (bulk ) Ei ( surface)] q 1 F = [ Ei (bulk ) EF (bulk )] q

S =

Ei (bulk)

kT N A P-type semiconductor ln F = q ni kT N D ln F = N-type semiconductor q ni

Ei (surface)

S = 2F

At the depletion to inversion transition point

Equations (from Pierret)

2KS 0 W = S qN A
1/ 2

2KS 0 Wmax = 2F qN A qN A W E= KS 0

1/ 2

MOS Cap: P-type substrate

Similar in functioning to the n-type substrate MOS Cap
But the relation of applied gate voltage to the various exhibited MOS Cap conditions are reversed
Flat band Accumulation 0 Onset of Inversion Inversion Depletion VT

Applied Volt. VG

P-type substrate: Flat Band Condition

When VG = 0 (No applied bias)
Metal Fermi-level and substrate Fermi-level are aligned No band bending
Assuming that the workfunction of metal and semiconductor are equal (ideal condition) The characteristics of the substrate (concentration of holes) is the same everywhere (in the bulk and near the surface)

Surface Bulk

Block charge diagram

No generated charges

P-type substrate: Accumulation

When VG<0
Relatively
Metal Fermi-level goes up (relatively to substrate Fermi-level)
For simplicity, assume that substrate Fermi-level remains in a fixed position, because substrate is grounded.

Band bending will be such that (near the surface)

Ei moves away from the semiconductor Fermilevel
The concentration of holes increases at/near the surface as compared to the bulk

Notice, oxide bands also bend, but with constant slope

Block charge diagram

Negative charge on the gate
Leads to a positive charge (accumulation of holes) near the surface region in the semiconductor substrate

P-type substrate: Depletion

When VT> VG >0
Relatively
Metal Fermi-level goes down (relative to substrate EF)

Band bending will be such that

Ei (surface) moves closer to EF The concentration of holes decreases at/near the surface
How? Holes near the surface are repelled (due to applied +ve bias on gate); i.e. electron from bulk will be attracted, and will fill up missing bonds (holes) at acceptor atoms Hence, these acceptor atoms become -ve charged ionized acceptor atoms (fixed charges), and create a depletion region.

Block charge diagram

+ve charge on the gate
Leads to a -ve charge (ionized acceptors in depletion region) near the surface

P-type substrate: Onset of Inversion and Inversion

When VG >= VT (VG = VT at Onset of Inversion)
Relatively
Metal Fermi-level continues to go down (relatively to substrate EF)

Band continue to bend (same direction as VT> VG >0)

Ei (surface) crosses the EF level, and continues to move down Hole concentration continues to decrease near the surface Electron concentration continues to increase near the surface
When Ei(surface) = EF, we have p(surface) = n(surface) = ni When Ei(surface) < EF, we have n(surface) > p(surface), and n(surface) < p(bulk) When EF - Ei(surface) = Ei(bulk) - EF, we have inversion of the surface We have n(surface) = p(bulk), majority carriers at surface are now electrons Also, in other words, Ei(bulk) - Ei(surface) = 2[Ei(bulk)- EF], at inversion

Block charge diagram

More +ve charge on the gate
Leads to a -ve charge (ionized acceptors in depletion region) near the surface Depletion region width grows (assume max. at inversion) Leads to increase in -ve charged electrons at surface

Ideal IV Characteristics NMOS

<

What is the meaning of this plot?

Vds
DC sweep from 0 to 1.8V

Vgs
DC (step) sweep 0.6, 0.9, 1.2, 1.5, 1.8

Where are linear and saturation regions in the plot?

Boundary condition
Vds >= Vgs-Vt

Can we approx verify this graph, with the given equations? Can we find the resistance of the transistor in linear/resistive region from this plot?

EL 511 VLSI Design

22

Ideal IV Characteristics PMOS

Similar to NMOS
However,
Mobility of holes is 2-3 times less than mobility of electrons So for the same sized (W/L) transistor,
PMOS will provide almost 1/3 to the current, as compared to NMOS

Voltage and current directions are reversed

Source is generally at higher potential than the drain Holes flow from source-todrain
Current flows from sourcedrain
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EL 511 VLSI Design

Conditions to check for Cut-off/Linear/Saturated