SR INTERNATIONAL INSTITUTE OF TECHNOLOGY

Rampally(V), Keesara(M), Ranga Reddy(Dist.) 501 301 Name of the faculty: Class: Class Hours UJWALA.B ECE 2nd BTECH 2 SEM 78

Lesson Plan of : __________________________________________ PULSE AND DIGITAL CIRCUITS Credit: 4 Total Number of Lectures Available:80 Total Number of Lecture According to Lesson Plan: 78 Lec No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Date 17/12/12 to 22/12/12 Topic to be covered Linear wave shaping :Low pass RC circuits or sinusoidal input Step and pulse input Low pass response for ramp input Low pass response for square wave input Low pass circuit acts as an integrator High pass circuit for sinusoidal and step input Response for ramp input Response for square wave input attenuators RL and RLC circuits Ringing circuit NON-LINEAR WAVE SHAPING:Diode clippers Clipping at two independent levels Transistor clippers Comparators,applications of voltage comparators Clamping operation Clamping circuit taking source and diode resistance taking into account Clamping circuit theorem Practical clamping circuits Effect of diode characteristics on clamping voltage Synchronized clamping Switching characteristics of diodes :Diode as a switch Piecewise linear diode characteristics Diode switching times Transistor as a switch Breakdown voltages Transistor in saturation Temperature variation of saturation parameters Transistor switching times Silicon controlled switch circuits Multivibrators: Fixed Bias Bistable Multivibrator Problems on fixed bias multivibrator Reference T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3

24/12/12 to 29/12/12

31/12/12 to 05/01/13

07/01/13 to 12/01/13

16/01/13 to 22/01/13

23/01/13 to 29/01/13

30/01/13 to 05/01/13

33 34 35 36 37 38 39 40 41 42 43 44 45 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

30/01/13 to 05/01/13

06/01/13 to 10/01/13

14/02/13 to 20/02/13

21/02/13 to 27/02/13

28/02/13 to 06/03/13

07/03/13 to 13/03/13

14/03/13 to 20/03/13

21/03/13 to 27/03/13

28/03/13 to 03/04/13

04/04/13 to 10/04/13

A self biased transistor binary commutating capacitors A non saturating binary A direct connected binary the emmiter coupled binary the collector coupled monostable multivibrator the collector coupled monostable multivibrator emmiter coupled monostable multivibrator triggering the monostable multivibrator the collector coupled astable multivibrator the collector coupled astable multivibrator emmiter coupled astable multivibrator emmiter coupled astable multivibrator TIME BASE GENERATORS: methods of generating time base waveform Miller and Bootstrap time base generators basic principles Miller and Bootstrap time base generators basic principles Transistor miller time base generator Transistor Bootstrap time base generator Transistor Bootstrap time base generator Current time base generators Current time base generators Methods of linearity improvement. SAMPLING GATES: Basic operating principles of sampling gates Unidirectional sampling gates bidirectional sampling gates Four diode sampling gate Reduction of pedestal in gate circuits Six diode gate Applications of sampling gates. SYNCHRONIZATION AND FREQUENCY DIVISION: Pulse synchronization of Relaxation devices Freq uency division in sweep circuit Stability of relaxation devices Astable relaxation circuits Monostable relaxation circuits Synchronization of a sweep circuit with symmetrical signals Synchronization of a sweep circuit with symmetrical signals Sine wave frequency division with a sweep circuit Sine wave frequency division with a sweep circuit A sinusoidal divider using Regeneration and Modulation A sinusoidal divider using Regeneration and Modulation REALIZATION OF LOGIC GATES USING DIODES & TRANSISTORS: AND, OR and NOT gates using Diodes and transistors DCTL RTL DTL TTL

T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3 T1,R1,R3

77 78

04/04/13 to 10/04/13

CML comparision

T1,R1,R3 T1,R1,R3

TEXT BOOKS : 1. 2. Pulse, Digital and Switching Waveforms - J. Millman and H. Taub, McGraw-Hill, 1991. Solid State Pulse circuits - David A. Bell, PHI, 4th Edn., 2002 .

REFERENCES : 1. 2. 3. Pulse and Digital Circuits - A. Anand Kumar, PHI, 2005. Wave Generation and Shaping - L. Strauss. Pulse, Digital Circuits and Computer Fundamentals - R.Venkataraman.

SR INTERNATIONAL INSTITUTE OF TECHNOLOGY

Rampally(V), Keesara(M), Ranga Reddy(Dist.) 501 301 Name of the faculty: Class: Class Hours UJWALA.B ECE II BTECH II SEM 50 mints

Lesson Plan of : __________________________________________ SWITCHING THEORY AND LOGIC DESIGN Credit: 4 Total Number of Lectures Available: 80 Total Number of Lecture According to Lesson Plan: 82
LEC NO 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. DATE

TOPIC TO BE COVERED

BINARY SYSTEMS :Philosophy of number systems 17/12/12 Decimal and binary number system to octal and hexadecimal number systems 22/12/12 Conversions from 1 number system to other number system 1s and 2s complement representation of negative numbers and problems 9,s and 10,s complements and subtraction methods 24/12/12 Binary arithmetic: addition, subtraction, multiplication, to Binary codes, Gray code , XS-3 code and problems 29/12/12 BCD codes,BCD addition and subtraction error detecting codes,binary logic Error correcting codes,binary storage and registers BOOLEAN ALGEBRA AND LOGIC GATES :Fundamental 31/12/12 postulates of Boolean algebra to 05/01/13 Basic theorems and properties Reducing Boolean expressions Logic gates, universal logic gates Boolean functions and their representation 07/01/13 Canonical SOP,POS forms Standard SOP ,POS forms and problems to 12/01/13 Properties of XOR gates

REFERENC E T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3,R2 T2,T3

integrated circuits
GATE LEVEL MINIMIZATION :Introduction 16/01/13 Minimization of SOP and POS forms k-map for 2 and 3 variables to 22/01/13 k-map for 4 variables k-map for 5 variables Dont care combinations,Exclusive Or function 23/01/13 NAND and NOR implementation other Two-level implementnations, to 29/01/13 Hardward Description language (HDL). COMBINATIONAL LOGIC :Combinational Circuits

30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41.

Analysis procedure 30/01/13 Design procedure to Binary Adder 05/01/13 Binary Subtractor
Decimal Adder

T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3

Binary multiplier 06/01/13 magnitude comparator to magnitude comparator 10/01/13 Decoders Encoders Multiplexers

42.
43. 47. 48. 49. 50. 51. 52. 53. 54. 55. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 71. 72. 73. 74. 75. 76.

14/02/13 problems to HDL for combinational circuits 20/02/13 HDL for combinational circuits SYNCHRONOUS SEQUENTIAL LOGIC :Sequential circuits latches, Flip-Flops Analysis of clocked sequential circuits HDL for sequential circuits 28/02/13 HDL for sequential circuits State Reduction and Assignment to 06/03/13 State Reduction and Assignment

Design Procedure.
discussion 07/03/13 UNIT-6:Registers to shift Registers 13/03/13

SISO

SIPO 14/03/13 PISO,PIPO Ripple counters to 20/03/13 synchronous counters

other counters HDL for Registers 21/03/13 HDL for Registers

to HDL for counters 27/03/13 HDL for Registers discussion UNIT-7:Random-Access Memory Memory Decoding Error Detection & correction Read-only memory Programmable logic Array 04/04/13 programmable Array logic to 10/04/13

Sequential Programmable Devices.

77. 78. 79. 80. 81. 82.

04/04/13 to ASYNCHRONOUS SEQUENTIAL LOGIC :introduction 10/04/13

Analysis Procedure

T2,T3 T2,T3 T2,T3 T2,T3 T2,T3 T2,T3

Circuits with Latches

Design Procedure Reduciton of state and Flow Tables Hazards, Design Example. Race-Free state Assignment

TEXT BOOKS : 1. DIGITAL DESIGN Third Edition , M.Morris Mano, Pearson Education/PHI. 2. FUNDAMENTALS OF LOGIC DESIGN, Roth, 5th Edition,Thomson. REFERENCES : 1. Switching and Finite Automata Theory by Zvi. Kohavi, Tata McGraw Hill. 2. Switching and Logic Design, C.V.S. Rao, Pearson Education 3. Digital Principles and Design Donald D.Givone, Tata McGraw Hill, Edition. 4. Fundamentals of Digital Logic & Micro Computer Design , 5TH Edition, M. Rafiquzzaman John Wiley

Rafiquzzaman John Wiley