Lec15 PDF

Digital Integrated Circuits Lecture 15: Nonideal Transistors
Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw
DIC-Lec15 cwliu@twins.ee.nctu.edu.tw
Outline

Transistor I-V Review Nonideal Transistor Behavior

Velocity Saturation Channel Length Modulation Body Effect Leakage Temperature Sensitivity Process Corners
Process and Environmental Variations
Ideal Transistor I-V
Shockley 1st order transistor models
0 Vds I ds = Vgs Vt 2 2 Vgs Vt ) ( 2
Vgs < Vt V V < V ds ds dsat Vds > Vdsat
cutoff linear saturation

3
Ideal vs. Simulated nMOS I-V Plot
180 nm TSMC process Ideal Models = 155(W/L) A/V2 Vt = 0.4 V VDD = 1.8 V
Ids (A) 400 300 Vgs = 1.8
BSIM 3v3 SPICE models
Ids ( A ) 250 200 V g s = 1 .8 V g s = 1 .5 V g s = 1 .2 V g s = 0 .9 50 V g s = 0 .6 0 0 0 .3 0 .6 0 .9 V ds 1 .2 1 .5
200
Vgs = 1.5 Vgs = 1.2 Vgs = 0.9 Vgs = 0.6 0 0.3 0.6 0.9 1.2 1.5 1.8
150 100
100
Vds
Simulated nMOS I-V Plot

180 nm TSMC process BSIM 3v3 SPICE models What differs? Less ON current No square law Current increases in saturation
Ids (A) 250 200 150 100 Vgs = 0.9 50 Vgs = 0.6 0 0 0.3 0.6 0.9 Vds 1.2 1.5 Vgs = 1.8 Vgs = 1.5 Vgs = 1.2
Velocity Saturation
We assumed carrier velocity is proportional to E-field v = Elat = Vds/L At high fields, this ceases to be true Carriers scatter off atoms Velocity reaches vsat
sat
Electrons: 6-10 x 106 cm/s Holes: 4-8 x 106 cm/s
sat / 2
Better model
v= Elat vsat = Esat E 1 + lat Esat
0 0
slope =
Esat
2Esat Elat
3Esat
Vel Sat I-V Effects
Ideal transistor ON current increases with VDD2

2 W (Vgs Vt ) I ds = Cox = (Vgs Vt ) 2 2 L 2
Velocity-saturated ON current increases with VDD

I ds = CoxW (Vgs Vt ) vmax
Real transistors are partially velocity saturated Approximate with -power law model Ids VDD 1 < < 2 determined empirically
DIC-Lec15 cwliu@twins.ee.nctu.edu.tw 7
-Power Model
0 V I ds = I dsat ds Vdsat I dsat Vgs < Vt Vds < Vdsat Vds > Vdsat
Ids (A) 400 300 Vgs = 1.8 200 Vgs = 1.5 100 Vgs = 1.2 Vgs = 0.9 Vgs = 0.6 0 0.3 0.6 0.9 1.2 1.5 1.8 V ds
cutoff linear saturation

Simulated -law Shockley
I dsat = Pc
(Vgs Vt )
Vdsat = Pv (Vgs Vt )
/2
Channel Length Modulation
Reverse-biased p-n junctions form a depletion region

Region between n and p with no carriers Width of depletion Ld region grows with reverse bias Leff = L Ld Ids increases with Vds Even in saturation
n+ L Leff p GND n+ bulk Si GND Source VDD Gate VDD Drain Depletion Region Width: Ld
Shorter Leff gives more current

Chan Length Mod I-V

I ds =
Ids (A)
V ( 2
gs
Vt ) (1 + Vds )
2
400 300 Vgs = 1.8
200
Vgs = 1.5 Vgs = 1.2 Vgs = 0.9 Vgs = 0.6 0.3 0.6 0.9 1.2 1.5 1.8 Vds
100
0 0
= channel length modulation coefficient not feature size Empirically fit to I-V characteristics
DIC-Lec15 cwliu@twins.ee.nctu.edu.tw 10
Body Effect

Vt: gate voltage necessary to invert channel Increases if source voltage increases because source is connected to the channel Increase in Vt with Vs is called the body effect
11
Body Effect Model

Vt = Vt 0 +
s + Vsb s
s = surface potential at threshold

s = 2vT ln
Depends on doping level NA And intrinsic carrier concentration ni = body effect coefficient
= ox
tox 2q si N A = 2q si N A Cox
NA ni
12
OFF Transistor Behavior

What about current in cutoff? I Simulated results 1 mA What differs? 100 A 10 A Current doesnt go 1 A to 0 in cutoff 100 nA
10 nA 1 nA 100 pA 10 pA
ds
Subthreshold Region
Saturation Region
Vds = 1.8
Subthreshold Slope Vt 0 0.3 0.6 0.9 Vgs 1.2 1.5 1.8
13
Leakage Sources
Subthreshold conduction Transistors cant abruptly turn ON or OFF Junction leakage Reverse-biased PN junction diode current Gate leakage Tunneling through ultrathin gate dielectric Subthreshold leakage is the biggest source in modern transistors
14
Subthreshold Leakage
Subthreshold leakage exponential with Vgs

Vgs Vt
I ds = I ds 0e
nvT
Vds 1 e vT
2 1.8 I ds 0 = vT e
n is process dependent, typically 1.4-1.5
15
DIBL
Drain-Induced Barrier Lowering Drain voltage also affect Vt
Vt = Vt Vds
ttds
VVV
High drain voltage causes subthreshold leakage to ________.
16
DIBL
Drain-Induced Barrier Lowering Drain voltage also affect Vt
Vt = Vt Vds
ttds
VVV
High drain voltage causes subthreshold leakage to increase.
17
Junction Leakage
Reverse-biased p-n junctions have some leakage

D V vT I D = I S e 1
Is depends on doping levels And area and perimeter of diffusion regions 2 Typically < 1 fA/m
p+
n+
n+ p substrate
p+ n well
p+
n+
18
Gate Leakage

Carriers may tunnel thorough very thin gate oxides Predicted tunneling current (from [Song01])
109 106 VDD trend tox 0.6 nm 0.8 nm 1.0 nm 1.2 nm 1.5 nm 1.9 nm
J G (A/cm )
103 100
10-3 10-6 10-9 0 0.3 0.6 0.9 1.2 1.5
1.8
Negligible for older processes May soon be critically important

VDD
19
Temperature Sensitivity
Increasing temperature Reduces mobility Reduces Vt ION decreases with temperature IOFF increases with temperature
I ds
increasing temperature
Vgs
20
So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for

Supply voltage choice Logical effort Quiescent power consumption Pass transistors Temperature of operation
21
Parameter Variation
Transistors have uncertainty in parameters Process: Leff, Vt, tox of nMOS and pMOS Vary around typical (T) values Fast (F) Leff: short Vt: low tox: thin Slow (S): opposite Not all parameters are independent for nMOS and pMOS
fast
FF SF TT
pMOS
FS SS
slow
slow
nMOS
fast
22
Environmental Variation

VDD and T also vary in time and space Fast: VDD: ____ T: ____
Corner F T S 1.8 70 C Voltage Temperature
23
Environmental Variation

VDD and T also vary in time and space Fast: VDD: high T: low
Corner F T S Voltage 1.98 1.8 1.62 Temperature 0C 70 C 125 C
24
Process Corners
Process corners describe worst case variations
If a design works in all corners, it will probably work for any variation.
Describe corner with four letters (T, F, S)

nMOS speed pMOS speed Voltage Temperature
25
Important Corners
Some critical simulation corners include
Purpose Cycle time Power Subthreshold leakage Pseudo-nMOS
nMOS
pMOS
VDD
Temp
26
Important Corners
Some critical simulation corners include
Purpose Cycle time Power Subthreshold leakage
nMOS S F F
pMOS S F F F
VDD S F F ?
Temp S F S ?
Pseudo-nMOS S
27

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Digital Integrated Circuits Lecture 15: Nonideal Transistors

Transistor I-V Review Nonideal Transistor Behavior

Process and Environmental Variations

Ideal Transistor I-V

Shockley 1st order transistor models

0 Vds I ds = Vgs Vt 2 2 Vgs Vt ) ( 2

Vgs < Vt V V < V ds ds dsat Vds > Vdsat

cutoff linear saturation

Ideal vs. Simulated nMOS I-V Plot

BSIM 3v3 SPICE models

Ids ( A ) 250 200 V g s = 1 .8 V g s = 1 .5 V g s = 1 .2 V g s = 0 .9 50 V g s = 0 .6 0 0 0 .3 0 .6 0 .9 V ds 1 .2 1 .5

Simulated nMOS I-V Plot

Electrons: 6-10 x 106 cm/s Holes: 4-8 x 106 cm/s

Vel Sat I-V Effects

Ideal transistor ON current increases with VDD2

Velocity-saturated ON current increases with VDD

cutoff linear saturation

Channel Length Modulation

Reverse-biased p-n junctions form a depletion region

Shorter Leff gives more current

Chan Length Mod I-V

400 300 Vgs = 1.8

Body Effect Model

s = surface potential at threshold

OFF Transistor Behavior

Subthreshold Slope Vt 0 0.3 0.6 0.9 Vgs 1.2 1.5 1.8

Subthreshold leakage exponential with Vgs

n is process dependent, typically 1.4-1.5

Drain-Induced Barrier Lowering Drain voltage also affect Vt

High drain voltage causes subthreshold leakage to ________.

Drain-Induced Barrier Lowering Drain voltage also affect Vt

High drain voltage causes subthreshold leakage to increase.

Reverse-biased p-n junctions have some leakage

10-3 10-6 10-9 0 0.3 0.6 0.9 1.2 1.5

Negligible for older processes May soon be critically important

So what if transistors are not ideal?

They still behave like switches.

But these effects matter for

Process corners describe worst case variations

Describe corner with four letters (T, F, S)

nMOS speed pMOS speed Voltage Temperature

Some critical simulation corners include

Purpose Cycle time Power Subthreshold leakage Pseudo-nMOS

Some critical simulation corners include

Purpose Cycle time Power Subthreshold leakage

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