ARMY INSTITUE OF TECHNOLOGY, PUNE DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

EXPRIMENT NO. 02 Date : TITLE: Study of IC 74LS83 as a BCD Adder AIM: Design and implement single digit BCD adder using binary adder IC. APPARATUS: Digital Trainer kit, IC 7483(4 bit full adder), IC 7408 (Quad Two Input AND Gate), IC 7432(Quad Two Input OR Gate), connectors. THEORY: A BCD adder is a circuit that adds two BCD digits and produces a sum digit also in BCD. BCD addition procedure can be summarized as follows, 1. Add two BCD numbers using normal Binary Addition. 2. If the four bit sum is equal or to less than 9 no correction is needed. The sum is in proper BCD form. 3. It the four-bit sum is greater than 9 or if carry is generated from the four bit sum, the sum is invalid according to BCD form. 4. To correct the invalid sum, Add (0110)2 i.e. 6 to the four bit sum. If carry results from this addition, add it to next higher order BCD digit. Thus to implement BCD adder we require : a. 4 bit binary adder for initial addition. b. Logic circuit to detect sum greater than 9. c. One more 4 bit adder to add (0110)2. IC 7483: A3, A2, A1, A0 and B3, B2, B1, B0 are the input of the IC 7483. Cin represents the carry input while Cout represents carry output.

represents the sum output with

MSB.

BCD adder using two 4-bit binary adder IC 7483. Case I: Sum 9 and carry = 0 The output of combinational circuit y=0. Hence B3 B2 B1 B0 = 0000 for adder 2. Hence output of adder 2 is same as that of adder 1. Case II: Sum > 9 and carry = 0 If S3 S2 S1 S0 of adder 1 is greater than 9, then output Y of combinational circuit becomes 1. Hence B3 B2 B1 B0 = 0110 (of adder 2). Hence six (0110) will be added to sum output of adder 1.

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We get the corrected BCD result at the output of adder 2.

Case III: Sum 9 but carry = 1 As carry output of adder 1 is high, y=1. So B3 B2 B1 B0= 0110 (of adder 2) Hence six (0110) will be added to sum output of adder 1. We get the corrected BCD result at the output of adder 2.

Design Procedure BCD adder: 1. 2. 3. 4. 5. Draw the truth table of the BCD adder and the logic circuit. Make the circuit connections according logical circuit diagram. After implementing the circuit connect Vcc. Verify truth table. Try out the various combinations of BCD numbers which are added by the circuit Observe the logical output. DESIGN FOR BCD ADDER 1. Truth Table for BCD addition

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K-MAP

Y=S4.S3+S3.S2

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PIN CONFIGURATION FOR IC 7483

CIRCUIT DIAGRAM FOR BCD ADDER:

CONCLUSION:

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4 BIT BINARY SUBTRACTOR: To perform binary subtraction with the adder IC, 2s complement logic is applied here. If we want to perform operation (A-B) then in this subtraction A is minuend and B is subtrahend. Following procedure will be takes place : 1. Take 2s complement of subtrahend. 2s complement of any number= 1s complement + 1 2. Add 2s complement of subtrahend in minuend. The circuit for subtracting A-B consists of an adder with inverters, placed between each data input B and the corresponding input of full adder. The input carry C0 must be equal to 1 when performing subtraction. LOGIC DIAGRAM: 4-BIT BINARY SUBTRACTOR

TRUTH TABLE:

ARMY INSTITUE OF TECHNOLOGY, PUNE DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

Input Data A

Input Data B

Subtraction

A4

A3

A2

A1

B4

B3

B2

B1

S4

S3

S2

S1

1 0 0

0 1 1

0 1 1

1 1 0

0 0 0

0 1 0

1 0 0

1 1 1

1 1 1

0 0 0

1 0 1

1 1 0

0 0 1

PROCEDURE: (i) (ii) (iii) RESULT: Make Connections as per given in circuit diagram. Apply Logical inputs as per truth table. Observe the logical output and verify with the truth tables.

CONCLUSION:

ARMY INSTITUE OF TECHNOLOGY, PUNE DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

Oral Question 1. Is carry look ahead generator is possible to draw with half adder? If not then why with full adder only? 2. Write truth table of full substractor. 3. What is glitch? How to avoid it? 4. Why we add 6 to BCD adder. 5. What is disadvantage of 2s complement. 6. In K-MAP why we put the terms as 00 01 11 10 instead of 00 01 10 11 7. Explain why look ahead carry is used in adder 8. Design BCD Adder. 9. What are weighted and nonweighted codes? 10. Define half adder and full adder. 11. Define half subtractor and full subtractor. 12. Draw and explain the block diagram of n-bit parallel adder. 13. Explain the method used for carry look ahead generation. 14. Explain the working of n-bit full subtractor with the help of neat block diagram. 15. What is 1s and 2s complement? 16. What is the difference between 1s and 2s complement? 17. What do you mean by comparator? 18. What is 9s and 10s complement? 19. What is the function of IC 7483? 20. What is positive and negative logic 21. What is SOP and POS. 22. What is use of Excess 3 code. 23. Give the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14. 24. Give 1's and 2's complement of 19. 25. Write 9s and 10s complement of 6.