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Fraunhofer IZM, Germany

23.05.2011

ITRS Packaging Roadmap


M. Jrgen Wolf Fraunhofer IZM, Berlin, Dresden, Germany wolf@izm.fraunhofer.de

Fraunhofer IZM

Moores Law
The observation made in 1965 by Gordon Moore, co-founder of Intel, that the number of transistors per square inch on integrated circuits had doubled every year since the integrated circuit was invented. Moore predicted that this trend would continue for the foreseeable future.

M.J. Wolf

Fraunhofer IZM

Fraunhofer IZM, Germany

23.05.2011

Moores Law Scaling can not maintain the Pace of Progress and Packaging enables equivalent Scaling
Beyond CMOS . . 22nm

32nm 45nm 65nm 90nm


Information Processing Digital content System-on-Chip (SOC)

More Moore : Scaling

Baseline CMOS: CPU, Memory, Logic

Analog/RF

Passives

HV Power

Sensors Actuators

Biochips Fluidics

130nm

More than Moore : Functional Diversification


Interacting with people and environment Non-digital content System-in-Package (SiP)

M.J. Wolf

Fraunhofer IZM

Technology Scenario Driven by Applications


Applications
Transport & Mobility Energy & Environment Health & Care Security & Safety
Communication & Consumer Electronics

Devices
Ultra-small sensor nodes for car networks Tire Pressure Monitoring System (TPMS), Driver assistance Car-to-car/road communication sensors and actuators for air and fuel injection Energy management Efficient power supplies and intelligent stand-by solutions Power IC packaging Digital power conversion Lighting Health monitoring systems Neural implants Hearing devices Visual aids Image sensors Admission control Biometrical control systems RFID systems Navigation systems Wireless communication Localization Portable TV

Required Technologies
Parallel processor, architecture 3D MPUs, GPUs Advanced sensor nodes Distributed Sensor Networks 3D integration with stacked Si devices / MPU, Memory Si-interposer with TSV and integrated passive devices High density and capacity memories Electrical /optical interconnect Multi-functional board with embedded components Heterogenous integration of sensors, memory, processors and power supply

M.J. Wolf

Fraunhofer IZM

Fraunhofer IZM, Germany

23.05.2011

ITRS Roadmapping www.itrs.net


At this time of major shifts in market and technology, ITRS serves the role of up-to-date knowledge base for industry, academia, and research institutes. The ITRS roadmap is a touchstone for industry roadmaps. ITRS would then be a first stop for people who wish to learn about the directions and roadblocks for both near term and long term into the future. Industry can us the roadmap to build their own company roadmaps. Academia and Research Institutes can us it to validate the selection and pacing of new technologies in to the future.

M.J. Wolf

Fraunhofer IZM

ITRS Roadmap Assembly and Packaging Forces of Change


Global Consumer Market Functions & Cost Technology Convergence More Moore & More than Moore

Packaging has become the crucial link in the supply chain Technology Landscape
Redefining WB & FC New Architectures WLP going main stream Embedded technologies SiP + 3D
Fraunhofer IZM

M.J. Wolf

Fraunhofer IZM, Germany

23.05.2011

SiP - System in Package

Horiz ontal P lac ement Wire B onding T ype F lip C hip T ype

Interpos er T ype S tac ked S truc ture Interpos er-les s T ype Wire B onding T ype Wire B onding + F lip C hip T ype

PiP, PoP and more F lip C hip T ype

T erminal T hroug h Via T ype

E mbedded S truc ture

C hip(WL P ) E mbedded + C hip on S urfac e T ype

3D C hip E mbedded T ype

WL P E mbedded + C hip on S urfac e T ype


M.J. Wolf

Fraunhofer IZM

System-in-Package Requirements
Year of Production
Number of terminalslow cost handheld Number of terminalshigh performance (digital) Number of terminalsmaximum RF Low cost handheld / #die / stack high performance / die / stack Low cost handheld / #die / SiP high performance / #die / SiP Minimum component size (micron) Minimum TSV pitch TSV maximum aspect ratio** TSV exit diameter(um) TSV layer thickness for minimum pitch Reflow temperature for Pb free (C)

2009
800 3350 200 9 3 9 6 400x 200 6 10 3 15 245

2011
900 3684 200 11 4 12 7 400x 200 4 10 2 10 245

2013
1000 4053 200 13 5 14 8 200x 100 3,6 10 1,8 10 220

2015
1000 4458 200 14 5 14 8 200x 100 3,3 10 1,6 8 200

2017
1000 4904 200 15 6 15 9 200x 100 2,9 10 1,5 8 180
M.J. Wolf

Fraunhofer IZM

Fraunhofer IZM, Germany

23.05.2011

Packaging Global Changes

2010 Year of Wafer Level Packaging


WLCSP Shipment Growth - 25% WLCSP Fanout High Volume Shipment TSV + Silicon Interposers Embedded Technologies
Source: W.Chen, ASE M.J. Wolf

Fraunhofer IZM

Growth of Wafer Level Chip Scale Packages (WLCSP)


Year 2000 WLCSPs were small, low I/O, expensive, and with limited manufacturing infrastructures

On Semi Analog - ASE TI Nanostar Digital - ASE Vishays Power MOSFET TechSearch Infineon BAW filters TechSearch

Year 2010 Billions shipped, >300 I/Os, Established infrastructure, with high volume manufacturing

Qualcomm 169L WLCSP ASE

Fujitsu Power Management WLCSP 308 L 7.7x7.7mm -TechSearch - TPSS

Broadcom 182L 6.5x6.5 WLCSP ASE

361 L WLCSP ASE

Source: W.Chen, ASE M.J. Wolf

Fraunhofer IZM

Fraunhofer IZM, Germany

23.05.2011

Driving Forces for 3D SiP

Form Factor & Miniaturization Reduced volume and weight Reduced footprint Performance Improved integration density Reduced interconnect length Improved transmission speed Reduced power consumption Heterogeneous Integration & Functionality Mixed functional Integration MEMS, Optical, AD SP, Transceiver Manufacturing Cost Reduction

M.J. Wolf

Fraunhofer IZM

Generations of 3D Packaging / 3D System Integration

We are at the doorstep of the largest shift in the semiconductor industry ever, one that will dwarf the PC and even the consumer electronics era". Dr. Chang-Gyu, Samsung

Package on Package (POP)

Stacked Die

3D IC
Ref. B Chen
M.J. Wolf

Fraunhofer IZM

Fraunhofer IZM, Germany

23.05.2011

3D TSV Roadmap

Source: Yole

M.J. Wolf

Fraunhofer IZM

Wafer-Level-Package for Optical Applications

Tapered Vias & Streets controlled sidewall angle for sribe line controlled sidewall angle for via holes
M.J. Wolf

Fraunhofer IZM

Fraunhofer IZM, Germany

23.05.2011

Si TSV Interposer RF Module

RF Mobile Transceiver (2,4 x 3,6 mm SnAg Solder Bumps (diameter: 50 m) Si Carrier (300 m thickness) TSV (8x8x 300 m) RDL Cu 20 m line /space Solder Balls (diam. 250 m /500 m pitch)

Dimension 7,5mm x 8 mm

F. Binder, IFX

M.J. Wolf

Fraunhofer IZM

3D TSV Approaches
Circuit Level (FE)
Stacked device layer

Wafer Level (BE)


TSV & Stack formation

Package /Board Level


Stacked Package Folded Substrate Die in Board Embedding (CiP) Die in Flex Embedding

ViaDie2Wafer First Stacking


(w/o TSV) W2W Stacking (w TSV) Via Middle Thin Chip Integration (TCI) Embedded Wafer Level Packaging (eWLP) --- IC devices w TSV --- Si Interposer w TSV -

Via Last

M.J. Wolf

Fraunhofer IZM

Fraunhofer IZM, Germany

23.05.2011

Interposer Technology

Source:Yole

M.J. Wolf

Fraunhofer IZM

3D System Architectures TSV Interposer


Top Die (190 m) RDL: T.W/Cu embedded die (35 m) interconnection: TiW/Cu

Base - Die

Interposer with embedded devices in RDL

Interposer with TSV & stacked devices (w TSV)

Silicon interposer as device carrier between devices and package / board for high IO count and high interconnect density (multi-layer (RDL), 5-10 m line/space)

Stacked modular Interposer w. TSV

M.J. Wolf

Fraunhofer IZM

Fraunhofer IZM, Germany

23.05.2011

Through Silicon Via Interposer / HD-Multi Device Carrier


Cu-TSV (> 10000/cm) High density Multi-Layer Redistribution (4 L Cu) Flip chip compatible IO-Pads Cu-Pillar Bumps SnAg Micro Solder Bumps

M.J. Wolf

Fraunhofer IZM

Chip Interconnection
Technology:
Solder, IMC, Cu-Cu, Nano-Interconnects
Cu Al
ILD

Top-Chip (17 m)

Bonding (reflow, TC) Stacking (D2W, D2W) Interconnect structure (Cu, ...)

Cu 3Sn Cu Al

12 m

Bottom Device

Challenges:
Low temperatur bonding fluxfree, self alignment Bonding on carrier vs. wafer Reliability, test, repair Productivity, throughput, yield
Fraunhofer IZM

M.J. Wolf

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Fraunhofer IZM, Germany

23.05.2011

TSV-Interposer
Silicon Interposer Apps#1: high TSV count (>10000/vm) high density TSV (5-10m), small pitch (50m -20m) high density Line/Space multilayer front/back side (#4) electrical & optical Interconnect med. TSV count med. TSV (10-20m), pitch (>100 m) ASR (5-15) multilayer front/back side MEMS integration Cu pillar interface to board/package

Silicon Interposer Apps#2:

Potential:

passive device integration optical interconnects heterogeneous device integration (e.g. TX, MEMS), e.g. thin chip integration thermal management (cooling)
M.J. Wolf

Fraunhofer IZM

Tera-scale Computing

Ref. B Bottems, ITRS

M.J. Wolf

Fraunhofer IZM

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Fraunhofer IZM, Germany

23.05.2011

Roadmap - 3D WL System Integration


3D TCT/TSV Hetero Integration eWLP w TMV Functional Layered Stack eGrain

3D InterconnectComplexity

3D CPUs

eWLP
WLP w. TSV eWLP 3D Interposer w. Cooling

3D Image Sensors

HDI TSV Interposer

Stacked TCI w TSV


Stacked Memory on TSV Interposer Controller / Memory Stacks

IPD & RDL Fraunhofer IZM 08/2009

2005

2006

2007

2008 2009 Year

2010

2012

2014
M.J. Wolf

Fraunhofer IZM

Photonic Packaging @ ITRS

Packaging of optoelectronic and MEMS components has been treated by ITRS in the section ASSEMBLY AND PACKAGING under packaging for specialized functions Optoelectronics packaging covers an expanding range of new technical requirements depending on their applications. Examples of optoelectronic packages and their applications are presented There are many difficult challenges remaining for optical packaging and they will become increasingly critical as the optical communication gets ever closer to the chip. A list of these challenges, technology requirements, potential solutions and the Cross TWG are presented.

Review of Packaging of Optoelectronic,Photonic, and MEMS Components IEEE JSTQE (2011) DOI:10.1109/JSTQE.2011.2113171

Fraunhofer IZM

Research Center of Microperipheric Technologies

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Fraunhofer IZM, Germany

23.05.2011

Silicon Photonics Packaging Concepts by Fraunhofer IZM


Generic-Pack for multiport electrooptic SOI Smart-Pack for (de)multiplexing

T. Tekin, H. Schroeder, L. Zimmermann, P. Dumon, W. Bogaerts "Fibre-array optical interconnection for silicon photonics" Proc. of ECOC, Vol. 5, pp. 93-94 (2008). L. Zimmermann, T. Tekin, H. Schroeder, P. Dumon, W. Bogaerts. "How to bring nanophotonics to application - silicon photonics packaging". LEOS Newsletter December 2008.

Fraunhofer IZM

Research Center of Microperipheric Technologies

Silicon Photonics Packaging Design Rules

Established Silicon Photonics Packaging Design Rules are Pigtailed SOI Chip summarized in following fields: Fiber Pigtailing Flip-Chip & Die Bonding Wire Bonding
fiber-array uv-curing epoxy uv-curing epoxy

SOI chip

Available www.izm.fraunhofer.de/EN/abteilung en/siit/technology/photonic/spic.jsp Hall C1 Booth 312

Fraunhofer IZM

Research Center of Microperipheric Technologies

13

Fraunhofer IZM, Germany

23.05.2011

Summary Assembly & Packaging is converting into complex system Integration Technology ITRS /A&P helps and supports to identify major new developments directions and specifications with respect to the targets of new product generations 3D System Integration (A&P) is an key enabler for the Heterogenous Integration of MEMS, MOEMs, MPUs, ASICs, Memories

M.J. Wolf

Fraunhofer IZM

Wafer Level All Silicon System Integration - ASSID @ FhG IZM


Fraunhofer IZM vision is to integrate heterogeneous chip functionalities into one package (SiP) by using enhanced 3Dintegration, assembly and interconnect technologies.
IZM / ASSID develops leading edge technologies for 3D-WL System-Integration and provide solutions ready for product integration to industrial partners. IZM / ASSID offers capacity and support for equipment and material evaluation to semiconductor industry. IZM / ASSID offers services by using qualified process capacities and demonstrate stable processes on a 300mm TSV process line.

M.J. Wolf

Fraunhofer IZM

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Fraunhofer IZM, Germany

23.05.2011

THANK YOU FOR YOUR ATTENTION


Acknowledgement: TWG A&P ITRS Fraunhofer IZM, TU Berlin IFX, GF, NXP, ASE, Philips, Joule, EMC3D Contact: M. Juergen Wolf wolf@izm.fraunhofer.de
All rights:

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M.J. Wolf
Fraunhofer IZM

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