Beruflich Dokumente
Kultur Dokumente
23.05.2011
Fraunhofer IZM
Moores Law
The observation made in 1965 by Gordon Moore, co-founder of Intel, that the number of transistors per square inch on integrated circuits had doubled every year since the integrated circuit was invented. Moore predicted that this trend would continue for the foreseeable future.
M.J. Wolf
Fraunhofer IZM
23.05.2011
Moores Law Scaling can not maintain the Pace of Progress and Packaging enables equivalent Scaling
Beyond CMOS . . 22nm
Analog/RF
Passives
HV Power
Sensors Actuators
Biochips Fluidics
130nm
M.J. Wolf
Fraunhofer IZM
Devices
Ultra-small sensor nodes for car networks Tire Pressure Monitoring System (TPMS), Driver assistance Car-to-car/road communication sensors and actuators for air and fuel injection Energy management Efficient power supplies and intelligent stand-by solutions Power IC packaging Digital power conversion Lighting Health monitoring systems Neural implants Hearing devices Visual aids Image sensors Admission control Biometrical control systems RFID systems Navigation systems Wireless communication Localization Portable TV
Required Technologies
Parallel processor, architecture 3D MPUs, GPUs Advanced sensor nodes Distributed Sensor Networks 3D integration with stacked Si devices / MPU, Memory Si-interposer with TSV and integrated passive devices High density and capacity memories Electrical /optical interconnect Multi-functional board with embedded components Heterogenous integration of sensors, memory, processors and power supply
M.J. Wolf
Fraunhofer IZM
23.05.2011
M.J. Wolf
Fraunhofer IZM
Packaging has become the crucial link in the supply chain Technology Landscape
Redefining WB & FC New Architectures WLP going main stream Embedded technologies SiP + 3D
Fraunhofer IZM
M.J. Wolf
23.05.2011
Horiz ontal P lac ement Wire B onding T ype F lip C hip T ype
Interpos er T ype S tac ked S truc ture Interpos er-les s T ype Wire B onding T ype Wire B onding + F lip C hip T ype
Fraunhofer IZM
System-in-Package Requirements
Year of Production
Number of terminalslow cost handheld Number of terminalshigh performance (digital) Number of terminalsmaximum RF Low cost handheld / #die / stack high performance / die / stack Low cost handheld / #die / SiP high performance / #die / SiP Minimum component size (micron) Minimum TSV pitch TSV maximum aspect ratio** TSV exit diameter(um) TSV layer thickness for minimum pitch Reflow temperature for Pb free (C)
2009
800 3350 200 9 3 9 6 400x 200 6 10 3 15 245
2011
900 3684 200 11 4 12 7 400x 200 4 10 2 10 245
2013
1000 4053 200 13 5 14 8 200x 100 3,6 10 1,8 10 220
2015
1000 4458 200 14 5 14 8 200x 100 3,3 10 1,6 8 200
2017
1000 4904 200 15 6 15 9 200x 100 2,9 10 1,5 8 180
M.J. Wolf
Fraunhofer IZM
23.05.2011
Fraunhofer IZM
On Semi Analog - ASE TI Nanostar Digital - ASE Vishays Power MOSFET TechSearch Infineon BAW filters TechSearch
Year 2010 Billions shipped, >300 I/Os, Established infrastructure, with high volume manufacturing
Fraunhofer IZM
23.05.2011
Form Factor & Miniaturization Reduced volume and weight Reduced footprint Performance Improved integration density Reduced interconnect length Improved transmission speed Reduced power consumption Heterogeneous Integration & Functionality Mixed functional Integration MEMS, Optical, AD SP, Transceiver Manufacturing Cost Reduction
M.J. Wolf
Fraunhofer IZM
We are at the doorstep of the largest shift in the semiconductor industry ever, one that will dwarf the PC and even the consumer electronics era". Dr. Chang-Gyu, Samsung
Stacked Die
3D IC
Ref. B Chen
M.J. Wolf
Fraunhofer IZM
23.05.2011
3D TSV Roadmap
Source: Yole
M.J. Wolf
Fraunhofer IZM
Tapered Vias & Streets controlled sidewall angle for sribe line controlled sidewall angle for via holes
M.J. Wolf
Fraunhofer IZM
23.05.2011
RF Mobile Transceiver (2,4 x 3,6 mm SnAg Solder Bumps (diameter: 50 m) Si Carrier (300 m thickness) TSV (8x8x 300 m) RDL Cu 20 m line /space Solder Balls (diam. 250 m /500 m pitch)
Dimension 7,5mm x 8 mm
F. Binder, IFX
M.J. Wolf
Fraunhofer IZM
3D TSV Approaches
Circuit Level (FE)
Stacked device layer
Via Last
M.J. Wolf
Fraunhofer IZM
23.05.2011
Interposer Technology
Source:Yole
M.J. Wolf
Fraunhofer IZM
Base - Die
Silicon interposer as device carrier between devices and package / board for high IO count and high interconnect density (multi-layer (RDL), 5-10 m line/space)
M.J. Wolf
Fraunhofer IZM
23.05.2011
M.J. Wolf
Fraunhofer IZM
Chip Interconnection
Technology:
Solder, IMC, Cu-Cu, Nano-Interconnects
Cu Al
ILD
Top-Chip (17 m)
Bonding (reflow, TC) Stacking (D2W, D2W) Interconnect structure (Cu, ...)
Cu 3Sn Cu Al
12 m
Bottom Device
Challenges:
Low temperatur bonding fluxfree, self alignment Bonding on carrier vs. wafer Reliability, test, repair Productivity, throughput, yield
Fraunhofer IZM
M.J. Wolf
10
23.05.2011
TSV-Interposer
Silicon Interposer Apps#1: high TSV count (>10000/vm) high density TSV (5-10m), small pitch (50m -20m) high density Line/Space multilayer front/back side (#4) electrical & optical Interconnect med. TSV count med. TSV (10-20m), pitch (>100 m) ASR (5-15) multilayer front/back side MEMS integration Cu pillar interface to board/package
Potential:
passive device integration optical interconnects heterogeneous device integration (e.g. TX, MEMS), e.g. thin chip integration thermal management (cooling)
M.J. Wolf
Fraunhofer IZM
Tera-scale Computing
M.J. Wolf
Fraunhofer IZM
11
23.05.2011
3D InterconnectComplexity
3D CPUs
eWLP
WLP w. TSV eWLP 3D Interposer w. Cooling
3D Image Sensors
2005
2006
2007
2010
2012
2014
M.J. Wolf
Fraunhofer IZM
Packaging of optoelectronic and MEMS components has been treated by ITRS in the section ASSEMBLY AND PACKAGING under packaging for specialized functions Optoelectronics packaging covers an expanding range of new technical requirements depending on their applications. Examples of optoelectronic packages and their applications are presented There are many difficult challenges remaining for optical packaging and they will become increasingly critical as the optical communication gets ever closer to the chip. A list of these challenges, technology requirements, potential solutions and the Cross TWG are presented.
Review of Packaging of Optoelectronic,Photonic, and MEMS Components IEEE JSTQE (2011) DOI:10.1109/JSTQE.2011.2113171
Fraunhofer IZM
12
23.05.2011
T. Tekin, H. Schroeder, L. Zimmermann, P. Dumon, W. Bogaerts "Fibre-array optical interconnection for silicon photonics" Proc. of ECOC, Vol. 5, pp. 93-94 (2008). L. Zimmermann, T. Tekin, H. Schroeder, P. Dumon, W. Bogaerts. "How to bring nanophotonics to application - silicon photonics packaging". LEOS Newsletter December 2008.
Fraunhofer IZM
Established Silicon Photonics Packaging Design Rules are Pigtailed SOI Chip summarized in following fields: Fiber Pigtailing Flip-Chip & Die Bonding Wire Bonding
fiber-array uv-curing epoxy uv-curing epoxy
SOI chip
Fraunhofer IZM
13
23.05.2011
Summary Assembly & Packaging is converting into complex system Integration Technology ITRS /A&P helps and supports to identify major new developments directions and specifications with respect to the targets of new product generations 3D System Integration (A&P) is an key enabler for the Heterogenous Integration of MEMS, MOEMs, MPUs, ASICs, Memories
M.J. Wolf
Fraunhofer IZM
M.J. Wolf
Fraunhofer IZM
14
23.05.2011
Fraunhofer IZM
M.J. Wolf
Fraunhofer IZM
15