Solution Set for DVD2

1. a. Draw a schematic of a Multiplexed Scan Flip Flop Solution:

(or)

b. Mention any 3 different types of violations possible during Synthesis or PD process & briefly explain them. Solution: Setup time Violation: If setup time is Ts for a flip-flop and if data is not stable before Ts time from active edge of the clock, there is a Setup violation at that flipflop. So if data is changing in the non-shaded area ( in the below figure) before active clock edge, then it's a Setup violation.

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

Hold time violation: If hold time is Th for a flip flop and if data is not stable after Th time from active edge of the clock , there is a hold violation at that flipflop. So if data is changing in the non-shaded area (in the above figure) after active clock edge, then it's a Hold violation. Maximim transition time violation The transition time of a net is the longest time required for its driving pin to change logic values. Transition time is decided on the basis of rise time and fall time. This constraint (max_transition) is based on the library data. For the nonlinear delay model (NLDM), output transition time is a function of input transition and output load. Way to calculate: CMOS delay model: Transition Time = Drive R X Load C Non-linear delay model: Transition Time from table lookup and interpolation/extrapolation. It can make the transition time of each net less than the max_transition value (defined in the library file) by adding a buffer at the output of driving gate. It can vary with the operating frequency of a cell. Since this parameter is based on rise/fall time and rise/fall time is the time required to charge/discharge input capacitance load of the pin. Now if operating frequency vary, the capacitive load vary as per relationship of Xc=1/C . If multiple clocks launch the same paths, the most restrictive value is used. If your design uses multiple technology libraries and each has a different default_max_transition value, synthesis tools uses the smallest max_transition value globally across the design. max_transition is available only for input pin.

2. a. What do the following acronyms stand for i) DFT ii)ATPG iii)PVT Solution: i. ii. iii. DFT : Design For Test ATPG : Automatic Test Pattern Generation PVT : Process Voltage Temperature

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

b. How do you find the max_transition violations in a design. What is the command? Once the violations are found,what is the fix? What are multi-cycle paths, false paths and case-analysis in static timing? Compute setup and hold analysis for the following circuit Solution:

Solution: report_constraints allviolations is the command to find the maximum transition It is fixed using compile_incremental design

Hold Analysis: When a hold check is performed, two things need to be considered: Minimum Delay along the data path and source clock Maximum Delay along the clock path from source to sink If the difference between the data path and the clock path is negative, then a timing violation has occurred. Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter /Inverter->Inverter/->FF2/D *** Assume inverter to inverter minimum wire delay is tmin=1ns *** Delay in Data path = min(wire delay to the clock input of FF1) + min(Clk-to-Q delay of FF1) + 2*min(cell delay of inverter) + min(3 wire delay- "Q of FF1-to-inverter" , inverter to inverter and "inverter-to-D of FF2") Td = 1+9+2(6)+(1+1+1)=25ns *** Assume inverter to inverter to FF2/Clk maximum wire delay is tmax=3ns *** Clock path is: CLK -> buffer -> inverter -> FF2/CLK Clock path Delay = max(wire delay from CLK to Buffer input)+ max(wire delay from Buffer output to inverter input) + max(cell delay of Buffer) + max(cell delay of inverter) + max(wire delay from inverter output to FF2/CLK pin) + (hold time of FF2) Tclk = 3+3+9+9+3+2 = 29 ns Hold Slack = Td - Tclk = 25ns -29ns = -4ns Since Hold Slack is Negative, So there is hold Violation. Setup Analysis: When a setup check is performed, we have to consider two thingsParameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

Maximum Delay along the data path and clock latency to source Minimum Delay along the clock path from source to sink If the difference between the clock path and the data path is negative, then a timing violation has occurred. Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter /Inverter->Inverter/->FF2/D Delay in Data path = max (wire delay to the clock input of FF1) + max(Clk-to-Q delay of FF1) +2*max(cell delay of inverter) + max(3 wire delay- "Q of FF1-to-inverter" , inverter to inverter and "inverter-to-D of FF2") =Td = 2+11+(9+9)+(2+2+2) = 37ns setup time has to be checked at the next clock cycle. *** For that assume clock period is 15ns *** Clock path is: CLK-> buffer->inverter -> FF2/CLK Clock path Delay = (Clock period) + min (wire delay from CLK to Buffer input) + min (wire delay from Buffer output to inverter input) + min(cell delay of Buffer) + min(cell delay of inverter) + min(wire delay from inverter output to FF2/CLK pin) - (Setup time of FF2) Tclk = 15+2+2+5+6+2-4=28ns Setup Slack = Tclk - Td = 28ns - 37ns = -9ns. Since Setup Slack is negative -> Setup violation. One of the possible to solution to overcome setup time violation in the circuit is, take the bigger clock period. Tclk=25+2+2+5+6+2-4=38ns Setup Slack = Tclk - Td = 38ns - 37ns = 1ns Since Setup Slack is positive -> No Setup violation. False Path: In a false path, there is a logical connection from one point to another. Because of the way the logic is designed, this path can never control the timing. Multy Cycle Path: A Multi-cycle path in a design is a Register-to-Register path, through some combinational logic where if the source register changes, the path will require N number of clock cycles (where N>1) before the computation is propagated to the destination register. Case Studies : If there was a class to attend and if the student is late by 2min then he will miss the class where as if it was the lecturer who is late then there is no problem. Comparing this with launch and capture paths. If the launch path is running late then there would be a problem.

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

3. a. Why do we need the function attribute in the .lib files. Explain this with an example. Solution: Synthesis is a process which converts RTL to gate level netlist. Libraries are very much essential in this process of synthesis. Design compiler during this process of synthesis, while converting RTL to Synthesis, DC maps the functionality of the RTL and infers a suitable logic for that corresponding functionality. In this process of inferring suitable gate, the tool matches the RTL functionality to the functionality mentioned in the library and corresponding cell matching the functionality is inferred. Hence function attribute is very much essential to infer correct cell matching the functionality of the logic during synthesis. Logical attributes is also used in STA. b. Does crosstalk increase or decrease as we move from 32nm to 28nm? Which of the following could be an adverse consequence of crosstalk? Identify all applicable effects from the list below i. Excessive power consumption ii. Glitching iii. Some paths slow down iv. Some paths speed up v. Cross correlation between sequential elements vi. Logical disturbance in RAM cells Solution: Cross Talk: Switching of the signal in one net can interfere neighbouring net due to cross coupling capacitance. If capacitance is less Cross Talk is less. If capacitance is more Cross Talk is more C=eA/D Distance between two wires are less in 28 nm as compared to 32nm So that capacitance is high in 28 nm, so cross talk is also high in 28 nm it is not applicable to Cross correlation between sequential elements 4. a. A SOC approaching tapeout has run into hold violations after routing. There were no violations before routing. Which of these causes would have contributed to this? i. The parasitics on the data signals are lower than expected ii. The parasitics on the data signals are higher than expected iii. The post route clock skew does not correlate well to preroute clock uncertainty iv. Input_delay and output_delay increased after routing

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

Solution: The possible reasons for hold violations after routing are both 1 & 3 The parasitics on the data signals are lower than expected & The post Route clock skew does not correlate well to pre-route clock uncertainty b. What is an NLDM? Give an example the values are not important, but identify the axes. Which tools in the IC design flow use it? NLDM is an acronym for Non Linear Delay Model. This is generally used while during the timing analysis of a design. Cell or gate delay is calculated using Non-Linear Delay Models (NLDM). NLDM is highly accurate as it is derived from SPICE characterizations. The delay is a function of the input transition time (i.e. slew) of the cell, the wire capacitance and the pin capacitance of the driven cells. A slow input transition time will slow the rate at which the cells transistors can change state logic 1 to logic 0 (or logic 0 to logic 1), as well as a large output load Cload (Cnet + Cpin), thereby increasing the delay of the logic gate.There is another NLDM table in the library to calculate output transition. Output transition of a cell becomes the input transition of the next cell down the chain.Path delay constitutes of timing paths. Sum of cell and net delay along a timing path constitute of path delay. Cell delay depends on the input transition and output load . The NLDM calculated before and after the layout . DC Compiler & Prime time generally uses it.

5. a. Explain the following terms with pictures and equations/inequalities i. Setup violation ii. Hold violation iii. Clock Skew

Setup violation: Tpd DIN > Tpd Clk

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

For capture the data at the same time when Clock signal (positive clock edge) reaches at pin C, you have to apply the input Data at pin DIN "Ts(in)=(Tpd DIN) - (Tpd Clk)" time before the positive clock edge at pin CLK. Here Time "Ts(in)" is know as Setup time of the System For Setup violation Ts=(TpdMin Clk)- (TpdMax DIN), If result is negative value, then it can consider as Setup time violation Hold violation: Tpd DIN < Tpd Clk For capture the data at the same time when clock signal (positive clock edge) reaches at pin C, input Data at pin DIN should not change before "Th(in)= (Tpd Clk) - (Tpd DIN)" time. If it will change, positive clock edge at pin C will capture the next data. Here time "Th(in)" is know as Hold Time of the System. For Hold violation Th= (TpdMin DIN)- (TpdMax Clk), if result is negative value then,it can consider as a Hold violation Clock Skew: Differences in clock signal arrival times across the chip are called clock skew. It is a fundamental design principle that timing must satisfy register setup and hold time requirements. There are two types of clock skew: negative skew and positive skew. Positive skew occurs when the transmitting register receives the clock earlier than the receiving register. Negative skew is the opposite: the receiving register gets the clock earlier than the sending register.

Fig 1: Sequentially adjacent registers with Clock Skew

Fig 2: Clock arrival time functions in the circuit of Fig 1.

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

b. A design has been synthesized for 300MHz. However, after place and route, the results of Primetime indicate that there is a lot of positive slack. The smallest positive slack is 0.4ns. What is the frequency that this design can run at now? 300 MHz 3.3ns clock. 0.4ns slack => 2.9ns clock (344.8 MHz) Solution: Approx 350Mhz (ok) c. Identify areas of potential congestion in floor plan below. In areas with high congestion, is the correlation to post layout routing better or worse when compared to less congested areas?

Solution:

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

6. We have 20 million (2 crore) paths on our chip. We would like to divide all our paths into 3 categories : those with negative slack, those with positive slack between 0 and 1ns and those with positive slack greater than 1ns. Write pseudocode to generate 20 million random floating point numbers and then bin them into the three categories. Print the number of paths in each category. Check your work as follows : i. No array should be used ii. Single pass, dont iterate multiple times iii. Dont print anything other than the number of paths in each category. iv. Dont Use scanf or swap functions Solution: //variable declaration float slack; int binneg, bin01, bingt1,i; //initialization of variables binneg =bin01 = bingt1=0; for (i=0; i< 20000000; i++) begin slack = random (); //conditional check for categories mentioned if (slack < 0) binneg ++; elseif (slack >1) bingt1++; else bin01++; // do not write >0 && <1 condition as it makes the code less efficient end printf(number of counts for binneg : , %d); a.

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

printf(number of counts for bin01 : , %d); printf(number of counts for bingt1 : , %d); // Do not use multiple loops, as there is no need to store anything. //For this Question, if you are trying to store anything then your code is in trouble. b. What is the difference between the commands get_nets and report_nets. What type of variables do they return? How is their output used? Also what is the difference between report_timing and check_timing in DC/ICC/PT? Solution: report_nets command displays information about the nets in the design of the current instance or in the current design. get_nets command creates a collection of nets in the current design relative to the current instance that match the specified criteria. This command returns a collection if any nets match the specified criteria. If no objects match the criteria, the command returns an empty string. Report_timing command displays the timing information about a design. The report_timing command provides a report of timing information for the current design. By default, the report_timing command reports the single worst setup path in each clock group. The timing report starts by showing the primary command settings, operating conditions, path startpoint, path endpoint, path group name, and path timing check type (max for a setup check, min for a hold check etc. Check_timing checks for the possible problems in setup of the timing analysisin the current design. This command checks the timing attributes placed on the current design and issues warning messages as needed. The messages provide information that identifies and corrects potential errors. The warnings do not necessarily indicate design problems.

7. a. Explain the following commands i. Compile incremental used in DC ii. Report_delay_calculation used in PT iii. Create_mw_lib used in ICC Solution: i. Incremental compile Specifies to attempt only incremental improvements to the gate structure of a design. Portions of a design that are already mapped are exempt from logic-level optimization, and the resulting design should be the same (if no improvements can be made) or better in terms of its design constraints. Implementations for DesignWare operators are reselected in an incremental compile run

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

if the swap can improve the Optimization Cost based on the Optimization constraints on the design. Report_delay_calculation command Displays the actual calculation of a cell or net timing arc delay value. Provides detailed timing calculation information about the specified cell or net timing arc. This information is useful for debugging or verifying timing data in a technology library. Both operating conditions and wire load models are considered when making delay calculations. create_mw_lib Creates a Milkyway library. Atleast one library between -technology and -plib them must be specified. By default, the newly created Milkyway library is not open in the current session. We need to open the milkyway library with this command

ii.

iii.

b. An SOC has a built in Voltage regulator. This Voltage regulator takes a digital code and outputs a voltage level accordingly. There is a bug in that block and all the voltages have shifted up by 15-20%. Think through all the consequences and list them factors to consider are: i. ii. iii. iv. v. Library characterization Speed of the circuits Setup, hold violations Power consumption Reliability

Solution: 1. Library characterization If It will be there in within tolerance limit it will allow that range of voltage, why because in characterization has less entries in corner cases. 2. Speed of the circuit Increases 3. Setup, hold violations It will get worst hold violation, and no setup violation. 4. Power consumption High 5. Reliability Low

8. a. In synthesis, what are the pros and cons of ungrouping hierarchy? How does ungrouping differ from flatten? Solution:

Parameswara Rao P, Vamsi N, Sandeep N

Solution Set for DVD2

Ungroup removes the level of hierarchy . It will Remove a single level of hierarchy from the current design by exploding the contents of the specified cell or cell instance in the current design. Any cells that are marked dont_touch are left undisturbed. Black boxes are also not collapsed. flatten Indicates that the specified cell and all of its subcells are to be exploded recursively until all levels of hierarchy are removed. Flattening reduces the design logic in to a two level, sum-of-products of form, with few logic levels between the input and output. This results in faster logic. It is recommended for unstructured designs with random logic. The flattened design then can be structured before final mapping optimization to reduce area. This is important as flattening has significant impact on area of the design. ungroup flatten all allows the DC to optimize the logic separated by boundaries as one logic resulting in better timing and an optimal solution b. If I have 20,000 Flip flops in my design and max_fanout is set to 4, how many buffers will be needed to construct a clock tree for my design? Solution: 5000 + 1000 + 250 + 60 + 15 +4 General rule divide by 3 c. For the following circuit, what is the pattern that detects a Stuck at 1 fault as shown (in other words, what is the pattern at signals A-E that will bring it out).

Solution:

d : 0/1, a:1, b:1, c:1, e:0.

Parameswara Rao P, Vamsi N, Sandeep N