1.

uvm_component base class DOUBT : When the factory creates this object, it will first search for an instan ce override that matches the full instance name of the object. If no instance-specific override is found, the factory will search for a type-wide override for the type mytype. If no type override is found then the type created will be of type mytype. 2. Advanced sequence control? a. Implementing complex scenarios o Executing sequences concurrently i. fork..join ii. create sequence and start sequence iii. using the pre_body() and post_body() callbacks - above callbacks are invoked only when a sequence is started by its sequence r's start_sequence() task or the sequence's start() task o Interrupt sequences i. An interrupt should eb coupled with some response by the agent. Once the in terrut is serviced, activity prior to the interrupt should be resumed - done using interrupt_handler_sequence(called based on p_sequencer.interrupt , grab(p_sequencer), ovm_do, ungrab), interrupt_clear_sequence(called in fork..j oin_none)

3. uvm_do can be broken in to below 2 lines - uvm_create (sequence_name) - sequence_name.start(p_sequencer) 4. p_sequencer helps avoid type casting and initialize it, it automatically give s required sequencer linked to current sequence UVM Register Layer: (use this in Memory Controller Verification) 1. uvm_reg: Register Abstraction Base Class - A register may be mapped to one or more address maps, each with different ac cess rights and policy. 2. uvm_reg_field UVM Configuration: ----------------1. The env contains configuration properties that enable you to customize the to pology and behavior and make it reusable. 2. uvm_config_db is similar to set_config_int in OVM Ex: uvm_config_db#(bit)::set(this,"*.master0.monitor", "checks_enable", 0);