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Digital Design Lab Manual 2011

Introduction to Verilog
This document uses short examples to demonstrate the basic Verilog syntax, time delays, and concurrent execution features. We have tried to condense all the interesting and hard parts of Verilog into 15 pages and skip all of the boring stuff like the what is the difference between real and integer data types. Studying this document will enable you to model circuits using simple structural and behavioral Verilog code and provide a solid framework for learning all the details of the language. If Verilog is a new language for you we recommend getting a copy of "Verilog HDL" by Samir Plantikar. It is a well organized Verilog textbook that is filled with lots of examples. Why Use Verilog Most Verilog and VHDL books begin with several chapters describing the language's history and advantages. But the arguments boil down to these:

HDL simulators are better then gate level simulators for 2 reasons: portable model development, and the ability to design complicated test benches that react to outputs from the model under test. Finding a model for a unique component for your particular gate level simulator can be a frustrating task, with an HDL language you can always write your own model. Also most gate level simulators are limited to simple waveform based test benches which complicates the testing of bus and microprocessor interface circuits. Verilog is a great low level language. Structural models are easy to design and Behavioral RTL code is pretty good. The syntax is regular and easy to remember. It is the fastest HDL language to learn and use. However Verilog lacks user defined data types and lacks the interface-object separation of the VHDL's entityarchitecture model. VHDL is good for designing behavioral models and incorporates some of the modern object oriented techniques. It's syntax is strange and irregular, and the language is difficult to use. Structural models require a lot of code that interferes with the readability of the model. C++as an hardware modeling language is excellent choice for high-level behavioral analysis of a system (like evaluating different data flow architectures in a microprocessor). However C++ lacks the basic hardware concepts like knowledge of strengths, connections, and concurrent execution which complicates model generation for lower level simulations.

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Choosing Verilog, VHDL, or C++ will be based on availability of tools, models, and inhouse expertise. If you are just learning your first HDL language we recommend Verilog because you will be able to quickly become comfortable with the syntax and timing issues of the language:

Verilog Structure
Verilog differs from regular programming languages (C, Pascal, ...) in 3 main aspects: (1) simulation time concept, (2) multiple threads, and (3) some basic circuit concepts like network connections and primitive gates. If you know how to program in C and you understand basic digital design then learning Verilog will be easy.

Modules
In Verilog, circuit components are designed inside a module. Modules can contain both structural and behavioral statements. Structural statements represent circuit components like logic gates, counters, and microprocessors. Behavioral level statements are programming statements that have no direct mapping to circuit components like loops, ifthen statements, and stimulus vectors which are used to exercise a circuit. A module starts with the keyword module followed by an optional module name and an optional port list. The key word endmodule ends a module.
`timescale 1ns / 1ps //create a NAND gate out of an AND and an Invertor module some_logic_component (c, a, b); // declare port signals output c; input a, b; // declare internal wire wire d; //instantiate structural logic gates and a1(d, a, b); //d is output, a and b are inputs not n1(c, d); //c is output, d is input endmodule

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Structural Design with Gate Primitives and the Delay operator Verilog defines some basic logic gates as part of the language. The module some_logic_component instantiates two gate primitives: the not gate and the and gate. The output of the gate is the first parameter, and the inputs are the rest of the parameters. These primitives are scalable so you can get multiple input gates just by adding inputs into the parameter list. For example:
nand a1(out1, in1, in2); //2-input NAND gate nand a2(out1, in1, in2, in3, in4, in5); //5-input NAND gate notif0 #(10,11,27) inv2(c,d,control) //rise=10, fall=11, off=27(not if

Here is a list of logic primitives defined for Verilog: Gate Parameter List Examples and a1(C,A,B);nand na1(out1,in1,in2,in3,in4);nor #(5) n1(D,A,B);//delay = 5 time unitsxor #(3,4,5) x1(E,A,B);//rise,fall,off delaysnor #(3:4:5) n2(F,A,B);//min:typ:max of delays not inv1(c,a);

scalable, requires at nand nor and least 2 inputs(output, or xor xnor input1, input2, , inputx) not buf notif0bufif0 (output, input)

control signal active low(output, input, notif0 inv2(c,a, control); control) control signal active high(output, input, not inv1(c,a, control); control)

notif1bufif1

Structural Design with Assignment Statements If you have a lot of random logic, the gate primitives of the previous section are tedious to use because all the internal wires must be declared and hooked up correctly. Sometimes it is easier to just describe a circuit using a single Boolean equation. In Verilog, Boolean equations which have similar timing properties as the gate primitives are defined using a continuous assignment statement. For example
wire d; and a1(d, a, b);

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not n1(c, d);

can be replaced with one statement:


assign c = !(a && b); //notice that wire d was not used here

Behavioral Design with Initial and Always blocks Behavioral code is used to describe circuits at a more abstract level then the structural level statements we have studied. All Behavioral code occurs within either an initial block or in an always block. A module can contain several initial and always blocks. These behavioral blocks contain statements that control simulation time, data flow statements (like if-then and case statements), and blocking and non-blocking statements. An initial block executes once during a simulation. Initial blocks are usually used to initialize variables and to describe stimulus waveforms which exercise which drive the simulation. An always block continuously repeats its execution during a simulation. Always blocks usually contain behavioral code that models the actual circuit operation. During a simulation each always and each initial block begin to execute at time zero. Each block executes concurrently with each structural statement and all the other behavioral blocks. The following example shows a behavioral SRAM model. The initial block sets the memory cells to zero at startup. The always block executes each time there is a change on the write control line, the chip select line, or the address bus. As an exercise, copy and paste this code into a verilog file and write a test bench to exercise the model.
//SRAM Model module sram(CSB,WRB,ABUS,DATABUS); input CSB; // active low chip select input WRB; // active low write control input [11:0] ABUS; // 12-bit address bus inout [7:0] DATABUS; // 8-bit data bus //** internal signals reg [7:0] DATABUS_driver; wire [7:0] DATABUS = DATABUS_driver; reg [7:0] ram[0:4095]; // memory cells integer i; initial //initialize all RAM cells to 0 at startup begin DATABUS_driver = 8'bzzzzzzzz; for (i=0; i < 4095; i = i + 1) ram[i] = 0; end

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always @(CSB or WRB or ABUS) begin if (CSB == 1'b0) begin if (WRB == 1'b0) //Start: latch Data on rising edge of CSB or WRB begin DATABUS_driver <= #10 8'bzzzzzzzz; @(posedge CSB or posedge WRB); $display($time," Writing %m ABUS=%b DATA=%b",ABUS,DATABUS); ram[ABUS] = DATABUS; end if (WRB == 1'b1) //Reading from sram (data becomes valid after 10ns) begin #10 DATABUS_driver = ram[ABUS]; $display($time," Reading %m ABUS=%b DATA=%b",ABUS,DATABUS_driver); end end else //sram unselected, stop driving bus after 10ns begin DATABUS_driver <= #10 8'bzzzzzzzz; end end endmodule

Verilog Syntax Details


Our goal up to this point has been to teach you how to model some simple circuits before swamping you with all the details about Verilog types, ports, and numbers. But as we do more Behavioral design it becomes easier to make mistakes in this area. Structural Data Types: wire and reg Verilog supports structural data types called nets which model hardware connections between circuit components. The two most common structural data types are wire and reg. The wire nets act like real wires in circuits. The reg type hold their values until another value is put on them, just like a register hardware component. The declarations for wire and reg signals are inside a module but outside any initial or always block. The initial state of a reg is x unknown, and the initial state of a wire is z. Ports:Modules communicate with each other through ports, the signals listed in the parameter list at the top of the module. Ports can be of type in, out, and inout.

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Here are 3 simplistic rules for matching the structural data type to the type of port: 1. Use reg as the outputs of Behavioral blocks. If you us a wire then the value will never be seen by other blocks. 2. Use wire for all inputs, inouts, and most outputs of Structural elements. 3. If you need a special strength type operation use special net keyword wand, wor, tir, triand, trior, trireg. Behavioral Data Types: integer, real, and time The types in integer and real are convenient data types to use for counting in behavioral code blocks. These data types act like their counter parts in other programming languages. If you eventually plan to synthesize your behavioral code then you would probably want to avoid using these data types because they often synthesize large circuits. The data type time can hold a special simulator value called simulation time which is extracted from the system function $time. The time information can be used to help you debug your simulations. ..... //code fragment from inside a module
integer i, y; real a; real b = 3.5; real c = 4; time simulationTime; initial begin y = 4; i = 5 + y; c = c + 3.5; a = 5.3e4; simulationTime = $time; $display("integer y = %d, i = %f \n", y, i); $display("reals c = %f, a = %e, b= %g \n", c, a, b); $display("time simulationTime = %t \n", simulationTime); end

3.3 Number Syntax Numbers in verilog are in the following format The size is always specified as a decimal number. If no is specified then the default size is at least 32bits and may be larger depending on the machine. Valid base formats are 'b , 'B , 'h , 'H 'd , 'D , 'o , 'O for binary, hexadecimal, decimal, and octal. Numbers consist Dept Of ISE, PESIT 6

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of strings of digits (0-9, A-F, a-f, x, X, z, Z). The X's mean unknown, and the Z's mean high impedance If no base format is specified the number is assumed to be a decimal number. Some examples of valid numbers are:
2'b10 'b10 3 8'hAf -16'd47 // // // // // 2 bit binary number at least a 32-bit binary number at least a 32-bit decimal number 8-bit hexadecimal negative decimal number

3.6 Arrays, Vectors, and Memories Verilog supports three similar data structures called Arrays, Vectors, and Memories. Arrays are used to hold several objects of the same type. Vectors are used to represent multi-bit busses. And Memories are arrays of vectors which are accessed similar to hardware memories. Read the following examples to determine how to reference and use the different data structures.
//*** Arrays for integer, time, reg, and vectors of reg *************** integer i[3:0]; //integer array with a length of 4 time x[20:1]; //time array with length of 19 reg r[7:0]; //scalar reg array with length of 8 c = r[3]; //the 3rd reg value in array r is assigned to c //*** Vectors are multi-bit words of type reg or net (wire)************ reg [7:0] MultiBitWord1; // 8-bit reg vector with MSB=7 LSB=0 wire [0:7] MultiBitWord2; // 8-bit wire vector with MSB=0 LSB=7 reg [3:0] bitslice; reg a; // single bit vector often referred to as a scalar .... //referencing vectors a = MultiBitWord1[3]; //applies the 3rd bit of MultiBitWord1 to a bitslice = MultiBitWord1[3:0]; //applies the 3-0 bits of MultiBitWord1 to bitslice //*** Memories are arrays of vector reg ******************************** reg [7:0] ram[0:4095]; // 4096 memory cells that are 8 bits wide //code excerpt from Chapter 2 SRAM model input [11:0] ABUS; // 12-bit address bus to access all 4096 memory cells inout [7:0] DATABUS; // 8-bit data bus to wite into and out of a memory cell reg [7:0] DATABUS_driver; wire [7:0] DATABUS = DATABUS_driver; //inout must be driven by a wire for (i=0; i < 4095; i = i + 1) // Setting individual memory cells to 0 ram[i] = 0;

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end .... ram[ABUS] = DATABUS; //writing to a memory cell .... DATABUS_driver = ram[ABUS]; //reading from a memory cell

Operators Here is a small selection of the Verilog Operators which look similar but have different effects. Logical Operators evaluate to TRUE or FALSE. Bitwise operators act on each bit of the operands to produce a multi-bit result. Unary Reduction operators perform the operation on all bits of the operand to produce a single bit result. Operator Name ! ~ && & & ~& || | | ~| ^ ^ ~^ ^~ ~^ ^~ == === != !== logical negation bitwise negation logical and bitwise and reduction and reduction nand logical or bitwise or reduction or reduction nor bitwise xor reduction xor bitwise xnor reduction xnor logical equality, result may be unknown if x or z in the if (a == b) input logical equality including x and z logical inequality, result may be unknown if x or z in the input logical inequality including x and z abus = bbus&cbus; abit = &bbus; Examples

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> >> >= < << <= <= relational greater than shift right by a number of positions relational greater than or equal relational less than shift left by a number of positions relational less than or equal if (a <= b) non blocking assignment statement, schedules assignment for future and allows next statement to #5 b <= b + 2; execute blocking assignment statement, waits until assignment #5 a = a + 2; time before allowing next statement to execute a = shiftvalue >> 2;

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How to work with Xilinx
Start ISE from the Start menu by selecting: Start All Programs Xilinx ISE 9.1i Project Navigator Create a new project: 1. Select File > New Project... The New Project Wizard appears. 2. Type lab_two in the Project Name field. 3. Leave the local Project Location for this tutorial. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. (Figure on next page.) 6. Fill in the properties in the table as shown below: Product Category: All Family: Spartan3 Device: XC3S200 Package: FT256 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: Verilog Verify that Enable Enhanced Design Summary is selected. Leave the default values in the remaining fields. 7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete. Create the top-level Schematic source file for the project as follows: 1. Click New Source in the New Project dialog box. 2. Select Verilog Module as the source type in the New Source dialog box. 3. Type in the file name counter. 4. Verify that the Add to Project checkbox is selected. 5. Click Next. 6. Declare the ports for the counter design by filling in the port information as shown below:

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7.

Click Next, then Finish in the New Source Information dialog box to complete the new source file template. 8. Click Next, then Next, then Finish. When you choose the counter.v tab you will see the outline of a Verilog module. Notice that it looks somewhat different than the examples in the textbook. Both methods of listing inputs and outputs are correct! Now fill in the code for the counter as shown below you wont recognize all the commands but for this tutorial just copy what is shown below. module counter(CLOCK, DIRECTION, COUNT_OUT); input CLOCK; input DIRECTION; output [3:0] COUNT_OUT; reg [3:0] count_int = 0; always @(posedge CLOCK) if (DIRECTION) count_int <= count_int + 1; else count_int <= count_int - 1; assign COUNT_OUT = count_int; endmodule

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When the source files are complete save the file and check the syntax of the design to find errors and typos. 1. Verify that Synthesis/Implementation is selected from the drop-down list in the Sources window. 2. Select the counter design source in the Sources window to display the related processes in the Processes window. 3. Click the + next to the Synthesize-XST process to expand the process group. 4. Double-click the Check Syntax process. Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate your design. Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench. Create the test bench waveform as follows: 1. Select the counter HDL file in the Sources window. 2. Create a new test bench source by selecting Project New Source. 3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type counter_tbw in the File Name field. 4. Click Next. 5. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next. 6. The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish. 7. You need to set the clock frequency, setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens. The requirements for this design are the following: The counter must operate correctly with an input clock frequency = 25 MHz. The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The design requirements correspond with the values below. Fill in the fields in the Initialize Timing dialog box with the following information: Clock High Time: 20 ns. Clock Low Time: 20 ns. Input Setup Time: 10 ns. Output Valid Delay: 10 ns.

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Offset: 0 ns. Global Signals: GSR (FPGA) Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically. Initial Length of Test Bench: 1500 ns. Leave the default values in the remaining fields.

8. Click Finish to complete the timing initialization. 9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows: Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up. Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the counter will count down.

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10. Save the

waveform. 11. In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project. Verify that the counter design functions as you expect by performing behavior simulation as follows: 1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources window. 2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench. 3. To view your simulation results, select the Simulation tab and zoom in on the transitions. Note: by selecting COUNT_OUT and right-clicking you can change the hex version to decimal. You can expand COUNT_OUT to see the individual counter bits.

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Lab Experiments
1. Implementation of all basic gates Logic Gate Symbols Truth Tables

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Verilog Code Verilog code for AND GATE module and12(a,b,c); input a; input b; output c; assign c = a & b; endmodule Verilog code for NAND GATE module nand12(a,b,e); input a; input b; output e; assign e = ~(a & b); endmodule Verilog code for XNOR GATE module xnor12(a,b,i); input a; input b; output i; assign i = ~(a ^ b); endmodule Verilog code for NOT GATE module not12(a,g); input a; output g; assign g = ~a;

Verilog code for OR GATE module or12(a,b,d); input a; input b; output d; assign d = a | b; endmodule Verilog code for XOR GATE module xor12(a,b,h); input a; input b; output h; assign h = a ^ b; endmodule Verilog code for NOR GATE module nor12(a,b,f); input a; input b; output f; assign f = ~(a | b); endmodule

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endmodule 2. Implementation of Half adder & Full Adder A) Half Adder Truth Table Input A B 0 0 0 1 1 0 1 1 Output S(Sum) C(Carry) 0 0 1 0 1 0 1 1 Graphical Notation

Circuit Diagram

Equations S (Sum) =A^B C (Carry) =AB Verilog code for Half adder module hadd(a,b,s,c); input a; input b; output s; output c; assign s = a ^ b; assign c = a & b; endmodule B)Full Adder Truth Table
Input A 0 0 0 0 1 1 1 B 0 0 1 1 0 0 1 C 0 1 0 1 0 1 0 Output SUM 0 1 1 0 1 0 0 Cout 0 0 0 1 0 1 1

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1 1 1 1 1

K- Map for sum

K-map for Carry

SUM = ABC + ABC + ABC + ABC SUM= A^B^C

Cout = ABC + ABC + ABC +ABC Cout= (A^B)C+AB

Circuit Diagram

Verilog code for Full adder module fadd(a,b,c,s,cout); input a; input b; input i; output s; output cout; assign s = (a ^ b) ^ c; assign cout = (a & b)|( b & c)|(c & a); endmodule C) Full Adder Using Two Half Adders and one OR gate Circuit Diagram

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Verilog code for Full adder using half adder module fadd(a,b,ci,s,co); input a; input b; output s; output cout; wire c1,c2,s1 HA 1(s1,c1,a,b); HA 2(s,cout,c1,s1) endmodule module HA(s,c,a,b); input a,b; output s,c; s=a^b; c=ab; endmodule

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3 Implementation of 1:4 and 4:1 Multiplexer A) 4:1 Multiplexer
Function Table Selection output Inputs S1 S0 0 0 D0 0 1 D1 1 0 D2 1 1 D3

Block Diagram 4:1 Multiplexer

Circuit Diagram 4:1 Multiplexer

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Verilog code 4 to 1 for multiplexer

module mux4to1(Y, I0,I1,I2,I3, sel); output Y; input I0,I1,I2,I3; input [1:0] sel; reg Y; always @ (sel or I0 or I1 or I2 or I3) case (sel) 2'b00:Y=I0; 2'b01:Y=I1; 2'b10: Y=I2; 2'b11: Y=I3; default: Y=2b00; endcase endmodule B)1:4 Demultiplexer
Function table Data Input D 1 1 1 1 Selection Input S1 S0 0 0 0 1 1 0 1 1 Output Y3 0 0 0 1 Y2 0 0 1 0 Y1 0 1 0 0 Y0 1 0 0 0

Function Table Inputs S1 0 0 1 1 S0 0 1 0 1 Y0=D Y1=D Y2=D Y3=D Output

Block Diagram 1:4 Demultiplexer

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Circuit Diagram 1:4 Demultiplexer

Verilog code for 1 to 4 demultiplexer module demux(S,D,Y); Input [1:0] S; Input D; Output [3:0] Y; reg Y; always @(S OR D) case({D,S}) 3b100:Y=4b0001; 3b101:Y=4b0010; 3b110:Y=4b0100; 3b111:Y=4b1000; default:Y=4b0000; endcase endmodule

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4. Implementation of encoder (with and without priority) and Decoder A)3-8 line Decoder
Function Table enable 0 1 1 1 1 1 1 1 1 A1 x 0 0 0 0 1 1 1 1 Input A1 x 0 0 1 1 0 0 1 1 A0 x 0 1 0 1 0 1 0 1 Z7 0 0 0 0 0 0 0 0 1 Z6 0 0 0 0 0 0 0 1 0 Z5 0 0 0 0 0 0 1 0 0 Z4 0 0 0 0 0 1 0 0 0 Output Z3 0 0 0 0 1 0 0 0 0 Z2 0 0 0 1 0 0 0 0 0 Z1 0 0 1 0 0 0 0 0 0 Z0 0 1 0 0 0 0 0 0 0

Block Diagram 3-8 line Decoder Z7 A0 A1 A2 3 to 8 line decoder Enable Z6 Z5 Z4 Z3 Z2 Z1 Z0

Circuit Diagram 3-8 line Decoder

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Verilog Code for 3 to 8 line decoder Module dec(bin,decout,en); input [0:2] bin; input en; output [7:0] decout; reg decout; always @(en or bin) begin decout=0; if(en) begin case(bin) 3b000:decout=8o001; 3b001:decout=8o002; 3b010:decout=8o004; 3b011:decout=8o010; 3b100:decout=8o020; 3b101:decout=8o040; 3b110:decout=8o100; 3b111:decout=8o200; endcase end end endmodule B)8:3 line encode(Octal-Binary Conversion) Function Table Input I3 x 0 0 0 1 0 0 0 0

enable 0 1 1 1 1 1 1 1 1

I7 x 0 0 0 0 0 0 0 1

I6 x 0 0 0 0 0 0 1 0

I5 x 0 0 0 0 0 1 0 0

I4 x 0 0 0 0 1 0 0 0

I2 x 0 0 1 0 0 0 0 0

I1 x 0 1 0 0 0 0 0 0

I0 x 1 0 0 0 0 0 0 0

Y2 0 0 0 0 0 1 1 1 1

Y1 0 0 0 1 1 0 0 1 1

Y0 0 0 1 0 1 0 1 0 1

Y0 = I1 + I3 + I5 + I7 Y1= I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 +I7 Block Diagram8:3 line encoder(Octal-Binary Conversion) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Dept Of ISE, PESIT Z0 Enable 8 to 3 line decoder A0 A1 A2

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Circuit Diagram8:3 line encoder (Octal-Binary Conversion)

Verilog Code for Encoder module encodeR(I0,I1,I2,I3,Y0,Y1,Y3); input I0,I1,I2,I3; output Y0,Y1,Y3; wire Y0,Y1,Y3;

Y0 = I1 | I3 | I5| I7 Y1= I2 |I3 | I6 | I7 Y2 = I4 | I5 | I6 |I7 endmodule C)Priority Encoder


Function Table

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K-Map simplification

Y0=D3+D1D2 Y1=D2+D3 V=D0+D1+D2+D3 Circuit Diagram

Verilog Code priority encoder module encodeR(D0,D1,D2,D3,Y0,Y1,V3); input I0,I1,I2,I3; output Y0,Y1,Y3; wire Y0,Y1,V; Y0=D3|D1|~D2 Y1=D2|D3 V=D0|D1|D2|D3 endmodule

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5 Implementation of BCD Adder K 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Binary Sum Z8 Z4 Z2 Z1 C 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 BCD Sum S8 S4 S2 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 Decimal S1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Truth Table

Circuit Diagram

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C= K+ Z1Z3+ Z2Z3 Verilog Code for BCD adder module bcd_adder(sum,output_carry,addend,augend,carry_in); output [3:0] sum; output output_carry; input [3:0] addend; input [3:0] augend; input carry_in; wire [3:0] z_addend; wire carry_out; wire c_out; wire [3:0] z_sum; adder_4bit m0(carry_out,z_sum,addend,augend,carry_in); and (w1,z_sum[3],z_sum[2]); and (w2,z_sum[3],z_sum[1]); assign z_addend={1b0,output_carry,output_carry,1b0); or(output_carry,carry_out,w1,w2); adder_4bit(c_out,sum,z_addend,z_sum,1b0); or(c_out,carry_out,c_out); endmodule module adder_4bit(carry,sum,a,b,cin); output carry; input [3:0] sum; input [3:0] a,b; input c_in; assign {carry,sum}=a+b+cin; endmodule

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6 Implementation of 4-bit Magnitude Comparator Consider two 4-bit binary numbers A and B such that A = A3A2A1A0 B = B3B2B1B0 (A = B) = x3x2x1x0

Circuit Diagram

Verilog code(Abstract level) module compare(A,B,y); input [3:0] A,B; output [2:0] y; reg y; always @(A or B) if(A==B) y=3b001; else if(A<B) y=3b010; else y=3b100;

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endmodule Verilog code for 4-bit magnitude comparator module compare(A,B,x,y,z); input [3:0] A,B; output x, y,z; wire x0,x1,x2,x3; assign x0=((~A[0]&B[0])| (A[0]&~B[0])); assign x1=((~A[1]&B[1])| (A[1]&~B[1])); assign x2=((~A[2]&B[2])| (A[2]&~B[2])); assign x3=((~A[3]&B[3])| (A[3]&~B[3])); assign x=x0&x1&x2&x3; assign y=((A[3]&~B[3]|(x3&A[2]&~B[2])|(x3&x2&A[1]&~B[1])|(x3&x2&x1&A[0]&~B[0])); assign z=((~A[3]&B[3]|(x3&~A[2]&B[2])|(x3&x2&~A[1]&B[1])|(x3&x2&x1&~A[0]&B[0])); endmodule

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7 Implementation of Flip flops [JK, D and T].
A)JK Flip-Flop Circuit Diagram

Graphical Notation

Characteristic Table Input J x 0 0 1 1 Characteristic Equation Q(t+1)=JQ(t)+KQ(t) K x 0 1 0 1

Input CP 0

Output Q(t+1) No Change Q(t) 0 1 Q(t)

Verilog code for JK flip flop module jkff(jk,pst,clr,clk,qp,qbar); input [1:0] jk; input pst,clr,clk; output qp,qbar; reg qp; wire q; always @ (posedge clk) if (pst) qp= 1; else begin if (clr) qp= 0; else begin case (jk) 2'b00: qp=q;

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2'b01 : qp = 1'b0; 2'b10 : qp =1'b1; 2'b11 : qp = ~q; default qp =0; endcase end

end assign qbar = ~q; assign q = qp; endmodule


B)D-Flip Flop Circuit Diagram

Graphical Notation

Characteristic Table Input D x 0 1 Characteristic Equation Q(t+1)=D

Clock Input CP 0/1

Next State Q(t+1) No Change 0 1

Verilog code for D flip flop: module dff(d,clk,q,qbar); input d; input clk; output q,qbar; reg q, qbar; always @ (posedge clk) begin q = d; qbar = ~d; Dept Of ISE, PESIT 32

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end endmodule
C)T-Filp Flop Circuit Diagram

Graphical Notation

Characteristic Table Input T x 0 1 Characteristic Equation Q(t+1)=TQ(t)+TQ(t) Clock Input CP 0/1 Next State Q(t+1) No Change Q(t) Q(t)

Verilog code for T flip flop: module tffeq(t,rst, clk,qp, qbar); input t,rst, clk; output qp, qbar; wire q; reg qp; always @ (posedge clk) if (rst) qp=0; else qp = q ^ t; assign qbar = ~ qp; endmodule

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8 Implementation of counters [Ripple, up down].
A) 4-Bit Binary Ripple Counter Function Table A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Circuit Diagram B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Output(count 0-15) C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Verilog Code for Ripple Counter module ripple(clkr,st,,t,A,B,C,D); input clk,rst,t; output A,B,C,D; Tff T0(D,clk,rst,t); Tff T1(C,clk,rst,t); Tff T2(B,clk,rst,t); Tff T3(A,clk,rst,t); endmodule module Tff(q,clk,rst,t); input clk,rst,t; output q; reg q; always @(posedge clk) begin if(rst) q<=1b0; else if(t)

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q<=~q; end endmodule B)4-bit Up-Down Counter Count Table Output(count down) Q0 Q1 Q2 Q3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output (count up) Q1 Q0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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Circuit diagram

Verilog code for up-down counter module updowncount (R, Clock, clr, E, up_down, Q); parameter n = 4; input [n-1:0] R; input Clock, clr, E, up_down; output [n-1:0] Q; reg [n-1:0] Q; integer direction; always @(posedge Clock) begin if (up_down) direction = 1; else direction = -1; if (clr) Q <= R; else if (E) Q <= Q + direction; end endmodule

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9) Implementation of counters [Ring, Johnson]. A)Ring Counter Circuit Diagram for ring counter

Count Table

clk Qa 1 2 3 4 1 0 0 0

Qb 0 1 0 0

Qc 0 0 1 0

Qd 0 0 0 1

Verilog code for ring counter

module ring_count (Resetn, Clock, Q); parameter n = 5; input Resetn, Clock; output [n-1:0] Q;

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reg [n-1:0] Q; always @(posedge Clock) if (!Resetn) begin Q[4:1] <= 0; Q[0] <= 1; end else Q <= {{Q[3:0]}, {Q[4]}}; endmodule
B)Johnson Counter Circuit Diagram for Johnson counter

outputs
Vcc 14 QA 13 QB 12 QC 11 QD 10 CLK1 9 8

74LS95

2 A

3 B

4 C

5 D

A1A

Count Table

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Verilog code

module stc(clk,clr,q,r,s,t); input clk,clr; output q,r,s,t; reg q,r,s,t; always@(negedge clk) begin if(~clr) begin q=1'b0; end else begin q<=~t; r<=q; s<=r; t<=s; end end endmodule

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10 Implementation of 4- bit serial adder Circuit Diagram for 4-bit serial adder

Verilog Code for serial adder module serial_adder(a,c,clk,rst,pl,si,sr,qout,p0); input clk,rst,si,sr,pl; output qout; output [3:0] p0; reg [3:0] sra; reg [3:0] srb; input [3:0] a; input [3:0] b; reg p0; wire s,c; FA f1(sra[0].srb[0],qout,s,c); always @ (posedge clk) begin if(rst) begin sra=4b0000; srb=4b0000; qout=0; p0=4b0000; end else if(pl) begin sra=a;

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srb=b; end else if(sr) begin sra={s,sra[3:1]}; srb={si,srb[3:1]}; qout=c; end; else qout=qout; p0=sra; end endmodule Fulladder module module FA(a,b,c,s,c); input a,b,c; output s,c; assign s=a^b^c; assign c=((a^b)&c)|(a&b); endmodule

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11 Implementation of universal shift register.
Circuit Diagram for universal shift register

Function Diagram

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Notes H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q,d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW-to-HIGH CP transition X = dont care = LOW-to-HIGH CP transition

Verilog Code module uni_shift(out,l0,r0,in,li,ri,s,clr,clk); output [3:0] out; output l0,r0; input [3:0] in; intput [1:0] s; input li,ri,clr,clk; reg out; assign l0=out[3]; assign r0=out[0]; always @ (posedge clk) begin if(clr) out<=0; else case(s) 3:out<=in; 2:out<={out[2:0],ri}; 1:out<={li,out[3:1]}; 0:out<=out; endcase end endmodule

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12 Implementation of Sequential Binary Multiplier.


Inputs: A: First 4-Bit operand (multiplier). B: Second 4-Bit operand (multiplicand). S: Start signal which initiates the multiplication operation Reset: Reset signal which puts the controller into the initial state. Outputs: P: The 8-bit product result (P = A x B).

Block Diagrm

Binary Multiplication

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Multiplier Data Path

The data path for the sequential multiplier is consists of several registers and an adder. The required registers include: B-Register: A 4-bit register which holds the multiplicand (B) P-Register: An 8-bit register which consists of two 4-bit registers PL (P-Low) and PH (P-High). o Initially the multiplier (A) is loaded in PL, while PH is cleared o The final result (product) is stored in P = (PH, PL). E-Register: A 1-bit register, that is used to hold the carryout output of the adder o Initially E is cleared th o It may be considered the 9 Bit of P, i.e. P8. o In the final step, E will hold a 0 value. Cnt: A 2-bit down counter used to control the number of steps to be performed (total of 4 steps). The counter counts from 3 down to 0. The operation is stopped when the count reaches 0. This zero condition (Zero) is detected by a NOR gate Notation: (E, PH) refers to the 5-bit register consisting of E as the MSB and PH. (E, PH, PL) refer to the 9-bit register consisting of E as the MSB, PH. and PL. Computation Steps: 1. Initialize: i=0, PH ? 0, PL ? A, B-Reg ? B, Cnt ? n-1, where n = number of Dept Of ISE, PESIT 45

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operand bits. 2. (E,PH) ? PH + aiB = PH + P0B; 3. Shift (E, PH, PL) right by one bit; Cnt ? Cnt -1; and i=i+1. 4. IF Cnt = 0 then STOP else Loop back to step 2 Example: A=1011, B=1101, then n = 4. 1. Initialization: P = (PH, PL) = 0000_1011 B = 1101 Cnt = 3 i = 0 2. E, PH ? PH + P0B = (0000) + (1101) = 01101 (E, PH, PL) = (0, 1101, 1011) 3. Shift P Right -- P = (0110, 1101) , Cnt = 2, and i=1 4. E, PH ? PH + P0B = (0110) + (1101) = 10011 (E, PH, PL) = (1, 0011, 1101) 5. Shift P Right -- P = (1001, 1110) , Cnt = 1, and i=2 6. E, PH ? PH + P0B = (1001) + (0000) = 01001 (E, PH, PL) = (0, 1001, 1110) 7. Shift P Right -- P = (0100, 1111) , Cnt = 0, and i=3 (Note that Cnt becomes 0 only after the next clock not while being in state S2) 8. E, PH ? PH + P0B = (0100) + (1101) = 10001 (E, PH, PL) = (1, 0001, 1111) 9. Shift P Right -- P = (1000, 1111) , Cnt = 0 10. STOP.

Verilog code module mult(product,ready,multiplicand,multiplier,start,clock,reset_b); parameter dp_width=5; output [2*dp_width-1:0] product; output ready; input [dp_width-1:0] multiplicand,multiplier; input start, clock,reset_b; parameter bc_size=3; parameter s_Idle=3'b001; parameter s_add=3'b010; parameter s_shift=3'b100; reg [2:0] state,next_state; reg [dp_width-1:0] A,B,Q; reg c; reg [bc_size-1:0] p; reg load_regs,dec_p,add_regs,shift_regs; // miscellaneous combinational logic assign product={A,B}; wire zero=(p==0); //zero=~p; wire ready=(state==s_idle); // control unit

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always @ (posedge clock, negedge reset_b) if(~reset_b) state<=s_idle; else state<=next_state; always @ (state,start,Q[0],zero) begin next_state=s_idle; load_regs=0; decr_p=0; add_regs=0; shift_regs=0; case(state) s_idle:begin If(start) Next_state=s_add; load_regs=1; end s_add: begin next_state=s_shift; decr_p=1; if(Q[0]) add_regs=1; end s_shift: begin shift_regs=1; if(zero) next_state=s_idle; else next_stae=s_add; end default: next_state=s_idle; endcase // data unit always @(posedge clock) begin if(load_regs) begin p<=dp_width; A<=0; C<=0;

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B<=multiplicand; Q<=multiplier; end if(add_regs) {C,A}=A+B; If(shift_regs} {C,A,Q}<={C,A,Q}>>1; If(decr_p) p<=p-1; end endmodule

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