THE OPTIMUM PIPELINE DEPTH FOR A MICROPROCESSOR-PAPER REVIEW NAME: Sidhaarth Vaithisankaran UIN : 655715902

The paper has been presented to find the optimum pipelining depth in a microprocessor which will give the best performance. The factors which affect the performance of the processor is analyzed and a formula for calculating the optimum pipeline depth is derived. Then a simulation tool was designed to calculate the same value. And finally the results of the theoretical and the simulation tool is compared. This process was repeated for N number of applications and for different classes of workloads. The results show that increasing the pipeline depth and limiting the number of pipeline stalls results in an optimum pipeline depth. The depth depends on the microarchitecture of the processor, technology used to build the processor and the workload run in the processor. The most important idea is the greater throughput of the deeper pipeline and larger penalty of hazards in the deeper pipelines. This tradeoff leads to an optimum design point. The depth is calculated by analyzing how the processor spends its time. (i.e.) the time for which the execution unit is doing useful work and the time for which the execution is stalled by the number of pipeline hazards. Then the final performance measure is calculated by dividing the total time by the number of instructions. The main strength of this paper is that, the optimum depth of the pipeline is calculated by both theoretical and simulation methods and the results are cross verified. The process is also repeated for various applications representing different classes of workloads. This means that all the possibilities are calculated and compared thoroughly before the final value is decided. The main weakness of this paper is that there was no mention whether the instruction processing is in-order or out-of-order. It was assumed that the outof-order does not change the analysis. But degree of superscalar processing will be altered with out-of-order processing. Also the effective penalty inferred from various hazards will be reduced by using out-of-order processing. There is no detail of how the simulation tool is designed and used. How to expand the processor pipeline in a uniform manner.

If I were the author of this paper, in my next paper I would do a research and get a thorough understanding about multicore processors and multithreading where the instructions from other programs can be pipelined other than the instructions queued down from the same program during delays to improve the performance and speed of the system.