Test Paper-1 analog and digital electronics

Source Book: GATE Multiple Choice Questions Electrical Engineering (Vol-1 and Vol-2) Author: RK Kanodia & Ashish Murolia ISBN: 9788192276212, 9788192276229 Publisher : Nodia and Company Visit us at: www.nodia.co.in Edition: 1st

Q. No. 1 - 10 Carry One Mark Each

MCQ 1.1

Consider the given a circuit and a waveform for the input voltage. The diode in circuit has cutin voltage V = 0 .

The waveform of output voltage vo is

SOL 1.1

Hence (C) is correct option. Diode will be off if vi + 2 > 0 . Thus vo = 0 For vi + 2 < 0 V, vi < 2, vo = vi + 2 = 3 V In the shunt regulator shown below, the VZ = 8.2 V and VBE = 0.7 V. The regulated output voltage Vo is

MCQ 1.2

www.gatehelp.com
Page 2 analog and digital electronics Test Paper-1

(A) 11.8 V (C) 12.5 V

SOL 1.2

(B) 7.5 V (D) 8.9 V

Hence (D) is correct option. Vo = VZ + VBE = 8.2 + 0.7 = 8.9 V A four-variable switching function has minterms m6 and m 9 . If the literals in these minterms are complemented, the corresponding minterm numbers are (A) m 3 and m 0 (B) m 9 and m6 (C) m2 and m 0 (D) m6 and m 9

MCQ 1.3

SOL 1.3

Hence (B) is correct option. m6 = ABCD , m 9 = ABC D After complementing literal ml 6 = ABC D = m 9 , ml 9 = ABCD = m 6 In the given circuit of figure if VTH = 0.4 V, the transistor M1 is operating in

MCQ 1.4

(A) Linear region (C) M1 is off

SOL 1.4

(B) Saturation region (D) Cannot be determined

Hence (B) is correct option. For P -channel MOSFET VSD (sat) = VSG + VTH = (1 0) 0.4 = 0.6 VSD = VS VD = 1 0.3 = 0.7 Here, VSD > VSD (sat) So, M1 is in saturation region.

www.gatehelp.com
Page 3 analog and digital electronics Test Paper-1

MCQ 1.5

The network shown below implements

(A) NOR gate (C) XOR gate

SOL 1.5

(B) NAND gate (D) XNOR gate

Hence (B) is correct option. f1 = C D + CB + CB , S = F1 f = f1 + f1 A = CB + CBA = CB + A = C + B + A = ABC Which of the following amplifier has high input impedance, low output impedance and low voltage gain (A) Common-gate (B) Common-Drain (C) Common-Source (D) None of these

MCQ 1.6

SOL 1.6

Hence (B) is correct option. For common drain amplifier output impedance, Ro = 1 (low) gm Input impedance Rin = 3 (high) gm R L Voltage gain . 1 (low) (Av) = 1 + gm R L Which one of the following is NOT a vectored interrupted ? (A) TRAP (B) INTR (C) RST 3 (D) RST 7.5

MCQ 1.7

SOL 1.7

Vectored interrupts are those interrupts in which program control transfer to a fixed location. In non vectored interrupts the location is not fixed. Here INTR is a non-vectored interrupt. Hence (B) is correct option. For the circuit shown below the value of Av = vo is vi

MCQ 1.8

www.gatehelp.com
Page 4 analog and digital electronics Test Paper-1

(A) 10 (C) 13.46

SOL 1.8

(B) 10 (D) 13.46

Hence (A) is correct option The noninverting terminal is at ground level. Thus inverting terminal is also at virtual ground. There will not be any current in 60 k . Av = 400 = 10 40 For the circuit shown below the true relation is

MCQ 1.9

(A) vo1 = vo2 (C) vo = 2vo2

SOL 1.9

(B) vo1 = vo2 (D) 2vo1 = vo2

At second stage input to both op-amp circuit is same. The upper op-amp circuit is buffer having gain Av = 1. Lower op-amp circuit is inverting amplifier having gain Av = R = 1. Therefore vo1 = vo2 . R Hence (B) is correct option. 11001, 1001 and 11001 correspond to the 2s complement representation of the following set of numbers (A) 25, 9 and 57 respectively (B) 6, 6 and 6 respectively (C) 7, 7 and 7 respectively (D) 25, 9 and 57 respectively All are 2s complement of 7 00110 & 11001 + 1 00111 = 7 10

MCQ 1.10

SOL 1.10

www.gatehelp.com
Page 5 analog and digital electronics Test Chapter Paper-1 1

1001

&

0110 + 1 0111

= 7 10

111001

&

000110 + 1 000111 = 7 10

Hence (C) is correct option.

Q. No. 11- 21 Carry Two Mark Each

MCQ 1.11

Consider the following loop LXI H, 000AH LOOP : DCX B MOV A, B ORA C JNZ LOOP This loop will be executed (A) 1 time (C) 11 times

(B) 10 times (D) infinite times

SOL 1.11

Hence (B) is correct option. LXI B, 000 AH LOOP : DCX B

MOV A, B ORA C JNZ LOOP Hence this loop will be executed 0AH or ten times. Hence (B) is correct option.
MCQ 1.12

; ; ; ; ;

00 " C, 0AH " B CB - 1 " B, flag not affected B"A A OR C " A, set flag

The analog multiplier X shown below has the characteristics v p = v1 v2 . The output of this circuit is

www.gatehelp.com
Page 6 analog and digital electronics Test Paper-1

SOL 1.12

(A) vs vss (C) vs vss Hence (C) is correct option. v + = 0 = v , Let output of analog multiplier be v p . vs = v p & v = v , v = v v s p p ss o R R vs = vss vo , vo = vs vss

(B) vs vss (D) vs vss

MCQ 1.13

For the circuit shown below the value of io is

(A) 12 mA (C) 6 mA
SOL 1.13

(B) 8.5 mA (D) 7.5 mA

The circuit is as shown below

v+ = v = 0, i1 = 12 = 3 mA 4k i2 = 3 + 2 = 5 mA , vo = (5) (3) = 15 V

www.gatehelp.com
Page 7 analog and digital electronics Test Paper-1

i2 = io + iL , 5 = io + 15 , 6 io = 7.5 mA Hence (D) is correct option.

MCQ 1.14

For the op-amp circuit shown below the voltage gain Av = vo /vi is

(A) 8 (C) 10
SOL 1.14

(B) 8 (D) 10

The circuit is as shown below

0 v i + 0 v1 = 0 , R R v1 = vi v1 0 + v1 v 2 + v1 = 0 , R R R 3v1 = v2, v2 = 3vi v2 v1 + v2 + v2 vo = 0 r R R 3vi + vi 3vi 3vi = vo vo = 8 vi

&

Hence (A) is correct option.

MCQ 1.15

Consider a binary weighted n -bit D/A converter shown in the following circuit of figure. What is the tolerance of resistance to limit the output error to the

www.gatehelp.com
Page 8 analog and digital electronics Test Paper-1

equivalent of ! 1 LSB ? 2

(A) (C)

1 2n 1
n1

(B) 1n 2 (D) 1 2n + 1

SOL 1.15

2 Required error in MSB # 1/2 LSB Let ! x % is the tolerance in resistance

V V # 1 nV 2 2 1R R R 1+ x a k 100 x a1 + 100 k 1 # 1n x 2 a1 + 100 k x 2n # 1 + x , x (2n 1) # 1 100 # 100 100 x # n 1 # 100 2 1 Hence (A) is correct option.
MCQ 1.16

Consider the common-source circuit shown below The transistor parameters are VTN = 0.8 V, Kn = 1 mA/V 2 and = 0 . The small-signal voltage gain is

www.gatehelp.com
Page 9 analog and digital electronics Test Paper-1

(A) 10.83 (C) 5.76

SOL 1.16

(B) 8.96 (D) 3.28

Form the DC analysis : VGSQ = 1.5 V , IDQ = 0.5 mA gm = 2Kn (VGS VTN ) = 2 (1 m) (1.5 0.8) = 1.4 mA/V ro = [IDQ] 1 = 3 The resulting small-signal equivalent circuit is shown below

vo = gm ugs RD, vi = vgs + gm vgs RS & vo = gm RD vi 1 + gm R S = (1.4m) (7k) = 5.76 1 + (1.4m) (0.5k)

Hence (C) is correct option.

MCQ 1.17
' In the circuit shown below the transistor parameters areVTN = 1 V and k n = 36 A/V 2

If ID = 0.5 mA , V1 = 5 V and V2 = 2 V then the width to-length ratio required in each transistor is

www.gatehelp.com
Page 10 analog and digital electronics Test Paper-1

W bLl 1 (A) (B) (C) (D)

SOL 1.17

W bLl 2 6.94 10.56 22.4 38.21

W bLl 3 27.8 50.43 5.53 12.56

1.75 4.93 35.5 56.4

Each transistor is biased in saturation because VDS = VGS and VDS > VGS VTN For M 3, V2 = 2 V = VGS 3 3 ID = 0.5 = b 36 # 10 lbW l (2 1) 2 2 L 3 W & b L l = 27.8 3 For M2, VGS2 = V1 V2 = 5 2 = 3 V
3 ID = 0.5 = b 36 # 10 lbW l (2 1) 2 2 L 3

& For M2 ,

W b L l = 27.8 3 VGS 2 = V1 V2 = 5 2 = 3 V
3 ID = 0.5 = b 36 # 10 lbW l (3 1) 2 2 L 2

& For M1 ,

W b L l = 6.94 2 VGS1 = 10 V1 = 10 5 = 5 V ID = 0.5 = b 36 # 105 lbW l (5 1) 2 2 L 1 W b L l = 1.74 1

&

Hence (A) is correct option.

MCQ 1.18

A p -channel JFET biased in the saturation region with VSD = 5 V has a drain current of ID = 2.8 mA , and ID = 0.3 mA at VGS = 3 V . The value of IDSS is (A) 10 mA (B) 5 mA (C) 7 mA (D) 2 mA

SOL 1.18

Hence (B) is correct option. 2 ID = IDSS b1 VGS l VP

www.gatehelp.com
Page 11 analog and digital electronics Test Paper-1

MCQ 1.19

2 2 2.8 m = IDSS b1 1 l , 0.3m = IDSS c1 3 m VP Vp 1 b1 VP l 2.8 = & & VP = 3.97 V 0.3 3 b1 VP l 2.8 = IDSS b1 1 l & IDSS = 5 mA 3.97 The transistor in the circuit shown below has parameters IDSS = 8 mA and VP = 4 V. The value of VDS is

(A) 2.7 V (C) 1.30 V

SOL 1.19

(B) 2.85 V (D) 1.30 V

Hence (B) is correct option. 60 VG = (20) = 6 V 60 + 140 Assume the transistor in saturation, ID = IDSS b1 VGS l VP ID = VS = VG VGS = 6 VGS RS RS 2k 2 6 VGS = (2k) (8m) b1 VGS l 4
2

&

VGS = 1.3 V

ID = (8m) b1 1.3 l = 365 mA 4

2

VDS
MCQ 1.20

VDS = 20 ID (2.7k + 2k) = 20 (3.65) (2.7 + 2) = 2.85 V VDS (sat) = VGS Vp = 1.30 ( 4) = 2.7 V > VDS (sat) Assumption is correct.

The following serial data are applied to the flip-flop through the AND gates as shown in figure. There is one clock pulse for each bit time. Q is initially 0 and PRE

www.gatehelp.com
Page 12 analog and digital electronics Test Paper-1

and CLR are high. If leftmost bits are applied first then output Q is

J1 : 1010011, J2 : 0111010, J 3 : 1111000 K1 : 0001110, K2 : 1101100, K 3 : 1010101 (A) 0000111 (B) 0011000 (C) 0101000
SOL 1.20

(D) 1010101

By applying the serial bits for J and K inputs of the flip-flop CLK J1 J2 J3 K1 K2 K3 J K Q 1 1 0 1 0 1 1 0 0 0 2 0 1 1 0 1 0 0 0 0 3 1 1 1 0 0 1 1 0 1 4 0 1 1 1 1 0 0 0 1 5 0 0 0 1 1 1 0 1 0 6 1 1 0 1 0 0 0 0 0 7 1 0 0 0 0 1 0 0 0

Hence (B) is correct option.

MCQ 1.21

For the circuit shown below each diode has V = 0.6 V and rf = 0 . Both diode will be ON if

(A) vs > 3.9 V

(B) vs > 4.9 V

www.gatehelp.com
Page 13 analog and digital electronics Test Paper-1

(C) vs > 6.3 V

SOL 1.21

(D) vs > 5.3 V

The circuit is as follows

For vs small, both diode are OFF. For vs > 0.6 V, D1 is ON. For v1 > 0.6 V, both diode will be ON. vs = 0.6 v1 + vs v1 = v1 + v1 0.6 5 5 0.5 0.5 v1 = 2us + 5.4 > 0.6 V & vs > 3.9 V 22 Hence (A) is correct option.

Common Data for Q. 22-23 :

For the circuit given IC = 3 # 1017 and VA = 3 and IC = 1 mA.

MCQ 1.22

The value of VB is (A) 26 mV (C) 726 mV

(B) 809.6 mV (D) 0 mV IC = IS eV /V :1 + VCE D VA

B T

SOL 1.22

Hence (B) is correct option.

As, VA = 3,

VB = VT ln b IC l IS = 26 # 103 ln c 1 # 1017 m = 0.8096 V 3 # 10

3

www.gatehelp.com
Page 14 MCQ 1.23 analog and digital electronics Test Paper-1

If VA = 5 V and IC = 1 mA for VCE = 15 V, the value of VB is (A) 802.8 mV (B) 796 mV (C) 809.6 mV (D) 26 mV

SOL 1.23

The collector current is IC = IS eV /V b1 + VCE l VA

B T

103 = 3 # 1017 eV /V b 0 + 1.5 l 5

B T

eV /V = 10 3.9
B T

14

VB = VT ln b 10 l 39 = 26 # 103 ln b 10 l . 802.8 mV 3.9 Hence (A) is correct option.

14

14

Statement for Linked Question 24-25 :

For the Schmitt trigger oscillator shown below saturation output voltage are + 10 V and 5 V.

MCQ 1.24

The frequency of oscillation is (A) 2183 Hz (C) 1369 Hz

(B) 869 Hz (D) 1443 Hz

SOL 1.24

The switching voltage are V+ = 10 = 5 V, 2 V+ = 5 = 2.5 V 2 The charging and discharging of capacitor is shown in fig. S4.5.23 Hence 5 = 10 + ( 2.5 10) e RC
i1

www.gatehelp.com
Page 15 analog and digital electronics
i e RC = 2 5
1

Test Paper-1

& &

t1 = RC ln 2.5

2.5 = 5 + (5 ( 5)) e RC
t e RC = 1 & t2 = RC ln 4 , 4
2

t2

&

T = t1 + t2 = RC ln 2.5 + RC ln 4 = RC ln 10 R = 50 k , C = 0.01 F T = 50k # 0.01 # ln10 = 1.15 ms f = 1 = 869 Hz T

Hence (B) is correct option.

MCQ 1.25

The duty cycle is (A) 60.2% (C) 48.4%

(B) 39.8% (D) 51.6%

SOL 1.25

Hence (B) is correct option. Duty cycle = t1 # 100 t1 + t 2 RC ln 2.5 = 100 RC ln 2.5 + RC ln 4 # = ln 2.5 # 100 = 39.8% ln 10
Answer Sheet

1. 2. 3. 4. 5.

(C) (D) (B) (B) (B)

6. 7. 8. 9. 10.

(B) (B) (A) (B) (C)

11. 12. 13. 14. 15.

(B) (C) (D) (A) (A)

16. 17. 18. 19. 20.

(C) (A) (B) (B) (B)

21. 22. 23. 24. 25.

(A) (B) (A) (B) (B)