EC1258 DIGITAL ELECTRONICS LAB

LIST OF EXPERIMENTS
1. ADDER AND SUBTRACTOR 2. BINARY CODE TO GRAY CODE AND VICEVERSA 3. BCD TO EXCESS3 CODE AND VICE VERSA 4. MAGNITUDE COMPARATOR 5. MULTIPLEXER AND DEMULTIPLEXER 6. 9 BIT PARITY GENERATOR/CHECKER 7. ENCODER AND DECODER 8. SHIFT REGISTER 9. SYNCHRONOUS COUNTER 10. ASYNCHRONOUS COUNTER 11. 4 BIT BINARY ADDER AND SUBTRACTOR 12. BCD ADDER

ADDERS

AIM: To Design and construct Half and Full Adder and to verify its truth table.

APPARATUS REQUIRED:

1. IC trainer kit. 2. IC 7432 3. IC 7408 4. IC 7404 5. IC 7486 6. Connecting wires.

PROCEDURE:

1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

HALF ADDER

IC7486 X Y
1 2 3

SUM

IC7408
1 2 3

CARRY

TRUTH TABLE FOR HALF ADDER:

INPUT A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 OUTPUT C 0 0 0 1

FULL ADDER

IC7486

IC7486
3 4 5 6

X Y Z

1 2

SUM

IC7408
1 2 3

IC7408
4 5 1 6 2

IC7432
3

CARRY

TRUTH TABLE FOR FULL ADDER:

A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 OUTPUT C 0 0 0 1 0 1 1 1

RESULT: Thus the Adder circuits are verified with their truth table.

SUBTRACTORS

AIM: To Design and Construct Half and Full Subtractor and verify its truth table. APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7432 3. IC 7408 4. IC 7404 5. IC 7486 6. Connecting wires.

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

HALF SUBTRACTOR

X Y

IC7486
1 2 3

DIFFERENCE

IC7404
1 2

IC7408
1 2 3

BORROW

TRUTH TABLE FOR HALF SUBTRACTOR:

INPUT A 0 0 1 1 B 0 1 0 1 D 0 1 1 0 OUTPUT B 0 1 0 0

TRUTH TABLE FOR FULL SUBTRACTOR:

A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 OUTPUT C 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 B 0 1 1 1 0 0 0 1

FULL SUBTRACTOR
IC7486

IC7486
3 4 5 6

X Y Z

1 2

DIFFERENCE

IC7404 2 1
2

IC7408
3

IC7404
3 4 4 5

IC7408
1 6 2

IC7432
3

BORROW

RESULT: Thus the Subtractor circuits are verified with their truth table.

CODE CONVERTERS BINARY CODE TO GRAY CODE

AIM: To Design and Implement BINARY TO GRAY & GRAY TO BINARY using logic gates.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7486 3. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

BINARY TO GRAY CODE:

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 INPUT C 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 D 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OUTPUT X 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Y 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 Z 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1

CODE
BINARY B3 B2 TO

CONVERTER
CODE

GRAY

B1

B0
IC7486
1 2 3

G0

IC7486
4 5 6

G1

IC7486
9 1 0 8

G2 G3

GRAY TO BINARY CODE:

W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

X 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

INPUT Y 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

Z 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

OUTPUT B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

GRAY G3 G2

TO BINARY CODE G1 G0
IC7486
1 2 3 9

IC7486
1 0 8

B0

IC7486
4 5 6

IC7486
1 2 3 1 2 1 3

IC7486
1 1

B1

IC7486
4 5 6

B2 B3

RESULT: Thus the Code Converters were designed and implemented.

BCD TO EXCESS 3 CODE AND VICE VERSA

AIM: To Design and Implement BCD TO EXCESS 3 & EXCESS TO BCD using logic gates.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7486 3. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

TRUTH TABLE:

BCD TO EXCESS 3 CODES:

B3 0 0 0 0 0 0 0 0 1 1

B2 0 0 0 0 1 1 1 1 0 0

INPUT B1 0 0 1 1 0 0 1 1 0 0

B0 0 1 0 1 0 1 0 1 0 1

E3 0 0 0 0 0 1 1 1 1 1

OUTPUT E2 E1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0

E0 1 0 1 0 1 0 1 0 1 0

BCD TO EXCESS-3 CODE

B3 B2 B1 B0 IC7404

IC7404

IC7404

E0
1 2

IC7486
3 1 2

E1

IC7404 IC7411
1 2 1 3 1 2 1 2

IC7432
3

E2

IC7432
4 5 6 1 2

IC7408
3

IC7408
4 5 6 1 2

IC7432
3

E3

EXCESS 3 TO BCD CODE:

E3 0 0 0 0 0 1 1 1 1 1

E2 0 1 1 1 1 0 0 0 0 1

INPUT E1 1 0 0 1 1 0 0 1 1 0

E0 1 0 1 0 1 0 1 0 1 0

B3 0 0 0 0 0 0 0 0 1 1

B2 0 0 0 0 1 1 1 1 0 0

OUTPUT B1 0 0 1 1 0 0 1 1 0 0

B0 0 1 0 1 0 1 0 1 0 1

EXCESS-3 TO BCD CODE

E3 E2 IC7404
3

E1 IC7404
5

E0 IC7404
9 8

B0 IC7486
1 2 3

B1

IC7408
1 2 3 1 2 1 2

IC7432
3

IC7411
1 2 1 3

IC7432
4 5 6

B2

IC7411
3 4 5 6

IC7408
1 2 3

IC7432
1 2 3

IC7411
1 2 1 3 1 2

B3

RESULT: Thus the Code Converters were designed and implemented.

MAGNITUDE COMPARATOR

AIM: To Design and Implement 2 bit, 4 bit Magnitude Comparator using logic gates and MSI devices.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7432 3. IC 7408 4. IC 7404 5. IC 7486 6. IC 7485 7. Connecting wires. PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

TRUTH TABLE: 2 BIT MAGNITUDE COMPARATOR

A0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A1
1

A1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A0
3

INPUT B0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
B1
5

B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0

OUTPUT A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0

2 BIT MAGNITUDE COMPARATOR

B0 IC7404 IC7404
1 2 1 3 9

IC7404

IC7404

IC7411
12 1

IC7432
2 3 5 4

IC7432
6

IC7408
1 3 2

A>B

IC7411
1 2 1 3 12

IC7486
1 2 3 1

IC7404
2

IC7408
1 3 2

A=B

IC7486
4 5 6 3

IC7404
4

IC7411
1 2 13 1 2

IC7432
1 3 2

IC7411
9 10 11 8

IC7432
4 6 5

A<B

1 2

IC7408
3

TRUTH TABLE:
4 BIT MAGNITUDE COMPARATOR

COMPARING INPUTS A3B3 A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A2B2 X X A2>B2 A2<B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A1B1 X X X X A1>B1 A1<B1 A1=B1 A1=B1 A1=B1 A1=B1 A1=B1 A0B0 X X X X X X A0>B0 A0<B0 A0=B0 A0=B0 A0=B0

CASCADING INPUTS A>B A=B A<B X X X X X X X X X X X X X X X X X X X X X X X X 1 0 0 0 1 0 0 0 1

OUTPUT A>B 1 0 1 0 1 0 1 0 1 0 0 A=B 0 0 0 0 0 0 0 0 0 1 0 A>B 0 1 0 1 0 1 0 1 0 0 1

4 BIT MAGNITUDE COMPARATOR

B1 A1 B0 A0
1 0 1 1 1 3 1 4 1 5 1 2 4 3 2 9 A = B _ IN A < B _ IN A > B _ IN 1

A2 B2 A3 B3
A 0 A > BB 0 A = BA 1 A < BB 1 A 2 B 2 A 3 B 3

+5V

IC7485

OUTPUT

RESULT: Thus the Magnitude Comparator circuit are designed and implemented.

MULTIPLEXER AND DEMULTIPLEXER

AIM: To Design and Implement Multiplexer, DEMultiplexer using logic gates and MSI devices.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7432 3. IC 7408 4. IC 7404 5. IC 74151 6. Connecting wires.

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

TRUTH TABLE: MULTIPLEXER

INPUT S0 0 0 1 1 S1 0 1 0 1 OUTPUT Y D0 D1 D2 D3

MULTIPLEXER
S1 S0

IC7404

IC7404 IC7411
1 2 13

12

D0

IC7432
1 2 3

IC7411 D1
3 4 5 6

IC7432
9 10 8

IC7411 D2
9 10 11 8

IC7432
4 5 6

IC7411 D3
1 2 13 12

TRUTH TABLE: DEMULTIPLEXER

D 1 1 1 1 INPUT A 0 0 1 1 B 0 1 0 1 D0 1 0 0 0 OUTPUT D1 0 1 0 0 D2 0 0 1 0 D3 0 0 0 1

DEMULTIPLEXER
IC7404 IC7404 IC7411 D0
9 1 0 1 1 8

S1

S0

Y0

IC7411 D1
3 4 5 6

Y1

IC7411 D2
9 1 0 1 1 8

Y2

IC7411 D3
1 2 1 3 1 2

Y3

RESULT: Thus the Multiplexer circuit is designed and implemented.

9 BIT PARITY GENERATOR / CHECKER

AIM: To Design and Implement Parity Generator/Checker using IC 74180.

APPARATUS REQUIRED:

1. IC trainer kit. 2. IC 74180 3. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

TRUTH TABLE PARITY CHECKER

INPUTS Number EVE of Xo N X7 EVEN 1

ODD 0

OUTPUTS EVE ODD N 1 0

ODD EVEN ODD X X

1 0 0 1 0

0 1 1 1 0

0 1 1 0 1

1 0 0 0 1

PARITY GENERATOR:

PARITY OF INPUTS X0 X7 ODD EVEN ODD EVEN

CASCADING INPUT EVEN 1 1 0 0 ODD 0 0 1 1

PARITY PARITY OF X0-X7 OF X0X7 EVEN ODD ODD EVEN ODD EVEN EVEN ODD EVEN ODD

9 BIT PARITY CHECKER / GENERATOR 9 BIT PARITY

X0 - X7
1 1 1 1

CHECKER
8 A 9 B 0 1 E V CE N _ O U T D 2 3 O ED D _ O U T F 1 G 2 H 3 E V E N _ IN 4 O D D _ IN 5 6

EVEN OUT ODD OUT

EVEN IN ODD IN

9 BIT PARITY

GENERATOR

X0 X1 X2 X3 X4 X5 X6 X7

X0 X1 X2 X3 X4 X5 X6 X7 EVEN IN ODD IN

8 A 9 B 10 E V CE N _ O U T 11 D 12 O ED D _ O U T 13 F 1 G 2 H 3 E V E N _ IN 4 O D D _ IN

5 6

EVEN OUT ODD OUT

RESULT: Thus the 9 bit Parity Generator/ Checker circuit are designed and implemented.

ENCODER AND DECODER

AIM: To Design and Implement encoder and decoder using logic gates .

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7432 3. IC 7408 4. IC 7404 5. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

TRUTH TABLE: ENCODER

A0 1 0 0 0 0 0 0 0 A1 0 1 0 0 0 0 0 0 A2 0 0 1 0 0 0 0 0 A3 0 0 0 1 0 0 0 0 INPUT A4 0 0 0 0 1 0 0 0 A5 0 0 0 0 0 1 0 0 A6 0 0 0 0 0 0 1 0 A7 0 0 0 0 0 0 0 1 D0 0 0 0 0 1 1 1 1 OUTPUT D1 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1

ENCODER (OCTAL TO BINARY)

A0 A1 A2 A3 A4 A5 A6 A7 IC7432
1 2 3 9

IC7432
10 8

IC7432
4 5 6

D0

IC7432
12 13 11 4

IC7432
6 5

IC7432
1 2 3

D1

IC7432
9 10 8 1

IC7432
3 2

IC7432
12 13 11

D2

TRUTH TABLE: DECODER

I0 0 0 0 0 1 1 1 1 INPUT I1 0 0 1 1 0 0 1 1 I2 0 1 0 1 0 1 0 1 A0 1 0 0 0 0 0 0 0 A1 0 1 0 0 0 0 0 0 A2 0 0 1 0 0 0 0 0 OUTPUT A3 A4 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 A5 0 0 0 0 0 1 0 0 A6 0 0 0 0 0 0 1 0 A7 0 0 0 0 0 0 0 1

DECODER (BINARY TO OCTAL)

IC7404 IC7404 IC7404 I0
1

I1
3

I2
5 6

IC7411
1 2 1 3 1 2

A0

IC7411
3 4 5 6

A1

IC7411
9 1 0 1 1 8

A2

IC7411
1 2 1 3 1 2

A3

IC7411
3 4 5 6

A4

IC7411
9 1 0 1 1 8

A5

1 2 1 3

IC7411
1 2

A6

IC7411
3 4 5 6

A7

RESULT: Thus the encoder and decoder circuit is designed and implemented.

SHIFT REGISTERS
AIM: To Design a 4bit Shift Register using flip-flops. (1). Serial In Serial Out (2). Serial In Parallel Out (3). Parallel In Parallel Out.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7474 3. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

SERIAL IN SERIAL OUT:

Vcc

10

PR E

Data In

PR E

PR E

PR E

10

2 3

5 6

12 11

9 8

2 3

5 6

12 11

9 8

Serial Out

C LR

C LR

C LR

13

T it le < T it le > S iz e A D a te : D ocum ent N um ber <D oc> F r id a y , S e p t e m b e r 2 1 , 2 0 0 7 Sheet 1 of 1 R ev <R ev C ode>

CLK 0 1 2 3 4

DATA 1 1 0 0 0

QD 0 0 0 0 1

13

7474 1

7474 1

7474

C LR

C LK Q

C LK Q

C LK Q

C LK Q

7474

SERIAL IN PARALLEL OUT:

Vcc

10

PR E

Data In

2 3

5 6

12 11

9 8

2 3

5 6

12 11

PR E C LR 13

PR E

PR E

10

9 8

C LR

C LR

13

7474 1

7474 1

C LR

C LK Q

C LK Q

C LK Q

C LK Q

7474

7474

QA

QB

QC

QD

T it le S iz e A D a te :

T it le < T it le > < T it le > S iz e D ocum ent N um ber D o c u Am e n t N < uDm o bc e> r <D oc> D a te : F r id a y , S e p t e m b e r 2 1 , 2 0 0 7 F r id a y , S e p t e m b e r 2 1 , 2 0 0 7 Sheet

Sheet 1 of

1 1

R ev R ev <R ev C ode> <R ev C ode> of 1

CLK 0 1 2 3 4

DATA 1 1 0 0 0

QA 0 1 0 0 0

QB 0 0 1 0 0

QC 0 0 0 1 0

QD 0 0 0 0 1

PARALLEL IN PARALLEL OUT:

Vcc

D1 4

D2 10

D3 4

D4 10 5 6 12 11 PR E C LR 13

PR E

PR E

2 3

5 6

12 11

9 8

2 3

PR E

9 8

C LR

C LR

13

QA

QB

7474

7474

C LR

C LK Q

C LK Q

C LK Q

C LK Q

7474

7474

QC

QD

T it le S iz e A D a te : T it le S iz e A

T it le < T it le > < T it le > S iz e D ocum ent N um ber D o c u Am e n t N < uDm o bc e> r <D oc> D a te : F rid a y , S e p t e m b e r 2 1 , 2 0 0 7 F rid a y , S e p t e m b e r 2 1 , 2 0 0 7 Sheet < T it le > D ocum ent N um ber <D oc> F r id a y , S e p t e m b e r 2 1 , 2 0 0 7 Sheet

Sheet 1 of

1 1

R ev R ev <R ev C ode> <R ev C ode> of 1

R ev <R ev C ode> 1 of 1

D a te :

CLOCK D1 0 1 1 1

D2 1 1

D3 0 0

D4 0 0

QA 0 1

QB 0 1

QC 0 0

QD 0 0

RESULT: Thus the Shift Registers circuits are designed and verified with their truth table.

SYNCHRONOUS COUNTER
AIM:

To Design and Implement 3-bit Synchronous counter.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7476 3. IC 7408 4. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

SYNCHRONOUS COUNTER
IC7408
1 2 3

PRESET IC7476
Q 15 9 6 Q 14 12 J

IC7476
Q 11 4 1 Q 10 16 J

IC7476
Q 15

PRE

PRE

1 16

C LK C LR K

C LK C LR K

C LK C LR K Q 14

CLOCK CLEAR A2 A1 A0

TRUTH TABLE:
CLK 0 1 2 3 4 5 6 7 QA 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 QC 0 1 0 1 0 1 0 1

RESULT: Thus the Synchronous Counter circuits are designed and verified with their truth table.

PRE

DATA IN

ASYNCHRONOUS COUNTER

AIM: To Design and Implement 4-bit ASynchronous counter.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7474 3. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

ASYNCHRONOUS

COUNTER
E

U Q Q

1 A 5 6

L R P R

D C L K 1

A0

CLOCK

C 7 4 7 4 1 0 E U Q Q

1 B 9 8

L R P R

1 2 1 1

D C L K 1 3

A1

C 7 4 7 4 4 E U Q Q

2 A 5 6

L R P R

2 3

D C L K 1

A2

C 7 4 7 4 1 0

U Q Q

2 B 9 8

PRESET A3

1 2 1 1

D C L K 1 3

CLEAR

C 7 4 7 4

TRUTH TABLE:
CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QA 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 QB 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 QC 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 QD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

RESULT: Thus the Asynchronous Counter circuits are designed and verified with their truth table.

L R P R

4 BIT BINARY ADDER / SUBTRACTOR

AIM: To design and implement 4 bit parallel binary adder and Subtractor.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7483 3. IC 7486 4. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Apply the binary inputs for A and B. 3. Observe the output for the corresponding input .

4 BIT BINARY ADDER/SUBTRACTOR

IC7486 B3
1 2 3

IC7486 B2
4 5 6

IC7486 B1
9 10 8

IC7486 B0
12 13 11

A0 A3 A1 A2 A3 Cin
13 11 7 4 16 10 8 3 1 9 6 2

GND/VCC

S0 S1 S2 S3 Cout
RESULT: Thus the 4 bit binary adder and Subtractor circuit was designed and implemented.

15 14

SUM SUM SUM SUM C4

1 2 3 4

C0 B1 B2 B3 B4 A1 A2 A3 A4

BCD ADDER

AIM: To design and implement BCD adder.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7483 3. IC 7408 4. IC 7432 5. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Apply the binary inputs for X and Y. 3. Observe the output for the corresponding input .

BCD ADDER

Y3 Y2 Y1 Y0
3 1 0 1 1 2 3 4 3 1 2 4 3 4 6 0

X0 X1 X2 X3
0
1 1 7 4 1 1 8 3 1 1 5 14 9 6 2 S U M C B S U M B B S U M B A S U M A A C 4 A

IC 7408
1 2 1 3 2 3 5 4

IC 7432 IC 7432
6 3 1

1 1 7 4 1 1 8 3 1

6 0

15

S0 S1 S2 S3

RESULT: Thus the BCD adder circuit was designed and implemented

14

S U M C B S U M B B S U M B A S U M A A C 4 A

1 0 1 2 3 4 3 1 2 4 3 4

Cout