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A 28nm ROM with Two-Step Decoding Scheme and OD-Space-Effect Minimization to Achieve 30% Speed and 190mV Vmin Improvement
Ching-Wei Wu, Kuang-Ting Chen, Robin Lee, Wei-Shuo Kao, Hong-Jen Liao, Jonathan Chang, Sreedhar Natarajan Memory Develop Project (MDP), Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu 300, Taiwan Phone: +886-3-5636688#703-8279, E-mail: cwwub@tsmc.com

Abstract An OSE-less [Oxide-definition Space Effect less] twin bits ROM cell is proposed. A reduced layout proximity dependence effect in ROM array is proposed using an OSE-less twin bits ROM cell. A Two-Step Decoding circuitry scheme suitable for either single-end or differential sensing is invented to read out twin bits ROM data. This work improves access time by 30% and reduces Vccmin by 190mV with TSMC 28nm Low Power process. Introduction In deep submicron era, the device behavior becomes more and more sensitive to layout implementation details. Devices with same geometric parameters, such as channel width and length, will show significantly different electrical performance according to its surrounding neighborhood and layout-dependent proximity effects [1]. One key layout-dependent effect is OD-Space-Effect (OSE), which is caused by the STI (shallow trench isolation) stress and related to the distance, direction of the OD (oxide definition or active device) region. In the channel-width direction, NMOS transistor favors tensile stress. However, the STI introduces compressive stress and degrades NMOS performance. The conventional read-only memory (ROM) cell is composed by either 1-T [2,3,5] or 2-T [4] NMOS with minimum OD-OD space, therefore suffer the worst OSE impact. Fig.1 shows a ROM cell in the middle has 31% Idsat less than one in the edge. Table.1 compares several possible solutions. Previous works 2-T [4] and 1-T Lower-Vth use differential sensing that is less sensitive to OSE impact, but needs higher cost by area or an extra mask. 1-T OD-Space-X2 was proposed to compensate the OSE-effected Idsat degradation but leads to 1.7x larger area penalty. Reference [6] can not support differential sensing and results in bad performance on vccmin, area and speed. This work proposes an OSE-less twin bits ROM cell layout that suppress the OSE impact, and a Two-Step Decoding circuitry scheme with differential sensing for better speed. OSE-less Twin Bits ROM Cell Figure 2 shows the proposed OSE-less twin bits ROM cell structure. Comparing to the conventional ROM cell shown in Fig. 1, the OSE-less ROM cell combines two ROM cells into one by shifting the left OD x/2 to right-side and the right to left-side. After merging left and right OD, this new ROM cell becomes OSE-less because the OD-OD space is relaxed by 2 times while still keeps the same 2-cell-pitch. The cell current discrepancy shown in Fig. 2 is improved from 31% to 6%. In convention, two ROM cells can store 4 kinds of coding states. To enable twin bits per cell in this OSE-less ROM to do the same, the 4 ROM code types (01, 10, 11, 00) are mapping to 4 BL (bit-line) nets (A, B, C, D) respectively. With the proposed architecture, a Two-Step Decoding circuitry, an OSE-less twin bits ROM cell is successfully implemented. The 6 sigma cell current simulation results are shown in Fig. 3. For conventional ROM cell, it degrades 82% from the mean-value and is very challenging to have sufficient design margin, especially in single-end sensing circuitry. The OSE-less ROM improves the mean-value by 2.42X and 6 sigma cell current by 5.42X. Operation of Two-Steps Decoding Circuitry The new twin bits ROM cell has 4 metal-pitches for A, B, C and

D that serve as output of the 1st read decoder (Fig. 4). The 4 signals stand for 01, 10, 11, and 00 respectively, and only one of them is pulled low for each read operation. Furthermore, the 4 signals require the 2nd decoder to determine which side of the twin bits is desired. The pulled down 0 can be passed through Y-MUX to DL and DLB. As long as the 0-coded bit is connected to DLB and 1-coded bit to DL, the inversed read-out value will be propagated to DL/DLB correctly. Figure 5 shows the waveform of OSE-less ROM read operation. A read-01 operation discharges A, and if Y-MUX0 is selected, 0 will be passed to DLB while DL remains high at pre-charged level. Read-11 (discharges C) follows the same style to pull-down DLB regardless Y-MUX0 or Y-MUX1 is selected, likewise for Read-00 (discharges D) and DL. This Two-Step Decoding circuitry not only selects the correct side of twin bits ROM, but also enables the employment of single-end or differential sense amplifier by producing DL/DLB signals. One minor drawback of this Two-Step Decoder is that each of the four 1st decoder output sees 2X loading when Y-MUX0/1 is turned on. For example, net A has to discharge Cs loading after Y-MUX0 is 1. However, with 5.42X more 6 sigma cell current, even if the worst-case scenario still produces 290% faster (in Fig. 3) BL development time (CV/I) than conventional ROM design. Measurement Results A test chip consisting of conventional and OSE-less ROM was manufactured in TSMC 28nm low power process. The silicon results of Vccmin and access time are shown in Fig. 6. Vccmin is greatly improved by 190mV because of OSE-less twin bits ROM. For conventional ROM cell, the design margin has to cover the 6 sigma weak bit cell current, thus Vccmin is limited due to bit-line discharged too slowly to read-out successfully before WL (word-line) turned off. Besides, the proposed work improves the ROM access time by 30% at 0.9VDD, low temperature, and worst corner. Conclusion Fig. 7 shows the microphotograph of 2 kinds of 256kbits ROM macros fabricated by TSMC 28nm Low Power technology. Here we summarize the performance of OSE-less twin bits ROM design. Comparing to conventional ROM, the proposed work improves the cell current mean-value by 2.42X and 6 sigma cell current by 5.42X. The normalized bit-line development time is improved by 290% and then improves the access time by 30% under 6 sigma ROM local variations. The Vccmin from silicon result shows 190mV improvement for 256k-bits ROM macro. In this paper, we discuss the OSE impact to ROM cells array for the first time and propose an OSE-less ROM cell and a Two-Step Decoding circuit to solve it. Reference
[1] J. V. Faricelli, 2010 Sep. CICC, pp. 1-8 [2] M. Seok, et al., 2008 Sep. CICC Dig. Tech. Papers, pp. 423-426 [3] M.F. Chang, et al., 2010 Feb. ISSCC, pp. 266-267 [4] K. Nii, et al., 2010 Sep. CICC, pp. 1-4 [5] S.K. Hsu, et al., 2006 Sep. ESSCIRC, pp. 299-302 [6] D.E.Dudeck, et al., 2007 Nov., U.S. Patent 7,301,828

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978-4-86348-348-4

2013 Symposium on VLSI Circuits Digest of Technical Papers

Type

OSE-less Twin Bits ROM

A WL
Connected one of nets (A, B, C, D) Two-Steps Decoding

Reference [6]
B C A W WL
Connected one of nets (A, B, C) or floating Single-Ended

2T ROM [4]

1T T ROM (Low wer Vth)

Lo ower V Vth WL

1T ROM (OD space x2)

2xOSE WL BL BLB

WL

BL BLB

Scheme

BL

BLB
Column MUX
Colu umn MUX Single-ended or Differe ential Sense Am mplifier

Column MUX Single-ended or Differential Sense Amplifier

Differential Sense Amplifier

Single-ended or Differential Sense Amplifier

Column MUX

Area OSE Impact Differential Sensing Speed Mask Cost

1X OK OK Fast OK

>1.2X OK NG Slow OK

>2X NG OK Medium OK

1X NG OK Me edium NG

>1.7X OK OK Fast OK

Table e.1 Different ROM scheme benchmark table

Fig. 1 Conventional ROM structure and com mparison

Fig. 2 OSE-less ROM struc cture and comparison

Icell (uA) CNV OSE-less diff

Median 37.4 90.3 2.42X

5.1 8.8 1.74X

6 weakbit 6.9 37.3 5.42X

6 weakbit / Median 0.18 0.41 2.25X

Fig. 5 Waveform of Read Operation

Fig. 7 Micrographs of the test chip

Fig. 3 ROM 6 sigma cell current simulation resu ults

3

Conventional

Access Time (a.u.)

Improve 30%

OSE-less

0.8

0.9

1.0

1.1

VDD

Fig. 6 Access Time and Vccmin measured data

Fig. 4 Two-Step Decoder Schem me with Table of Connection

2013 Symposium on VLSI Circuits Digest of Technical Papers

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