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Package Level Modeling Goals and Challenges Basic Packaging Concepts Package Characterization Introduction to FLOPACK
Modeling Goals
Modeling Challenges
Keeping
up with the rapidly changing field of IC packaging is difficult, especially for system designers (end-users). Some modeling assumptions are not obvious
Do I model my trace layers in a PBGA discretely? Can I neglect the bond wires in modeling a PQFP? Can I represent my thermal vias as a lumped block?
Generating
and tedious Information about the internal details of a package may be difficult to obtain
is an electronics package?
The combination of engineering and manufacturing technologies required to convert an electronic circuit into a manufactured assembly Martin Miller, Electronic Packaging, Microelectronics and Interconnection Dictionary
What
multi-disciplinary field:
Functions
of a package:
Electrical
Power distribution Interconnection
Mechanical
Die protection
Thermal
Heat dissipation
Die enclosure
Die
A package need not have all of the above elements The die, of course, is always present!
Ceramic Packages
More expensive More reliable Best electrical characteristics (fine line widths, multiple layers) Hermetic Excellent thermal performance Small number of packages in use Applications: High-power processors
Package Characterization
Standard
test methods defined by JEDEC are provided as a basis for comparison between various packages and devices. Well defined environments are used to ensure reliability and consistency between vendors. The thermal resistance values are not meant to and will not predict the performance of a package in an application-specific environment.
Package Characterization
Thermal
Resistance of a Package:
jx
T j Tx P
Tj = temperature at active surface of die (junction) Tx = temperature at some reference point P = package power
Package Characterization
ja
(Natural Convection)
ja
T j Ta P
Ta = ambient temperature, taken inside a specific enclosure defined by JEDEC (Still-Air Test) Measurements taken either with a High-k (2S2P) and Low-k (1S0P) board
Package Characterization
jma
(Forced Convection)
jma
T j Ta P
Ta = ambient temperature, taken upstream in the wind tunnel Board orientation is an important factor
Package Characterization
jc (junction to case resistance) The thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that same surface is properly heat sunk so as to minimize temperature variation across that surface.
jc
Ambient Die
T j Tc P
Case Junction
Substrate PCB
Package Characterization
qjc
Junction
Conduction
Package Characterization
jb (junction to case resistance) The thermal resistance from the junction to the board.
jb
T j Tb P
Package Characterization
Compact Models
Generates
Packaging Materials
Plastics/Resins Epoxy, FR-4, Polyimide, BT, die attach materials Metals/Alloys Copper, Solders (Pb/Sn alloys), Kovar, Alloy-42, Aluminum, Gold, Tungsten, etc. Ceramics Alumina (Al2O3), AlN, BeO Semiconductors Silicon, Gallium Arsenide (GaAs)
Packaging Materials
Relevant
Glass transition temperature for organic materials (Tg) - Temperature above which material loses its laminate
characteristics. Typical values: FR-4 = 125 C, BT = 200 C
Underfill
Interconnections
Die
2)
Interconnections: Level 1
Level
Three
Peripheral, not area array; low I/O density Pitch on die limited to usually of 3 mils Large signal lengths; high self-inductance
Technology
introduced in the 1970s Popular in Japan, not much in the U.S. Leadframe is directly bonded to the I/O pads on die periphery, in a process known as Inner Lead Bonding Leadframe is normally attached to a (usually polyimide) tape, hence the name
Bumped die Die Polyimide Tape Cu leadframe
More expensive today than wire-bonding Peripheral array, I/O density not high
Advantages:
Short interconnect length, excellent electrical performance Can handle up to 2 mil pitch on die periphery
Modeling:
This interconnection can usually be ignored in CFD modeling (insignificant thermal resistance)
Has
its roots in an IBM technology of the 1960s ( called C4) Did not become popular till late 1980s Die connected with substrate through solder balls
Usually not in regular array Common solders: 37Pb/63Sn, 95Pb/5Sn Typical dia ~ 3 mils
C4 Die Substrate Underfill
Can have major CTE mismatch problems Underfill makes rework practically impossible Higher cost (although this is dropping)
Advantages:
Best electrical performance of all methods Area array leads to highest I/O density
Modeling:
Usually have a small, but significant thermal resistance, especially for ceramic packages. Negligible spreading in Flip-chip layer Best modeled as collapsed cuboid with volume averaged conductivity
Interconnections: Level 2
Level
2 interconnect: coupling between the package substrate and PCB Can generally be classified by mechanical attachment method and I/O arrangement:
Surface mount (SMT) : I/Os rest (usually soldered) on PCB surface.
Surface Mount/Peripheral leaded
Interconnections: Level 2
Three
Peripheral Leads
These
are most commonly surface mounted (exception, Dual In-line Package) in PQFPs, SOPs etc. Pitches have shrunk to as low as 16 mils (0.4 mm) I/O counts up to ~ 400 Mature, low cost technology I/O limits due to peripheral array, co-planarity problems Leads typically of Copper (older packages, Alloy-42)
Gull-wing leads
Advantages:
J-leads
Low cost, mature technology Easy to inspect for faults No CTE mismatch problems with FR-4 boards
Disadvantages
Long interconnect lengths, high self-inductance Lead co-planarity problem Peripheral array; low I/O density
Modeling advice:
Form a critical heat transfer path for peripheral leaded packages Model as equivalent cuboid of volume averaged orthotropic conductivity. Modeling leads discretely does not improve model accuracy significantly for packages with a large number of leads.
Solder Balls
Package
using solder balls is knownPeripheral Balls Central/Thermal as Ball Grid Array (BGA) Balls Technology pioneered by IBM in the 1960s, Found wide acceptance in the 1990s BGA use is rising almost exponentially, especially in the U.S. Solder balls typically of 95Pb/5Sn or 37Pb/63Sn Array can be peripheral, with solder additional central balls Underfill rarely present
Solder Balls
Advantages
High I/O density Excellent electrical performance (low self-inductance) Self-aligning during reflow, low manufacturing defect rate
Disadvantages:
Difficult to inspect for defects Possible CTE mismatch Not cheap (although cost is dropping)
Modeling
choices:
Modeling
choices:
Full Cuboid
Pins
Package
using pins is called a Pin Grid Array (PGA). (More on PGAs later.....) Pins are typically made of Kovar (an alloy) They are often by means of a socket, connecting with the PCB through its own pins
Package pins Socket Socket pins
Modeling Pins
Most
pins have pitches of 50 mils or 100 mils and diameters of about 15 mils I/O counts of up to ~ 800 Modeling approach:
Ceramic packages: can model as equivalent volume averaged cuboid, as ceramic substrate is a good heat spreader Plastic packages: may need to model as discrete pins, especially if die size is small
Modeling ICs
The Die
Term
for the piece of semiconductor on which all the active circuits lie Usually made of Silicon Gallium Arsenide is used in some special applications (microwave/high speed) Circuitry present within a thin layer on one side only, known as active surface
Circuitry Active surface
The Die
Modeling advice:
Model as a cuboid with temperature dependent conductivity (for Silicon) Place collapsed source on active surface to represent heat dissipation Do not forget to set the source direction inwards, within the die!
Collapsed source
Cuboid
Die Flag
Die Flag:
The die is often placed (usually in plastic packages) on a thin metal plate known as the die flag or die pad. The die flag serves either a manufacturing or a thermal function, or both. The die flag is usually made of copper, and is typically larger than the die
Die Flag
Die
Die Flag
Die
Because the die flag is metallic, it can act as a very effective heat spreader
Modeling
It is recommended that the die flag be modeled discretely Spreading within the die flag can reduce the thermal resistance of a package by ~ 15 % This is small, but not insignificant!
Die Attach
Die
Attach:
The die is often attached to the substrate or the die pad by an adhesive known as the die attach It is often made of an epoxy based compound Typical values for die attach: Thickness = 1-2 mils, Conductivity = 1- 2 W/mK
Die Attach Die pad Die
Die Attach
Die Protection
The die is fragile and needs protection (although packages with bare dies do exist) Two common means of protection:
Overmolding Capping
Overmolding
Overmolding:
Overmold is almost always an epoxy based compound Low conductivity (0.6 - 0.8 W/mK) A significant contributor to thermal resistance To reduce this resistance, a metallic slug is sometimes placed inside a plastic package
Metal Slug Adhesive Overmold
Die
Capping
Die
Capping:
In ceramic packages Capping seals off the die cavity Cap usually made of aluminum Model cap as cuboid May need to consider effects of radiation between cap and die
Cap Ceramic substrate
Die
Leadframes
Leadframes:
A characteristic of all peripheral leaded packages Most packages with leadframes are plastic (PQFP, SOP, PLCC), but ceramic ones do exist (CQFP) Leadframes normally made of Copper, although Alloy-42 (a Ferrous alloy) can be found in older designs
Die Flag
Die
Leadframes
Leadframe
attachment:
Leadframe typically wire bonded to die TAB bonded in TAB packages When wire bonded, gap between die flag and leadframe is an important thermal bottleneck
Bond wire Die Die flag Leadframe Thermal bottleneck Die attach
Modeling Leadframes
Leadframe modeling:
Can be modeled as cuboid blocks with volume averaged, orthotropic conductivity Take average extent for internal leadframe
Substrates
A
substrate is an element on which the die is mounted to and which routes the I/Os from die to PCB Critical element from thermal standpoint Packages without a substrate: PQFP, SOP (e.g) Substrates:
Ceramic Organic
Ceramic Substrates
Ceramic
Substrates:
Most commonly made of Alumina (k = 20 W/mK) For better thermal performance, AlN or BeO also used (k ~ 200 W/mK) BeO is hazardous, requires special handling Ceramic layers placed together and fired in high temperature oven Metal traces usually made of Tungsten or Molybdenum
Ceramic Substrates
Ceramic substrate
Ceramic Substrates
Advantages:
Hermetic; highly reliable Fine line widths Excellent thermal performance Many (20 +) trace layers possible Good CTE match with silicon die
Disadvantages:
Require specialized, expensive manufacturing technique CTE mismatch with FR-4 PCB, large packages need underfill
Ceramic Substrates
Applications:
High power, heavy duty packages such as processors
Organic Substrates
Organic
substrates:
Present only in plastic packages e.g. Plastic Ball Grid Array (PBGA), Plastic Pin Grid Array (PPGA) Challenging to model Dielectric made of a plastic based laminate resin; metal is usually copper
Die
Resin
Organic Substrates
Advantages:
Lower dielectric constant than ceramic substrates Manufacturing technology similar to that for PCBs Less expensive to manufacture Excellent CTE match with PCB
Disadvantages:
Limited number of layers Need thermal enhancements Poor CTE match with silicon die
Applications:
Organic Substrates
Traces:
Cu traces can be signal layers or power/ground planes Typical organic substrates are either 2-layer or 4layer 2-layer substrate often (but not always) has signal layers only (no power and grounds)
Bond wire Two signal traces Die Die Flag
Organic Substrates
Traces:
4-layer substrates have two additional power and ground planes
Bond wire
Modeling
traces:
Lumping traces and resin together as a single cuboid or block-and-plate is not recommended! Model traces as discrete layers Within each layer, volume average based on Cu coverage
Cuboids
Vias
Originally created for increasing interconnection density in multiple layer PCBs Technology migrated to organic packages Today, also used for thermal enhancement (thermal vias)
Cu plating
Air Substrate
Via classification:
Signal vias electrical function can be blind/buried Thermal vias serve purely thermal function usually thru-hole
Modeling
vias:
Typically model only thermal vias Difficult to model signal vias! Signal vias may be thermally significant in some packages (e.g. flip-chip), need investigation.......
Modeling
as discrete
most refined approach accounts for constriction resistance Takes up more grid; introduces large aspect ratio grid cells
Modeling Boards
Technology
for manufacturing organic substrates and PCBs is similar Compatibility - Detailed Model and Board Model Need to pay attention to:
Copper Planes Vias Connectors
Radiation
Modeling Boards
FLOPACK
PCB macro can create a model with an arbitrary number of layers as well as compact or discrete via groups.
Copper Planes
Dielectric
Heatsinks
If
a heatsink is present on detailed package model, it must be modeled accurately for consistency Heatsinks:
Parallel Fin
Can use FLOTHERM SmartPart, or FLOPACK
Pin Fin
Can use FLOTHERM SmartPart, or FLOPACK
Disk-fin
FLOPACK generator
Proper
gridding important for resolving boundary layers within heatsinks Focus on extruded heatsinks (most common) Transverse and streamwise directions are key Transverse direction:
Use 3 cells between fins No extra grid needed within fins 2 cells sufficient to resolve base
2 Cells in Base
direction:
Losses = Skin friction + Contraction/Expansion Transverse gridding resolves Skin Friction Losses Streamwise gridding critical to resolving Contraction/Expansion Losses Cluster cells at entrance and exit of extruded heatsink
Normal
direction:
Fins
Heatsinks: Miscellaneous
Model radiation on heatsink surfaces in natural convection Do not forget thermal grease (model as collapsed cuboid)
JC 15.1 subcommittee Standards to provide Figures of Merit for comparing package performance (http:///www.jedec.org) Examples of Standards available:
Still Air Test for Theta-JA (Rja) Forced Air Test for Theta-JMA (Rjma) Ring Cold Plate for Theta-JB (Rjb) Low Conductivity Test Board (1S Board) High Conductivity Test Board (2S2P Board)
being discussed:
Cold Plate for Theta-JC Various standards for new test boards
Other:
Validation beds for computational models Reporting format for detailed models Standards for compact modeling
Compact Modeling
Introduction Compact Deriving Deriving
Detailed Models
Recall
that .....
A Detailed Model attempts to capture thermal behavior of a package by reproducing the physical structure of the package as completely as possible
Limitations
of Detailed Models
Reveal internal (proprietary) construction details of packages Are computationally demanding due to large grid required
A
Compact Model seeks to capture the thermal behavior of the package accurately ....
... at pre-determined (critical) points (junction, case etc.) .... by using a reduced set of parameters to represent the package
These
parameters need not be geometric The most popular approaches use some sort of thermal resistance network representation
2-Resistor
Compact Models:
T Rjc J Rjb B
A significant improvement over single-resistor metrics Simple topology Can be used in System/Boardlevel/EDA tools (via IDF 3.0) Can be derived experimentally or computationally Typical accuracy for most cases is < 20%
http://www.jedec.org
FLOPACK
Computational Approach:
The
and jc approaches lump all heat paths together as one - use with caution.
ja
and
jc
Inaccuracies
TO
Shunt Resistors
BI
BO
DELPHI
What
is (was) DELPHI? Project that proposed new methodologies for creating and validating computational component models Ultimate Goal: to enable component manufacturers to supply validated compact thermal models of their parts to end-users Results were:
Modeling methodology for Detailed Models 2 experimental systems (Double Cold Plate and Submerged Double Jet Impingement) Modeling methodology for Compact Models
Deliverable
Detailed Model
Compare Compact Model Results with Detailed Model Results to Estimate Accuracy
Compact Model
...A wide variety of boundary conditions within the spectrum of possible environments encountered in electronics cooling.
Model
Internal Leads
Tie Bar
Encapsulant
100-Lead PQFP
DELPHI
Top Inner
Top Outer
Sides 32.5
Junction
Leads
55.2 29.1
10.3
Bottom Inner
Bottom Outer
can either :
Generate their own compact models using FLOPACK Use compact models generated by component supplier
FLOPACK
generates a compact model as a PDML downloadable Compact Component SmartPart User simply imports the model and locates it correctly in their model User should not change entries except power
Package Styles
SmartPart
Area
Array:
Heat transfer through top and bottom only Two solder ball regions possible
Leaded:
Heat transfer through top, bottom, and leads Leadframe could be 2-sided (Dual) or 4-sided (Quad)
Cuboid blocks in three layers create isothermal nodes Cuboids representing solder balls (not included in SmartPart)
Top Outer
Place
monitor point in the middle of the junction region Can also use Tables Window
Example
As
an example, we will examine the implementation for an area array package, a Flip-Chip Plastic Ball Grid Array (FC-PBGA) Bare die protruding at top Inner and outer solder balls
Bottom Outer
Network Menu
Node
Resistance (C/W)
Heat Energy (Joules) Heat Flow Rate - Q (Watts) Temperature Difference - T (Kelvin) Thermal Resistance - Rth (K/W) Thermal Capacitance - Cth (J/K) Charge - Q (Coulomb) Current - I (Amperes) Potential Difference - V (Volts) Electrical Resistance R (Ohm- V/A) Electrical Capacitance - C (Farad C/V)
Steady State
Only Resistance elements are necessary Conduction Very well suited for problems which result in predominantly one-dimensional heat flow pattern. Complicated networks may be needed to represent multidimensional problems. Convection and Radiation Not suitable for most of the engineering problems of interest. May be used as an simplified boundary condition for the conduction problems.
Transient
Both Resistance and Capacitance elements are necessary Otherwise quite similar to the Steady State Models
Network Identification
Number of RC Components and interconnections Needs good understanding of the thermal paths
Network Identification
Implementation in FLOTHERM
Model an equivalent network in FLOTHERM using existing options
Network Identification
Implementation in FLOTHEM
Network Identification
Networks can be of
One-Dimensional Only one major heat path Very short transients (semi-infinite assumption) Multidimensional More than one major heat path MCMs Interaction between various power cells within a die
Network Identification
Implementation in FLOTHEM
One-Dimensional Networks
Assumed RC Values
Foster Network
Network Identification
Bad
Implementation in FLOTHEM
Multi-Dimensional Networks
The most complicated steps
Assumed RC Values
Network Identification
Bad
Implementation in FLOTHEM
Network Identification
Implementation in FLOTHEM
Implementation in FLOTHERM
One-Dimensional Networks
Very simple Model blocks with appropriate dimensions and stack them to represent the network and Resistance
Network Identification
Implementation in FLOTHEM
Multidimensional Networks
Complicated May not be possible to implement in FLOTHERM
Beyond FLOTHERM
Tools
Matlab Mathcad MS Excel
Suggested Readings
Mathematics
Laplace Transforms Matrix Algebra Curve fitting methods Inverse Transforms Complex Numbers Numerical Methods
Network Synthesis
Passive Networks
Heat Transfer