IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL 21, NO 2, MARCHIAPRIL 1991

365

Improved Current Control Technique of VSI PWM Inverters with Constant Modulation Frequency and Extended Voltage Range
Luigi Malesani,
Member, IEEE,

Paolo Tenti,

Member, IEEE,

Elena Gaio, and Roberto Piovan

A bstract-A hysteresis control method for three-phase, current-controlled, VSI PWM inverters is presented, characterized by constant switching frequency. It is based on the phase-interference minimization technique presented in a previous paper but avoids the need to know load parameters. Moreover, it minimizes commutation losses and current ripple while allowing maximum output ac voltage to be obtained from the inverter. The method exhibits all the favorable characteristics of hysteresis controls: fast response, good accuracy, and robustness. Fig. 1. Three-phase inverter with motor load.

ity of the inverter is increased by about 15% in comparison with URRENT control of voltage-fed PWM inverters supplying the usual inverters, where the load midpoint voltage is kept at three-phase ac loads can be achieved by means of three the midpoint of the dc supply. main techniques, i.e., ramp comparison, predictive control and PRINCIPLE OF OPERATION hysteresis control. Hysteresis control [2]- [7] gives accurate and fast response Fig. 1 shows a VSI PWM inverter together with the equivawhile requiring minimum hardware. The main limitations of this lent scheme of a symmetric three-phase load including symmettechnique are interference among phases and wide variations in rical emf _e. switching frequency, which cause irregular inverter operation In order to describe the interference suppression method, and uneven output current waveforms. consider the load equations: These limitations can be overcome by suppressing phase interference, according to a method that allows separate modulations to be performed on each phase. As a result, regular inverter operation and reduced current ripple are obtained. Moreover, by means of a PLL, the hysteresis-band amplitude (2) U, = ( U , U2 + 4 3 within the output waveform period may be controlled in order to where all voltages are referred to the supply midpoint. Instantaobtain constant modulation frequency. which are produced by the inverter, can A first application of the method was presented in a previous neous phase voltages _U, paper [ 5 ] . There, however, estimation of passive load parame- only assume values H/2. Because the load has no neutral ters was needed to eliminate phase interference. Here, a substan- connection, the instantaneous sum of currents i is always zero. tial improvement of the interference suppression principle is Let i* be the load reference currents; the reference phase presented, which keeps all the previous advantages but does not voltages that should be applied to obtain the desired currents I* require any knowledge of load. The only condition is load are: symmetry. di* _U* = RI* + L+ _e ~ $ 1 Such a result can be achieved by performing modulations only (3) dt by two inverter legs at a time while keeping the third standing at 2 4 : = (UT u; - U 3 ) / 3 . the positive or negative dc supply voltage. This kind of opera(4) tion gives the following additional advantages: Commutation Because the sum of reference currents I*, like actual currents losses are substantially reduced, and the output voltage capabili , must be zero, (3) and (4) are not independent. Thus, there is one degree of freedom in determining reference voltages _U* Paper IPCSD 90-36, approved by the Industrial Power Conversion Comcorresponding to given currents j * . mittee of the Industry Applications Society for presentation at the 1988 The differences between actual phase voltages _U and reference Industry Applications Society Annual Meeting, Pittsburgh, PA, October voltages g* produce current deviations _S defined as 2-7. Manuscript released for publication August 16, 1990. This research

INTRODUCTION

was supported by the Italian Ministry of Public Education and by Gruppo Macchine Elettriche of the National Research Council. L. Malesani and P. Tenti are with the Department of Electrical Engineering, University of Padova, Padova, Italy. E. Gaio and R. Piovan are with Istituto Gas Ionizzati, CNR, Padova, Italy. IEEE Log Number 9041935.

From the above relations, it results in

dli R_S + L dt

= _U - _U* - (U, -

u$)J

OO93-9994/91/03OO-0365$01 .OO @ 1991 IEEE

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which shows that due to terms U, and U : , the current deviation in each phase is affected by other phases. In order to suppress the interference, a particular modulation technique can be adopted, according to which only two inverter legs at a time perform the modulation, whereas one of the two switches of the third phase is kept closed. Thus, the corresponding phase voltage U, is maintained at supply value +E/2 or - E / 2 . The choice of the standing phase and output polarity varies according to modulation needs, as will be discussed later. The absence of modulation in standing phase s can be interpreted in the previous equations by assuming that actual voltage U, and its reference uf coincide. Thus, also uf must be given a value of +E/2 or - E / 2 , which can be done in principle. With this assumption, from (2), (4), and (6), by substituting the values of U, and uf and taking into account load symmetry, current errors 6, and U, of modulating phases p and q derive

+$
0

_-E
2

R6,

+ L - dt

d6, d6

2
= -(U,

1
-

~ 6 , LL = -(U - U*) dt 3 " 3

3 2

U;) - -(U,

- U*,)

1
-

. ; ) .

(7)
tl

$
3

Errors 6, and 6, can be split as follows:

t,

ts

t4

t5

6, = (2u, - u,)/3

6,

(2u, - u p ) / 3 .

(8)

(b) Fig. 2. Inverter reference voltages for sinusoidal operation: (a) Load voltages; (b) inverter output voltages. I,

Error components up and U, only depend on corresponding phase voltages u p and U,. In fact, from 7 and 8, one can derive

.-

R a p + L - dt
Ru,

du,

= (U, -

4
(9)

+L

du A = (U, - U*,) dt

This holds irrespective of load parameters and f.e.m., provided they are symmetric. Signals up and U, are immediately obtained from actual errors 6, and 6,. Taking into account that the instantaneous sum , 6 , and 6, is also zero, (8) gives of ,6

frs

1%

Fig. 3. Basic scheme of hysteresis control.

Hysteresis control can be performed on these signals instead of errors 6, as usual, thus allowing each inverter phase to behave independently. Regular, interference-free operation results. A further advantage is that a PLL can be adopted to control commutation frequency by varying dead-band amplitude. The switching times of one phase are not, in fact, affected by other phases. The choice of standing phase must satisfy some conditions. In fact U, is the highest voltage that can be generated if it assumes the value of +E/2 and lowest if it assumes the value of -E/2. Thus, uf corresponds at any instant to the highest or lowest of references _U*. This condition is illustrated, without any loss of generality, in Fig. 2, which refers to the case of sinusoidal and symmetrical voltages to be applied to the load. For example, in time interval t,, only phase 1 can be kept at + E / 2 voltage, or phase 3 can be kept at - E / 2 . If, in intervals t,, t?, t,, phases 1, 2, 3, respectively, are kept at +E/2, and in intervals t,, t,, t,, phases 3 , 1, 2 are kept at - E / 2 , reference voltages E* result, as is shown in Fig. 2(b).

If the blocked phase is not properly chosen, modulation is no longer able to ensure that load currents follow references with the desired accuracy. For instance, in the case of Fig. 2, if phase 1 is kept at + E / 2 even after the end of interval t , , the hysteresis control of phase 2 turns on the positive switch of the corresponding inverter leg, but the resulting voltage is lower than needed; soon, current error U corresponding to phase 2 exceeds the lower boundary of the hysteresis band.

CONTROL IMPLEMENTATION
The basic configuration of the proposed hysteresis control is shown in Fig. 3. Phase current errors _S are obtained, according to ( S ) , from actual currents i and references j*. Interference-free error terms up and U, are calculated, according to (lo), in the multiplexer-adder (MA) under control of P, signals. They indicate the phase, which is kept standing, and its polarity (1 , 1 - , 2 , 2 - , 3 , 3 - ). The correspondence used is summarized in Table I.

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367

TABLE I

blocked phase 1+
op
aq

36 , - 6, 6, - 6,
Q q

2+
6, - 6 , 6, - 6,
Q q

16, - 6, 6 , - 6,
-

3+
6, 6 ,
Qp

26 , 6,

6, - 6, 6 , - 6,

6,
6,

6,
6,

QI

0"

0"

0"

Q,

TABLE XI

blocked phase

1+
KpKp+

3x 1+

2+
1-

1x

3+
2x 1x

2x

I I
KqK,+ KqKq+ Kq+ KO-

3x

I I

2x

x 2+
x
X

KpKpKp+ K,+

1x
x x

x 3x 2X

2+
x 3+ x
X

2+
x 1+ x
X

3X

3+
X

x
X

1+
X

x
X

2 f
X

Hysteresis modulation is performed on signals up and U, in PLL-HC blocks. Dead-band amplitudes 0 and 0 ,are varied by 4 the PLL controls, which ensure synchronization of modulation frequencies with a reference frequency f,,. The structure of these blocks is of the type described in [5]. Modulator outputs, which are logic signals Q, and Q,, determine the states Q,, Q 2 , Q3 of the inverter legs (high status corresponds to positive switch S' closed and negative switch S" open), together with their complements. This is done in the output multiplexer (OM) under the control of P, according to the choice made in the MA. The correspondence is shown in Table I. In the OM, the blocking of one phase to high (+) or low ( - ) status is also performed in dependence of P,. Signals up and U, are compared in blocks CP with dead bands of increased amplitudes in order to detect the occurrence of any excess with respect to the hysteresis band of modulators PLL-HC. To this end, amplitudes 0 , and P, are fed to blocks CP and added to suitable fixed quantities to determine the increased deadbands. When signal up exceeds the upper or lower boundary of the relative increased band, signals K,+ or K,- go high. This is the same for U, and K q + or K,-. This happens whenever the choice of the standing phase is not proper and must be changed. For this purpose, the standing phase selector (SPS) senses signals K, and K , and, depending on the actual status of P,, selects a new status. The latter is maintained until a new excess error occurs. The operating rules adopted for the SPS are summarized in Table 11, which indicates the new status in dependence of signals K and of the previous status. An x indicates that no change in the previous status is performed for the corresponding situation. Table II also shows the cases of simultaneous excess signals from both up and U,. These cases correspond to overmodulation conditions of the inverter.

IMPLEMENTATION CRITERIA
The above implementation involves several choices, which are discussed here. First, only two interference-free error terms U,

and U, are used; these are derived from the different phases according to the choice of the standing phase. The modulated signals are then fed to the corresponding phases. As an alternative solution, three error-free signals could be used, one for each phase, performing three separate modulations. This would reduce the complexity of multiplexers MA and OM. However, in this instance, PLL performance would be severely disturbed due to the time intervals where the corresponding phase is blocked. In fact, during these times, the dead-band amplitude would increase to its maximum, and long recovery transients would result. Second, adoption of the excess error as an index, which determines the commutation of the standing phase, is a simple and safe way of ensuring proper system operation both in steady state and in transients. In fact, current errors are easily obtained, and any improper operating condition is immediately detected. Moreover, the amplitude of the band that causes the commutation is usually reduced with respect to its maximum, as is shown in Fig. 7 . This happens because the corresponding phase voltage approaches one of the dc supply voltage limits, and PLL control narrows the band in order to maintain constant modulation frequency. The excess error, therefore, does not appreciably affect overall current deviation. If, similarly to [5], a lower limit is put to the band amplitude, a more regular operation is obtained, as is demonstrated by experimental tests. In fact, this reduces the transient of the band amplitude, which, although limited, occurs after commutation. In any case, as the PLL loses synchronization when the required voltage exceeds dc supply limits, a lower limit to the band amplitude does not appreciably worsen PLL operation at phase commutations. The phase commutation criterion, which is summarized in Table 11, derives from the following considerations. As the desired voltage of one phase exceeds that of the standing phase and, thus, the dc supply limits, two choices are possible: transfer of the standing status to the phase exceeding the limits or transfer of it to the third phase. In the first instance, proper operating conditions are ensured. However, as may be easily verified in the case of periodic output waveforms such as those of Fig. 2(a), unsymmetric behavior results; the blocked status is transferred from the positive (or negative) switch to another of the same sign, where each phase is kept still for a third of the period. If, according to the Table 11, the third phase is chosen, the polarity of the standing switch is changed at every phase commutation. The resulting output voltage reference waveforms (for the case of Fig. 2(a)) are shown in Fig. 2(b), with one phase commutation every sixth of the period. Both choices ensure a sufficient voltage margin, provided that the desired maximum line-to-line voltage does not exceed the dc supply value E . This requirement is less demanding than that of usual methods, which keep reference load midpoint voltage U*, at the supply midpoint. For symmetric, sinusoidal voltage waveforms like those of Fig. 2, the benefit is about 15%. When the desired maximum line-to-line voltage is greater than the dc supply limits, errors U and U, can simultaneously exceed 4 the boundaries of the hysteresis band. In these cases, no changes are profitably made on the existing status, except when both nonblocked phases require a voltage of the same sign of the standing phase; the latter has the wrong polarity, which is thus reversed. It can be easily shown that with the above strategy, when the desired voltage increases, inverter operation gradually enters

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Fig. 4. Inverter output: Top-phase voltage (200 V/div, 1 ms/div); bottom-phase current (6.6 A/div).

Fig. 5 . Inverter output currents (6.6 A/div, 2 ms/div).

overmodulation conditions, eventually reaching square-wave operation, as is required by full exploitation of the inverter capability. The operating rules of the MA and OM blocks, which are summarized in Table I, are derived from the above criteria with the aim of minimizing the changes in error signals up and U*. With this kind of control, switching frequency is only approximately constant. In fact, switching stops when the corresponding phase is blocked. Moreover, there are appreciable frequency variations near the phase commutations, which call for suitable margins in the maximum switching rate. Nevertheless, average frequency is maintained constant by PLL control within narrow limits, which allows good exploitation of switch capability. Moreover, the total number of commutations is reduced, typically by a third, by blocked-phase operation. Thus, total switching losses are greatly reduced in comparison with usual methods.

Fig. 6. Error signals: Top-total phase error 6 (0.66 A/div, 1 ms/div); bottom-interference-free error U (1.33 A/div).

EXPERIMENTAL RESULTS
An inverter prototype, controlled according to the described hysteresis method, was built. The inverter was rated for a 400-V dc supply and a 10-A r.m.s. output current. The load, an induction motor, was rated for 220-V r.m.s., 50 Hz, 1500 r/min, and 2 kW. It was operated at variable speed from zero to 2000 r/min. Measured equivalent motor parameters were R = 2 Q and L = 12 mH. A 5-kHz modulation reference frequency was adopted. System behavior was tested in the whole operating range, both in steady state and in transient conditions, demonstrating the excellent performance of the proposed method. Benefits in terms of output voltage capability and commutation losses were evaluFig. 7. Phase commutation: Top-under band limit (0.66 A/div, 1 ms/div); ated, showing good accordance with theoretical forecasts. Fig. 4 shows typical output voltage and current waveforms. center-error signal U (0.66 A/div); bottom-lower band limit (6.6 A/div). The time interval during which the phase voltage is blocked is evident. Fig. 5 shows typical output current waveforms for all was produced. Immediately, phase commutation is commanded, three phases. Fig. 6 reports the total current error 6 of one phase and within a few commutation cycles, the PLL resumes control. and, on a reduced scale, one interference-free signal U . The Switching frequency is quite uniform throughout the period, effectiveness of the method in eliminating the influence of phase except near the phase commutations. interference is evident from a comparison of the two waveforms. Fig. 8 demonstrates the system response to transients, which Fig. 7 illustrates the commutation between the phases. For this is peculiar to hysteresis controls. A three-phase step in reference purpose, one error U is shown together with its band limits. current was applied; the current rises at the maximum rate As band amplitude decreases, which occurs when phase volt- allowed by the supply voltage and load parameters as error age approaches the supply limit, the lower limit of the amplitude signal U saturates. No current overshoot is produced. Fig. 9 becomes effective, and the PLL loses synchronization. The error shows the system behavior in overmodulation. With the increase signal does not reach the opposite band limit, and an excess in output voltage, the system ensures a gradual transition to error takes place on the same side on which the last commutation square-wave operation.

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[4] A. Nabae, S. Ogasawara, and H. Akagi, A novel control scheme of current-controlled PWM inverters, presented at IEEE-IAS Ann. Mtg., 1985, pp. 473-478. [ 5 ] L. Malesani, and P. Tenti, A novel hysteresis control method for current-controlled VSI PWM inverters with constant modulation frequency, presented at IEEE-IAS Ann. Mtg., Atlanta, Oct. 1987, pp. 851-855. [6] E. Gaio, R. Piovan, and L. Malesani, Comparative analysis of hysteresis modulation methods for VSI current control, presented at Third Int. Conf. Power Electron. Variable-Speed Drives, London, July 1988. [7] E. Gaio, R. Piovan, and L. Malesani, Evaluation of current control methods for voltage source inverters, presented at ICEM 88, Pisa, Sept. 1988.
Luigi Malesani (M63) was born in Lonigo (Vicenza) Italy, on Sept. 18, 1933. He received the doctor degree in electrical engineering, with honors, from the University of Padova in 1962. From 1963 to 1964, he was employed as a researcher in the Centro Gas Ionizzati of CNR. From 1964 to 1975, he was an Assistant Professor of electrical engineering, and from 1968 to 1975, he was an Associate Professor of Electronic Components at the University of Padova. Since 1975, he has been Professor of Applied Electronics at the same University. His interests are in power elecironics, circuit design, electrical machines, and automatic control. He has written a number of papers on these subjects. Dr. Malesani is member of AEI. Paolo Tenti (M85) was born in Bolzano, Italy, in 1951, and in 1975, he graduated with honors in electrical engineering in the State University of Padova. He started work at the Institute of Electric and Electronic Engineering of the same university as a lecturer of electrotechnics and was a contract researcher of the National Research Council of Italy (CNR). In 1979, he began teaching in Power Electronics as contract professor and in 1981 became a permanent researcher. Since 1985, he has been an associate professor of power electronics in the Department of Electrical Engineering of the University of Padova. His main research interests concern industrial electronics, static power conversion, and industrial drives. Current activities regard PWM rectifiers, power filters and compensators, SMPSs for space and industrial applications, and advanced control techniques. Dr. Tenti is member of AEI. Elena Gaio was born in Lendinara (Rovigo), Italy, on August 8, 1958. She received the Dr. degree in electronics engineering from the University of Padova in 1983. In 1985, she received the Post-Degree diploma from the School of Plasma and Controlled Thermonuclear Fusion Engineering from Padova University. Since 1984, she has been with the Istituto Gas Ionizzati of C.N.R., working with the Power Supply Group of the RFX thermonuclear fusion experiment. Her field of interest is in dc/dc converter systems. In particular, her experience covers the analysis and numerical simulation of power circuits and control systems. Roberto Piovan was born in Megliadino S. Vitale (Padova), Italy, on November 30, 1955. He obtained the Dr. degree in electrical engineering from the University of Padova in 1980. He has been working, since 1980, at Istituto Gas Ionizzati of CNR in the power supply field for nuclear fusion research plants. His experience covers supply systems based on capacitoi banks, acldc, and dc/dc converters. Presently, he is working on the power supply commissioning of the RFX thermonuclear fusion experi-

Fig. 8

Phase current transient response: Top-phase current (6.6 A/div, 2 ms/div); bottom-error signal U (1.33 A/div).

Fig. 9. Overmodulation: Top-phase voltage (200 V/div, 2 ms/div), bottom-phase current (13.3 A/div).

CONCLUSIONS A method for PWM hysteresis current control of three-phase

voltage source inverters is presented. It is based on substantial improvement of the principle of minimization of interference among modulations of the various phases, which does not require any knowledge of load parameters or e.m.f., provided the load is symmetric. Interference minimization allows PLL control of switching frequency. The inherent benefits of the proposed technique are full exploitation of inverter voltage capabilities and definite reduction in commutation losses. The method exhibits the good accuracy and excellent dynamic response, which is typical of hysteresis techniques. Experimental tests confirmed theoretical forecasts, showing excellent performance of the control.

ACKNOWLEDGEMENTS
The authors would like to thank M.Bonetto for his invaluable help in implementing the system prototype and R. Sartorello for his experienced supervision and effective support of experimental work.

REFERENCES
[ l ] G. Pfaff, A. Weschta, and A. Vick, Design and experimental results of a brushless AC servo-drive, presented at IEEE-IAS Ann. Mtg., 1982, pp. 692-697. [2] A. Kawamura and R. G. Hoft, Instantaneous feed-back controlled PWM inverters with adaptive hysteresis, IEEE Trans. Industry Applications, vol. IA-20, no. 4, pp. 769-775, 1984. [3] D. M. Brod and D. W. Novotny, Current control of VSI-PWM inverters, IEEE Trans. Industry Applications, vol. IA-21, no. 4, pp. 562-570, 1985.

ment.