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ORGANIZING COMMITTEE Chief Patron Sri. G.R.Ravinder Reddy Secretary Patron & Coordinator Dr. S. Udaya Kumar Principal Co-Coordinator Dr.C.V.Narasimhulu
HOD-ECE
AICTE Sponsored
Faculty Development Programme (FDP)
on
Advanced VLSI system Design 17th -29th June, 2013 Registration Form
Name:......... Designation:....... Organization:................... Professional Experience: Teaching: R&D:.......... Industry:........ Address for Communication: . Tel. No: Mobile:..... E-mail:.
on
Advanced VLSI system Design 17th -29th June, 2013 Organized by
Department of Electronics &Communication Engineering
Steering Committee Members: Prof. K.Somasekhara Rao, Dean, Academics Prof. D.Rama Krishna Rao, Dean, R&D Dr. M. Satyanarayana, Director, R&D Projects Sri.D.Venkata Rami Reddy, Associate Professor Sri.P.Sudhakar, Associate Professor Mr.P.Sagar Babu, Assistant Professor Mr.K.V.S.Naga Raju, Assistant Professor Ms.G.Sahithi, Assistant Professor Mr.S.Mohammed Rafi, Assistant Professor Mr.Ch.Vijay Krishna, Assistant Professor
Declaration
The information furnished above is true to the best of my knowledge. I agree to abide by the rules and regulations governing the FDP. Place: Date: Signature of the Applicant
The Coordinator
Geethanjali College of Engineering & Technology
Cheeryal (V), Keesara (M), R.R. Dist. 501301
Note: Registration form may be submitted through E- mail followed by hard copy.
Tel No. : 040-32449152 Visit us: www.geethanjaliinstitutions.com E-mail: uksusarla@gmail.com narasimhulucv@gmail.com gcetece2013@gmail.com info@gcet.edu.in
department and in a short period the intake has been increased to 240. The first batch of ECE students graduated in the year 2009 and are well placed in reputed organizations. The department has well equipped laboratories with good infrastructure. The department has highly qualified and experienced faculty. The department has been sanctioned a DST Project titled Design and Development of Multi wavelength Laser Radar (LIDAR)" with an overall budget of 34.58 lakhs in the academic year 2010-11. Our college has been recognized as Scientific and Industrial Research Organization (SIRO), i.e. as an R&D centre by DSIR (Department of Scientific and Industrial Research) Govt. of India (Ref. No: F No 11/532/2011-TU-V dated October 12, 2011) in the academic year 2011-12.
Custom IC Design (CIC) Flow including Hands on Sessions. Application Specific Integrated Circuit (ASIC) Flow Including Lab sessions. Mixed Signal Design including Lab Sessions. FPGA flow including Lab Sessions. Introduction to HDLs, Combinational and Sequential Circuit Design using HDLs. Test and Testability. Introduction and Issues in VLSI Design automation Algorithms. Need For Low Power VLSI Design, Low power methods. Introduction to SoC Technology.
Resource Persons
Persons from various institutions such as IIIT, NITs, JNTUH etc, and organizations such as DRDO, BDL, CADENCE, CoreEL Technology working in the area of VLSI design.
Eligibility
Faculty of Educational Institutions/ Research Scholars/ Research Personnel working in R& D Organizations, with a minimum qualification of Masters degree in Electronics & Communication/ Electrical/ Computer Science and allied branches of Engineering.
Registration
Participants are requested to register by filling in the Registration Form and sending the same to the Coordinator by E-mail followed by hard copy. Max. No. of participants: 50 (First come first served basis) Note: TA/DA, Lodging and Boarding will be provided to the outstation participants as per eligibility norms.
Topics to be covered
Introduction to VLSI Technologies (CMOS, BiCMOS). Introduction to Novel and Innovative Nano Devices (GaAs, CNTFETs and SETs). Introduction to CAD tools and Layout Design Rules.
Important Dates
Last date for receipt of application: 10/06/2013 Intimation of Selection: 12/06/2013