CpE358/CS381 Switching Theory and Logical Design Class 17

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-660

Today
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata Class Wrap-up: Electronic Dice Design Problem
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-661

Initial Problem Statement

Electronic Dice (Difficulty=7) 7 LEDs flash in a seemingly random fashion (20/second) until user presses a button. Flashing stops within 1 second and LEDs display a pattern representing the 6 possible die faces. Probability of any outcome is equally likely.

Roll

Electronic Dice

Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-662

Block Diagram of System Implementation

Clock Random S/R Generator

3 bits (0-7) Run Controller Roll 0<state<7 State Compare 3 bits (1-6) Display Decode

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-663

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. 0<state<7

Roll

SR Clock

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-664

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. Start 0<state<7

Roll

SR Clock

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-665

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. Start 0<state<7

Roll

SR Clock

20 Hz Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-666

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. Start 1010 CI 4-bit ctr LD Co CI 4-bit ctr LD 1110 Co 0<state<7

Roll

SR Clock

20 Hz Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-667

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. Start 1010 CI 4-bit ctr LD Co CI 4-bit ctr LD 1110 Co D Q 0<state<7

Roll

SR Clock

20 Hz Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-668

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. Start 1010 CI 4-bit ctr LD Co CI 4-bit ctr LD 1110 Co D Q 0<state<7

Roll

SR Clock

20 Hz Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-669

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. Start 0 D Q CI 4-bit ctr LD 1010 Co CI 4-bit ctr LD 1110 Co D Q 0<state<7

Roll

SR Clock

20 Hz Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-670

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. Start 0 D Q CI 4-bit ctr LD 1010 Co CI 4-bit ctr LD 1110 Co D Q 0<state<7

Roll 0 D Q

SR Clock

20 Hz Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-671

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. Start 0 D Q CI 4-bit ctr LD 1010 Co CI 4-bit ctr LD 1110 Co D Q 0<state<7

Roll 0 D Q

SR Clock

20 Hz Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-672

Random S/R Generator

Run Controller

Run Controller

State Compare

Display Decode

If Roll has been pressed, output clock for no more than one more second. Stop the clock only if the state output of the shift register is 1, 2, 3, 4, 5, or 6. Start 0 D Q CI 4-bit ctr LD 1010 Co CI 4-bit ctr LD 1110 Co D Q 0<state<7

Roll 0 D Q

SR Clock

20 Hz Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-673

Random S/R Generator

State Compare

Run Controller

State Compare

Display Decode

State Compare prevents the shift register from stopping if the current state is 0 or 7
State 000 001 010 011 100 101 110 111 Output 0 1 1 1 1 1 1 0

b2b1b0

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-674

Random S/R Generator

State Compare

Run Controller

State Compare

Display Decode

State Compare prevents the shift register from stopping if the current state is 0 or 7
State 000 001 010 011 100 101 110 111 Output 0 1 1 1 1 1 1 0

Output = (b0b1b2) + (b0+b1+b2)

b2b1b0

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-675

Random S/R Generator

Display Decode
A B C D E F G
A B X 0 0 0 0 0 1 X C X 0 0 0 1 1 1 X D X 1 0 1 0 1 0 X E X 0 0 0 1 1 1 X

Run Controller

State Compare

Display Decode

F X 0 0 0 0 0 1 X

G X 0 1 1 1 1 1 X

b2b1b0

0 1 2 3 4 5 6 7

X 0 1 1 1 1 1 X

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-676

Random S/R Generator

Display Decode
A B C D E F G
A B X 0 0 0 0 0 1 X C X 0 0 0 1 1 1 X D X 1 0 1 0 1 0 X
E 0 1 D 0 1 00 X 0 01 1 1 11 1 X 10 0 0 F 0 1 G 0 1
Copyright 2004 Stevens Institute of Technology All rights reserved

Run Controller

State Compare

Display Decode

E X 0 0 0 1 1 1 X

F X 0 0 0 0 0 1 X
00 X 1 00 X 0 00 X 1

G X 0 1 1 1 1 1 X
01 0 1 01 0 0 01 0 1 11 0 X 11 0 X 11 1 X 10 0 1 10 0 1 10 1 1

b2b1b0

0 1 2 3 4 5 6 7

X 0 1 1 1 1 1 X

b1b0
A 00 X 1 00 X 0 00 X 1 01 0 1 01 0 0 01 0 1 11 1 X 11 0 X 11 0 X 10 1 1 10 0 1 10 0 1

b2

0 1 B 0 1 C 0 1

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

1-677

Random S/R Generator

Display Decode
A B C D E F G
A B X 0 0 0 0 0 1 X C X 0 0 0 1 1 1 X D X 1 0 1 0 1 0 X
E 0 1 D 0 1 00 X 0 01 1 1 11 1 X 10 0 0 F 0 1 G 0 1
Copyright 2004 Stevens Institute of Technology All rights reserved

Run Controller

State Compare

Display Decode

E X 0 0 0 1 1 1 X

F X 0 0 0 0 0 1 X
00 X 1 00 X 0 00 X 1

G X 0 1 1 1 1 1 X
01 0 1 01 0 0 01 0 1 11 0 X 11 0 X 11 1 X 10 0 1 10 0 1 10 1 1

b2b1b0

0 1 2 3 4 5 6 7

X 0 1 1 1 1 1 X

b1b0
A 00 X 1 00 X 0 00 X 1 01 0 1 01 0 0 01 0 1 11 1 X 11 0 X 11 0 X 10 1 1 10 0 1 10 0 1

b2

0 1 B 0 1 C 0 1

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

1-678

Random S/R Generator

Display Decode
A B C D E F G
A B X 0 0 0 0 0 1 X C X 0 0 0 1 1 1 X D X 1 0 1 0 1 0 X
E 0

Run Controller

State Compare

Display Decode

E X 0 0 0 1 1 1 X

F X 0 0 0 0 0 1 X
00 X 1 00 X 0 00 X 1

G X 0 1 1 1 1 1 X
01 0 1 01 0 0 01 0 1 11 0 X 11 0 X 11 1 X 10 0 1 10 0 1 10 1 1

b2b1b0

0 1 2 3 4 5 6 7

X 0 1 1 1 1 1 X

b1b0
A 00 X 1 00 X 0 00 X 1 01 0 1 01 0 0 01 0 1 11 1 X 11 0 X 11 0 X 10 1 1 10 0 1 10 0 1

A=b1+b2 B=b1b2
D 0 1 00 X 0 01 1 1 11 1 X 10 0 0

E=b2

b2

0 1 B 0 1 C 0 1

1 F 0 1 G 0 1
Copyright 2004 Stevens Institute of Technology All rights reserved

F=b1b2

D=b0 C=b2

G=b1+b2
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1-679

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Random S/R Generator

Random S/R Generator

Run Controller

State Compare

Display Decode

Use a maximal length S/R generator to create a pseudorandom string of 1s and 0s.

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-680

Random S/R Generator

Random S/R Generator

Run Controller

State Compare

Display Decode

Use a maximal length S/R generator to create a pseudorandom string of 1s and 0s. 3 bits are taken out of the S/R to represent the die state. Since there is an equal probability of any three bit combination, there are 8 states which can be represented. 2 of them are eliminated by other circuitry, so the probability of 1, 2, 3, 4, 5, or 6 are the same.

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-681

Random S/R Generator

Random S/R Generator

Run Controller

State Compare

Display Decode

Use a maximal length S/R generator to create a pseudorandom string of 1s and 0s. 3 bits are taken out of the S/R to represent the die state. Since there is an equal probability of any three bit combination, there are 8 states which can be represented. 2 of them are eliminated by other circuitry, so the probability of 1, 2, 3, 4, 5, or 6 are the same. The three bits that are selected for use must not be adjacent, otherwise if 000 is rejected, the next state will be 000 or 100, depending on the next bit. 000 will be rejected again, but 100 will be accepted, increasing its probability compared to the other states. Likewise, if 111 is rejected, 011 will be accepted, increasing the probability of that state.

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-682

Random S/R Generator

Random S/R Generator

Run Controller

State Compare

Display Decode

Use a maximal length S/R generator to create a pseudorandom string of 1s and 0s. 3 bits are taken out of the S/R to represent the die state. Since there is an equal probability of any three bit combination, there are 8 states which can be represented. 2 of them are eliminated by other circuitry, so the probability of 1, 2, 3, 4, 5, or 6 are the same. The three bits that are selected for use must not be adjacent, otherwise if 000 is rejected, the next state will be 000 or 100, depending on the next bit. 000 will be rejected again, but 100 will be accepted, increasing its probability compared to the other states. Likewise, if 111 is rejected, 011 will be accepted, increasing the probability of that state.

N-bit S/R b0 b1 b2
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-683

Block Diagram of System Implementation

Clock Random S/R Generator

3 bits (0-7) Run Controller Roll 0<state<7 State Compare 3 bits (1-6) Display Decode

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-684

Initial Problem Statement

Electronic Dice (Difficulty=7) 7 LEDs flash in a seemingly random fashion (20/second) until user presses a button. Flashing stops within 1 second and LEDs display a pattern representing the 6 possible die faces. Probability of any outcome is equally likely.

Roll

Electronic Dice

Clock
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-685

Summary
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata Class Wrap-up: Electronic Dice Design Problem
www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-686