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FPGA based multilevel cascaded inverters with SVPWM algorithm

for photovoltaic system


M. Valan Rajkumar
a,1
, P.S. Manoharan
b,
a
Department of Electrical and Electronics Engineering, Anna University of Technology, Madurai, India
b
Department of Electrical and Electronics Engineering, Thiagarajar College of Engineering, Madurai 625 015, India
Received 18 May 2012; received in revised form 2 November 2012; accepted 4 November 2012
Available online 6 December 2012
Communicated by: Associate Editor Nicola Romeo
Abstract
This paper presents the control for three-phase multilevel cascaded H-bridge inverter for photovoltaic (PV) system. The maximum
power point tracking (MPPT) is capable of extracting maximum power from the PV array connected to each DC link voltage level.
The MPPT algorithm is solved by perturbation and observation method (P&O). Space vector pulse width modulation (SVPWM) algo-
rithm uses a simple mapping to generate gate signals for the inverter. The location of the reference vector and time are easily determined.
The adjustments of modulation index and phase angles are synthesized onto eld programmable gate array (FPGA) by means of hard-
ware description language (VHDL). A digital design of the generator SVPWM using VHDL is proposed and implemented on FPGA.
This is done to achieve high dynamic performance with low total harmonic distortion (THD). Simulation and experimental results are
given to verify the implemented SVPWM control for PV system in terms of THD.
2012 Elsevier Ltd. All rights reserved.
Keywords: Photovoltaic (PV) system; Cascaded H-bridge multilevel inverter; Space vector pulse width modulation (SVPWM); Field programmable gate
array (FPGA); Total harmonic distortion (THD)
1. Introduction
Recently, the installation of PV generation systems is
rapidly growing due to concerns related to environment,
global warming, energy security, technology improvements
and decreasing costs. PV generation system is considered as
a clean and environmental-friendly source of energy. The
main applications of PV systems are in either standalone
or grid connected congurations. Standalone PV genera-
tion systems are attractive as they are indispensable elec-
tricity source for remote areas. However, PV generation
systems have two major problems: (i) low conversion
energy in low irradiation conditions (ii) the amount of elec-
tric power generated by PV arrays varies continuously with
weather conditions. Therefore, how to increase the e-
ciency of the energy produced from PV arrays are discussed
(Richard et al., 2005; Marcelo et al., 2009).
Many MPPT algorithms have been proposed in the lit-
erature, such as incremental conductance (INC), constant
voltage (CV) and perturbation and observation (P&O).
The P&O method has been widely used because of its sim-
ple feedback structure and fewer measured parameters, as
described in (Hajizadeh and Golkar, 2008). The implemen-
tation of the low power consumption MPPT controller
using a pulse frequency modulation dc-dc boost converter
was developed (Lopez-Lapena et al., 2010). Dierent types
of multilevel inverter topologies are presented in the litera-
ture (Jose et al., 2002; Tolbert et al., 1999; Hammond,
1997). Many methods of pulse width modulation (PWM)
0038-092X/$ - see front matter 2012 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.solener.2012.11.003

Corresponding author. Tel.: +91 9486019204; fax: +91 452 2483427.


E-mail addresses: valanrajkumar@gmail.com (M. Valan Rajkumar),
psmeee@tce.edu (P.S. Manoharan).
1
Research Scholar.
www.elsevier.com/locate/solener
Available online at www.sciencedirect.com
Solar Energy 87 (2013) 229245
techniques are used to control the inverter have been dis-
cussed (Colak et al., 2011). SVPWM directly uses the con-
trol variable given by the control system, and identies
each switching vector as a point in complex (a, b) space
has been discussed in detail (Massoud et al., 2003).
SVPWM is suitable for digital signal processing implemen-
tation and optimization of switching patterns as explained
(Celanovic and Boroyevich, 2001).
Simple ON-time calculation is done due to the use of a
two-level geometry based ON-time equations. The ON-
time calculation equations for dierent modulation mode
do not change with the position of reference vector like
the traditional approach in (Mondal et al., 2003, 2002).
The optimal switching sequence and the discontinuous
modulation can be applied to multilevel inverters using
zero sequence oset voltages derived from two-level inver-
ter space vector concepts are discussed (McGrath et al.,
2003). The multilevel ON-time calculation problem is con-
verted to a simple two-level ON-time calculation problem.
This method is described in detail in (Gupta et al., 2004).
The implementation of PWM by digital signal processor
(DSP) and microcontroller has been discussed (Tzou
et al., 1996; Vadivel et al., 1991).
An attractive idea is to implement the PWM via an
application-specic integrated circuit (ASIC). The FPGA
is a sub-class of ASIC controllers which provides charac-
teristics such as fast prototyping, simple hardware and soft-
ware design and higher switching frequency are discussed
(Puyal et al., 2006; Tzou and Hsu, 1997). The FPGA-based
PW modulators for multilevel three-phase three-wire volt-
age source inverters were developed (Zhou et al., 2004;
Tonelli et al., 2001). A generic digital VHDL module for
the multilevel multiphase SVPWM algorithm has been dis-
cussed (Alvarez et al., 2011).
A single phase cascaded H-bridge multilevel inverter can
be controlled using phase shifted PWM as a feasible multi-
string topology for PV applications are discussed (Villanu-
eva et al., 2009). In a PV system, proportional controller
current control scheme is used to maintain the output cur-
rent sinusoidal and to get high dynamic performance from
the dierent atmospheric conditions are discussed (Selvaraj
and Rahim, 2009). The scheme is (Cecati et al., 2010) pro-
posed for a single-phase multilevel cascaded H-bridge
inverter for PV applications with fuzzy logic control and
system-on-chip approach.
The leakage current in three-phase transformer-less PV
systems connected to the grid was discussed (Cavalcanti
et al., 2010). A fundamental-frequency-modulated diode
clamped multilevel inverter fed by PV modules for stand-
alone application has been discussed (Ozdemir et al.,
2009). A novel power conversion scheme for the grid con-
nection of a PV generation system has been analysed and
implemented in DSP was discussed (Grandi et al., 2009).
The elimination of harmonics in multilevel inverters
using particle swarm optimization was explained (Al-oth-
man and Tamer Abdelhamid, 2009). The THD minimiza-
tion on output voltage of the multilevel inverters was
discussed (Yousefpoor et al., 2012). Real time algorithm
for minimizing THD in multilevel inverters with unequal
or varying voltage steps under staircase modulation was
proposed (Liu et al., 2009a). Real time calculation of
switching angles minimizing THD for multilevel inverters
with step modulation was discussed (Liu et al., 2009b).
Harmonic optimization of voltage balancing control for
multilevel converter system was discussed (Pan and Peng,
2006).
This paper proposes a system consisting of a PV array
connected to the three phase multilevel cascaded H-bridge
inverter through DC bus which is connected to the three
phase load as shown in Fig. 1.
The control structure of the PV system is composed of
two structure control.
1. The MPPT control, whose main property is to extract
the maximum power from the PV generator,
2. The inverter control is applied
i. To control DC bus voltage.
ii. To convert DC input to AC output at the same wave-
forms as the three phase lines.
iii. To ensure high quality of the output power.
2. PV array modeling and simulation
The PV array used in the proposed system is KC200GT
and it is simulated using a model based on (Ravi et al.,
2011; Xiao et al., 2004; Sera et al., 2007). In this model,
a PV cell is represented by a current source in parallel with
diode and a series resistance as shown in Fig. 2. In this PV
array, mathematical model can be expressed as
I I
Photo
I
RSat
exp
q
A
D
K
B
T
V IR
se

_ _
1
_ _

V R
se
I
R
p
1
Eq. (1) shows that the non linear output characteristics of
solar cell. It is aected by temperature, radiation of solar
and condition of load, where I
Photo
is the photo current,
I
RSat
is the reverse saturation current, q is the electron
charge (1.6021747 10
19
C), R
Se
is the series resistance
and R
p
is the parallel resistance. Photocurrent I
Photo
is di-
rectly proportional to the solar irradiation (G
ira
). In Eq.
(1) A
D
is dimensionless factor, K
B
is the Boltzmann con-
stant (1.38 10
23
J/K) and T is the temperature.
I
Photo
G
ira
I
sc
G
ira
G
iras
_ _
2
where I
SC
short circuit current depends linearly on cell tem-
perature and G
iras
is the standard irradiation (1000 W/m
2
).
I
sc
T I
scsat
1 DI
sc
T T
st
3
where DI
sc
is the temperature coecient and T
St
is the stan-
dard temperature (298 K). I
Photo
and I
RSat
depend on the
230 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245
cell temperature and solar irradiation and these can be
mathematically expressed as
I
Photo
G
ira
; T I
scsat
G
ira
G
iras
_ _
1 DI
sc
T T
st
4
I
RSat
G
ira
; T
I
Photo
G
ira
; T
e
V oc
V
t

1
5
In Eq. (5), V
t
is thermal voltage. The parameters of solar
array KC200GT at nominal operating conditions is shown
in the Table 1.
3. MPPT control
Many MPPT algorithms have been proposed in the lit-
erature. The two algorithms often used to achieve maxi-
mum power point tracking are the P&O and INC
methods. The INC method oers good performance under
rapidly changing atmospheric conditions. The INC method
uses two voltage sensors and two current sensors to sense
the output voltage and current of the PV array. If the sen-
sors require more conversion time, then the MPPT process
will take longer to track the maximum power point. During
tracking time, the PV output is less than its maximum
power. This means that longer the conversion time, larger
the power loss (Hajizadeh and Golkar, 2008).
On the contrary, if the execution speed of the P&O
method increases, then the system loss will decrease. More-
over, this method only requires two sensors, which results
in a reduction of hardware requirements and cost. There-
fore, P&O method is used to control the MPPT process.
In order to achieve maximum power, two dierent
applied control methods that are often chosen are volt-
age-feedback control and power-feedback control (Hua
et al., 1998). Voltage-feedback uses the solar-array terminal
voltage to control and keep the array operating near its
maximum power point by regulating the arrays voltage
and matching the voltage of the array to a desired voltage.
The drawback of the voltage-feedback control is its neglect
of the eect of irradiation and cell temperature. Therefore,
the power-feedback control is used to achieve maximum
power.
The P&O MPPT algorithm with a power-feedback con-
trol (Hua et al., 1998; Koutroulism and Kaalitzakis, 2001)
Fig. 1. General diagram of three phase load connected photovoltaic system.
Fig. 2. Equivalent circuit of a PV cell physical model.
Table 1
Parameters of the adjusted model of the KC200GT solar
array at nominal operating conditions.
I
mp
7.61 A
V
mp
26.3 V
P
max,m
200.143 W
I
sc
8.21 A
V
oc
32.9 V
I
o,n
9.825 10
8
A
I
Photo
8.214 A
A 1.3
R
p
415.405 X
R
se
0.221 X
M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245 231
is shown in Fig. 3. The power is calculated by using deter-
mination of PV voltage and PV current. At the maximum
power point dv/dt is zero. The maximum power point can
be achieved by changing the reference voltage by the
amount of DV
ref
.
In order to implement the MPPT algorithm, a buck-
boost dc-dc converter is used. The parameters L and C in
the buck-boost converter must satisfy the following condi-
tions (Mohan et al., 2003).
L > R1 D
2
=2f 6
C > D=Rf DV =V
out
7
In Eqs. (6) and (7), D is the duty cycle and f is the switching
frequency. The buck-boost converter consists of one
switching device that enables it to turn ON and OFF
depending on the applied gate signal D. The gate signal
for the switching device can be obtained by comparing
the saw-tooth waveform with the control voltage (Haji-
zadeh and Golkar, 2008). The change of reference voltage
DV
ref
obtained by MPPT algorithm becomes the input of
the pulse width modulation (PWM). The PWM gate signal
to control the buck-boost converter and, thus, maximum
power is tracked and delivered to the inverter.
4. Five-level cascaded H-bridge inverter topology
The multilevel inverter is best suited for the application
which demands the nest quality of the ac supply wave-
forms. This work presents a SVPWM control scheme,
which pertains fully to cascaded multilevel inverters. The
comparison of diode clamped and cascaded inverters are
shown in Table 2. When compared to diode clamped
inverters, cascaded inverter requires the least number of
components to achieve the same number of voltage levels.
A cascaded multilevel inverter consists of a series of H-
bridge (single-phase, full-bridge (FB)) inverter units. The
general function of this multilevel inverter is to synthesize
a desired voltage from several separate dc sources (SDCSs),
which may be obtained from batteries, fuel cells, or solar
cells. A three phase ve-level cascaded H-bridge circuit dia-
gram is shown in Fig. 4. Each SDCS is connected to H-
bridge inverter. The ac terminal voltages of dierent level
inverters are connected in series. An m-level cascaded H-
Fig. 3. Flow chart of the P&O MPPT.
232 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245
bridge inverter typically consists of 2(m 1) main switch-
ing devices, 2(m 1) main diodes and (m 1)/2 capacitors
on the DC bus. Unlike the diode-clamp inverter, the cas-
caded inverter does not require any voltage-clamping
diodes.
The phase output voltage is synthesized by the sum of
four inverter output voltages V
an
= V
a1
+ V
a2
+ V
a3
+ V
a4
.
Each inverter level can generate three dierent voltage out-
puts, +V
dc
, 0 and V
dc
, by connecting the dc source to the
ac output side by dierent combinations of the four
switches, S
p1
, S
p2
, S
n1
, and S
n2
. When the switches S
p1
and S
p2
, are turned ON, it gives V
a4
= +V
dc
. When the
switches S
n2
and S
n1
, turned ON, it gives V
a4
= V
dc
.
When the all switches are turned OFF, it gives V
a4
= 0.
Similarly, the ac output voltage at each level can be
obtained in the same manner. If N
S
is the number of dc
sources, the output phase voltage level is m = N
S
+ 1.
Controlling the conduction angles at dierent inverter
levels can minimize the harmonic distortion of the output
voltage. If the phase current i
a
, is sinusoidal and leads or
lags the phase voltage V
an
by 90, the average charge to
each dc capacitor is equal to zero over one cycle. Therefore,
all SDCS capacitor voltages can be balanced. Each H-
bridge unit generates a quasi-square waveform by phase
shifting its positive and negative phase-leg-switching tim-
ings. Table 3 shows the relationship between the output
voltage levels and switching states for the ve-level topol-
ogy is shown in Fig. 5. Switches S
px
and S
nx
(x = 1, 2, 3, 4) are arranged in pairs and operate in a com-
plementary mode where S
px
as positive switches and S
nx
as
negative switches. State condition 1 means the switch is
ON and 0 means the switch is OFF.
5. SVPWM algorithm
Dierent PWM techniques are applied for controlling
the active devices in a multilevel inverter (Colak et al.,
2011). In this paper, SVPWM technique is used to generate
PWM control signals to the inverter. Fig. 6 shows the space
Table 2
Comparison of diode clamped and cascaded multilevel inverter topologies.
S. No. Topology Diode clamped Cascaded
1 Power semiconductor switches 2(m 1) 2(m 1)
2 Clamping diodes per phase (m 1)(m 2) 0
3 DC bus capacitors (m 1) (m 1)/2
4 Balancing capacitors per phase 0 0
5 Voltage unbalancing Average Small
6 Applications Motor drive system STATCOM Motor drive system, PV, fuel cells, battery system
Fig. 4. Five-level cascaded inverter topology.
M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245 233
vector diagram for two-level inverter. Modulation index
(MI) is dened as in Eq. (8)
MI
V
P1
V
P1Six
8
In Eq. (8), V
P1
is the peak value of fundamental voltage
and V
P1Six
is the peak value of fundamental voltage at
six step operation. For a n-level cascaded topology V
P1
-
Six
= (2/p)(n 1)V
dc
, where V
dc
is the dc link voltage.
For a NPC topology V
P1Six
= (2/p)(V
dc
), this is same as
two-level inverter. The SVM is used to compensate the re-
quired volt-seconds using discrete switching states and their
ON-times produced by inverter.
In a two level inverter, ON-time calculation is based on
the location of reference vector within a sector S
i
, i = 1,
2 . . . , 6 for a two-level inverter, volt-second equation is,
V
z
T
s
V
X
T
a
V
Y
T
b
9
The volt-seconds in terms of components V
Z
, V
X
and V
Y
of
along a b axis are,
V
Z
a
T
s
T
a
0:5T
b
10
V
Z
b
T
s
hT
b
11
T
s
T
a
T
b
T
0
12
Table 3
Relationship between output level and switching states (1 indicates ON-states and 0 indicates OFF-states).
Output level Switching states
S
p1
S
p2
S
p3
S
p4
S
n4
S
n3
S
n2
S
n1
2V
dc
0 0 0 0 1 1 1 1
V
dc
1 0 0 0 1 1 1 0
0 0 0 1 0 1 1 1
0 0 1 0 1 0 1 1
0 1 0 0 1 1 0 1
0 1 1 0 0 1 1 0 0
0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0
1 0 0 1 0 1 1 0
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
+V
dc
1 1 1 0 1 0 0 0
0 1 1 1 0 0 0 1
1 0 1 1 0 0 1 0
1 1 0 1 0 1 0 0
+2V
dc
1 1 1 1 0 0 0 0
Fig. 5. One-leg circuit of ve-level cascaded inverter.
Fig. 6. Space vector diagram for two-level inverter.
234 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245
Solving Eqs. (10)(12), obtain for the calculation of ON-
times,
T
a
T
s
V
Z
a

V
Z
b
T
s
2h
_ _ _ _
13
T
b
T
s
V
Z
b
h
_ _
14
T
0
T
s
T
a
T
b
15
In Eqs. (13) and (14), h is height of the triangle of sector
S
i
fh 0:866 or

3
p
=2g, assuming that the sides of the
equilateral triangle are unity. In Eqs. (13)(15), T
S
= 1/
(2f
S
), f
S
is the switching frequency. Fig. 7 shows the sector
1 for two-level inverter.
Each sector can be split into (n 1) triangles, where n
indicates level of the inverter. For any given reference vec-
tor, the sector of operation and its angle within the sector is
determined by using Eqs. (16) and (17), respectively.
S
i
int
h
60
_ _
1 16
c rem
h
60
_ _
17
In Eqs. (16) and (17), h(0 6 h 6 360)is the angle of the ref-
erence vector with respect to a axis, c0

c 60

is the
angle within the sector and S
i
(1 6 S
i
6 6) is its sector oper-
ation, int and rem is standard math function of integer and
reminder. The space vector diagramof a three phase voltage
source inverter is a hexagon, consisting of six sectors.
SVPWM algorithm is to identify the triangle in which
the tip of the reference vector is located. Each triangle
can be treated as a vector of a two level inverter. The
ON-time can be calculated using small vector analogy
ON-time equation of the two-level inverter. Fig. 8 shows
the space vector diagram for ve-level inverter.
In each sector, triangle can be classied into two types.
Type 1 triangle has its base side at the bottom. Type 2 tri-
angle has its base side at the top. The triangle number D
j
can be determined in terms of two integer variables I
1
and I
2
, which are dependent on the position of reference
vector (V
a
, V
b
).
I
1
int V
a

V
b

3
p
_ _
18
I
2
int
V
b
h
_ _
19
Eq. (18) signies part of the sector between the lines
y

3
p

3
p
I
1
and y

3
p
x

3
p
I
1
1. This forms
one region. Eq. (19) signies part of the sector between
the lines y = hI
1
and y = h(I
1
+ 1). This forms another re-
gion. The tip of reference vector is situated at the intersec-
tion of these two regions inclined at 120 and forms
triangle or rhombus.
This rhombus is made of two triangles. Let (V
aS
, V
bS
)
are the co-ordinates of the reference vector with respect
to the origin of the rhombus.
V
aS
V
a
I
1
0:5I
2
20
V
bS
V
b
I
2
h 21
In Eqs. (20) and (21), (V
aS
/V
bS
) is the slope of the line be-
tween the origin of the rhombus and the reference vector
and it is compared with slope of the diagonal of the rhom-
bus which is

3
p
.
The slope comparison is done by evaluating inequality
V
bS
6

3
p
V
aS
and to determine the small vector V
Z
and
the exact triangle number D
j
. If the V
bS
6

3
p
V
aS
, which
indicates triangle of type 1 and these triangles are similar
to sector 1 of two-level inverter. The triangle number D
j
is obtained as
D
j
I
2
1
2I
2
22
If V
bS
>

3
p
V
aS

,
which indicates the triangle of type 2
and these triangles are similar to sector 2 of two-level.
The triangle number D
j
is obtained as
D
j
I
2
1
2I
2
1 23
In Eqs. (22) and (23), D indicates the triangle and j is the
triangle number and hence D
j
is an integer and signies
jth triangle in the sector. Using Eqs. (22) and (23), to iden-
tify triangle in a sector and the on times are calculated
using Eqs. (13)(15). The D
j
is formulated to provide a sim-
ple way of arranging the triangle, leading to ease of identi-
cation and extension to any level and it greatly simplies
the PWM process as switching state can be easily mapped
with respect to D
j
. The sector and switching states mapping
is shown in Table 4.
6. Inverter control
The inverter control circuit has the function to control
the active and reactive power. In the decoupled d-axis Fig. 7. Sector 1 for two-level inverter.
M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245 235
and q-axis current control loops, two PI controllers are
employed to eliminate current errors. The outputs of PI
controllers are inductor lter voltage references V

Ld
and
V

Lq
that are superimposed by V
gd
and V
gq
to generate the
inverter output voltage references V

d
and V

q
for SVPWM.
The current references i

d
and i

q
are provided by the output
of PV array.
At the end V
ref
is obtained, these are passed to inverter
control which gives outputs of pulses to drive the multilevel
inverter switches. As there is dc-dc buck-boost converter
between the PV generator and the inverter, to get the
MPPT function.
7. FPGA implementation
FPGA is a silicon chip containing an array of logic con-
gurable blocks, consists of congurable logic block
(CLB), digital clock manager (DCM), and hardware multi-
pliers. The FPGA used in this project is Xilinx Spartan 3A,
which has 1.8 Million gates device. An ASIC can perform a
single function for the lifetime of the chip whereas FPGA
can be reprogrammed to perform dierent function in a
matter of microseconds.
The design used Xilinx development tools, namely
works view, and is realized in a single FPGA chip with
no external memory. The whole system is implemented in
only a single chip and more reliable, faster design, verica-
tion time, and high performance. A standard FPGA design
ow should include circuit design and entry, functional
simulation, synthesize, post synthesize simulation, place-
and-route, post place-and-route simulation, board level
simulation and download and debug. The block diagram
for FPGA implementation of SVM control strategy is
shown in Fig. 9. The SVM generator based on nite state
machine (FSM) is to implement the SVM algorithm. The
FSM consists of six states, which are waiting, a b trans-
formation, sector selection, triangle determination, switch
states judgment, and dwell time conguration.
In this programming, FPGA using VHDL and coding
are used to generate the SVPWM for the inverter circuit.
Simulation steps are as follows.
1. Initialize system parameters using FPGA.
2. Perform VHDL coding to:
i. Determine sector.
ii. Determine time duration T
a
, T
b
, T
0
.
iii. Determine the switching time of each sector.
iv. Generate the inverter output voltage.
3. View the SVPWM waveforms through Xilinx.
8. Simulation results
Simulations are performed by using MATLAB/simulink
for the proposed system. The SVPWM switching strategy is
used in this paper. The SVPWM output is generated from
Fig. 8. Space vector diagram for ve-level inverter.
Table 4
Sector and switching states mapping.
Sector Phase A Phase B Phase C
S
1
S
a
S
b
S
c
S
2
S
b
S
c
S
a
S
3
S
c
S
a
S
b
S
4
S
a
S
b
S
c
S
5
S
b
S
c
S
a
S
6
S
c
S
a
S
b
236 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245
this simulink module. This involves determining the posi-
tion of reference vector according to fundamental fre-
quency f = 50 Hz, sampling frequency f
s
= 10 kHz and
time. According to sector wherein the reference vector is,
determine the switching sequence and to calculate the time
for dierent switching states. The switching instant of a
SVPWM pulse waveform is shown in Fig. 10. The modula-
tion index determines the shape of the output voltage of the
inverter. The simulation block diagram for proposed sys-
tem is shown in Fig. 11.
The MPPT using P&O tracks the operating point
quickly and accurately in irradiance level. The simulation
result of P&O MPPT tracking is shown in Fig. 12. Simula-
tion result for the two-level inverter is shown in Fig. 13.
Simulation result for the three-level inverter is shown in
Fig. 14. Simulation result for the proposed ve-level inver-
ter is shown in Fig. 15. This shows that the generated line-
to-line voltage is much improved with the level of inverter.
The decoupling of the voltage loops V

d
and V

q
is good,
since the V

q
remains constant under variations which
shows high dynamic performance of the controllers. The
performance of the P&O with the three phase ve-level cas-
caded H-bridge inverter also shows that output of the PV
follows its reference.
The THD levels of three phase two-level, three-level and
ve-level are compared in Table 5. This proves that the
proposed scheme can reduce the THD which is indispens-
able condition for PV system. The results from ve-level
SVPWM inverter are compared with those from two-level
SVPWM and three-level SVPWM inverter in terms of
THD. The THD measurement for the two-level inverter
is shown in Fig. 16. The THD measurement for the
Fig. 9. Block diagram for FPGA implementation SVM control with nite state machine.
Fig. 10. Switching instant of a SVPWM pulse waveform.
M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245 237
three-level inverter is shown in Fig. 17. The THD measure-
ment for the proposed ve-level inverter is shown in
Fig. 18. These shows the THD, which is highly reduced
as the level of inverter, increases. From the results it is
observed that the generated voltage spectrum is very much
increased with the level of inverter. The THD measurement
Fig. 11. Simulation block diagram for the proposed system.
238 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245
of the two-level inverter is 16.10% and three-level inverter
is 9.08%. The THD measurement of the proposed ve-level
inverter is 5.68%.
The THD values of the proposed inverter are lower than
that of the ve-level diode clamped multilevel inverter
(DCMLI) using sinusoidal PWM (SPWM) technique (Ravi
et al., 2011). The THD measurement of three-level DCMLI
is 35.27% and ve-level DCMLI is 13.11% (Ravi et al.,
2011) as shown in Table 6. The fundamental component
of the output voltage is increased with the level of inverter.
This proves that the proposed scheme can reduce the THD
which is necessary criterion for PV system.
9. Experimental results
The simulation results are veried experimentally using
a FPGA Spartan 3A kit. The proposed two-level and
three-level inverter is tested with a PV array and the ratings
Fig. 12. Simulation result of P&O MPPT tracking algorithm.
Fig. 13. Line-to-line voltage (V
ab
) two-level inverter.
Fig. 14. Line-to-line voltage (V
ab
) three-level inverter.
M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245 239
of PV module are shown in Table 1. The 1200 V, 25 A,
IGBT is used in cascaded H-bridge inverter. The 415 V,
1.8 A, 50 Hz, 1440 rpm, 1 HP three phase induction motor
is used as load. Prototypes two-level and three-level voltage
source inverter, to validate the simulation results are built.
VHDL code is developed to examine the switching pat-
terns of SVPWM method. This code is synthesized using
Xilinx ISE. The FPGA based generalized SVPW modula-
tor is applied to control these voltage source inverter to
track the given reference. The generation of SVPWM pulse
waveform for two-level inverter through Xilinx show in
Fig. 19. The generation of SVPWM pulse waveform for
three-level inverter through Xilinx show in Fig. 20.
The proposed system is tested in laboratory during
stand-alone operations. The block diagram for the control
system is shown in Fig. 21. The photograph of the experi-
mental setup that includes the FPGA is shown in Fig. 22.
Fig. 15. Line-to-line voltage (V
ab
) for proposed ve-level inverter.
Table 5
Total harmonic distortion for the proposed system.
No of levels THD (%)
2 16.10
3 9.08
5 5.68
Fig. 16. THD measurement for two-level inverter.
Fig. 17. THD measurement for three-level inverter.
240 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245
The solar panel is not shown in photograph. The voltage
signals are scaled down to match the FPGA analog input
level. These oscilloscope graphs demonstrate the good
quality of the obtained voltage waveforms, conrming sim-
ulation results. The triggered signals generated by the
Fig. 18. THD measurement for proposed ve-level inverter.
Table 6
Comparison between THD for proposed system with SPWM.
No of levels SPWM (%) Proposed SVPWM (%)
3 35.27 9.68
5 13.11 5.68
Fig. 19. Generation of SVPWM pulse wave for two-level inverter.
Fig. 20. Generation of SVPWM pulse wave for three-level inverter.
M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245 241
FPGA control the transistors of the multilevel inverter.
The two-level and three-level three phase cascaded inverter
with dierent switching states, are used in the experiments.
The switching frequency is 10 kHz. The THD levels of two-
level and three-level inverter are compared in Table 5. The
experimental system conguration is the same as that in
simulations.
The experimental result of controlling a two-level inver-
ter is shown in Fig. 23. The experimental result of control-
ling a three-level inverter is shown in Fig. 24. The
experimental results show that the FPGA based PV system
having output line-to-line voltage with lower THD. Better
performance can be obtained when the modulation index is
increased. Therefore, the overall eciency of PV system
depends on the multilevel conversion with SVPWM con-
trol, P&O MPPT and DC-DC conversion. The use of
FPGA allows very high speed control loops, resulting in
signicantly enhanced performance. In the output, wave-
forms have limited harmonic content; therefore, a small
and light output lter is sucient for fullling electromag-
netic interference rules, thus reducing size and cost.
10. Conclusion
This paper presents FPGA based multilevel cascaded
inverters with SVPWM algorithm for photovoltaic system.
The conguration for the proposed system is designed and
simulated using MATLAB/simulink and implementation
in FPGA. The acceptable results for the proposed multi-
level cascaded inverter are summarized as follows.
Fig. 21. Basic structure of the experimental setup.
Fig. 22. Photograph of experimental setup.
242 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245
(1) The proposed system produces less dv/dt voltage
stress imposed on the switching devices and the
capacity to operate at a lower switching frequency.
(2) The P&O MPPT algorithm does not require any
additional hardware components. The PV system loss
decreases, execution speed increases, and requires less
conversion time.
(3) The SVPWM can provide proper selecting switching
states of the inverter, optimization of switching pat-
terns, and improving dc link voltage utilization. It is
more ecient than any other conventional PWM
methods.
(4) Embedding SVPWM in an FPGA creates the
increased controller bandwidth, high speed input out-
put response enables a precise switching, the exible
adjustment of dead time, resulting in the reduction
of voltage harmonics which is very benecial for the
output voltage quality.
(5) The FPGA can be more ecient than the conven-
tional controller due to fast prototyping, software
design and simple hardware design.
(6) It is seen from the simulation results that the gener-
ated voltage spectrum is very much improved with
increase in the level of the inverter for PV system.
The THD is highly reduced as the level of inverter
increases (5.68%). It is quite low as compared with
the conventional two-level inverter (16.10%) and
three-level inverter (9.08%). Hence, the optimum
power is transferred to drive a 1 HP three phase
induction motor.
Fig. 23. Line-to-line voltage (V
ab
) of two-level inverter.
Fig. 24. Line-to-Line voltage (V
ab
) of three-level inverter.
M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229245 243
(7) The THD value of the ve-level DCMLI with SPWM
(13.11%) is higher than the THD value of the pro-
posed ve-level with SVPWM (5.68%).
(8) The results obtained are full of promise to use the
multilevel cascaded H-bridge inverter with SVPWM
strategy are gained importance in high voltage, high
power, and high performance applications such as
PV generation system. The proposed system solves
commutation loss, electromagnetic interference, har-
monics and high frequency switching problems.
(9) The level of the inverter increases, the harmonic con-
tent of the output voltage waveform decreases. Thus,
the output voltage quality increases. It can be easily
extended to the n-number of levels.
Acknowledgment
One of the authors of this paper (P.S. Manoharan)
acknowledges University Grant Commission (UGC), India
for sanctioning the funding under major research project,
vide reference F.No. 40-468/2011 (SR).
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