A Minimal CISC Processor Architecture for Field Programmable Gate Arrays.

Michael Freeman,
Dept. Computer Science, University of York, UK
mjf@cs.york.ac.uk

1. Introduction [2]. This lead to the development of microprogrammed

control units that are commonly found in CISC processors,
Decreasing cost and increased complexity of modern field where each machine instruction is interpreted by a
programmable gate array (FPGA) devices, such as microprogram stored in control memory within the
Xilinx’s Spartan 3[1], have allowed the development of processor. These microprograms are composed of a series
true system on a chip (SOC) architectures for embedded of microinstructions, which themselves can be composed
micro-controller and ubiquitous computing applications. of a series of nanoinstructions [3] defining the control
To minimize the size and, therefore, the cost of the signals required to perform the desired machine operation,
required FPGA, consideration must be given to matching as shown in figure 1.
the desired functionality to the FPGA’s resources. This
paper describes the initial work in comparing software,
firmware and hardware biased solutions and a
reconsideration of complex instruction set computer
(CISC) based processor architectures to achieve this aim.
One of the main developments in FPGA design that has
permitted true SOC architectures to be developed is the
increasing amount of onchip memory. In general, this can
be divided into two types; distributed and block RAM.
Distributed RAM is implemented from lookup tables
Figure 1 Microprogrammed control memory hierarchy
within the general purpose logic resources of the FPGA,
whereas block RAM is a true dual port memory element,
The use of a second control memory i.e. nanocontrol
with configurable address and data bus widths, organized
memory, is not always required. However, this two level
in columns throughout the FPGA. To maximise the speed
approach can reduce the total amount of control memory
and area performance of these devices and, therefore,
required. The advantage of a microprogrammed controller
minimize cost, consideration of these hardware resources
is its flexibility and reduced general purpose logic
within the FPGA must be made before a design solution is
requirements, allowing a standard hardware architecture to
made.
be used for a number of applications, i.e. changing the
A typical embedded FPGA micro-controller is normally
processor’s firmware (control memory) will permit the
based on a RISC processor core. This processor uses block
same architecture to execute different instruction sets.
RAM for its data and instruction memory. However, its
One of the main aims of this work is to develop a
instruction decoder and control logic are constructed from
standardized FPGA based hardware module that can be
general purpose logic, reducing FPGA resources that are
individually configured to the desired application e.g.
available for peripheral devices. An alternative solution to
embedded micro-controller and ubiquitous computing [6].
minimise this problem is the CISC processor core. This
It is hoped that with the large amounts of onchip memory
processor again uses block RAM for its data and
available in modern FPGA devices, a CISC processor
instruction memory and also for its control logic, as part of
architecture will be able to minimise the area requirements
a microprogrammed (firmware) controller. This frees up
within the final FPGA device. By moving the processor’s
general purpose logic, allowing more support to be
functionality out of hardwired logic into block RAM and
included within the processor for specific applications, for
optimising the microcontrol and nanocontrol memory
peripheral devices, or simply to allow smaller, cheaper
widths to minimise storage requirements, general purpose
FPGAs to be used.
logic within the FPGA will be freed up for other
In the 1950s Professor M.V. Wilkes first recognised that
peripheral devices, reducing the required size and cost of
a processor’s control unit was implemented as a series of
the FPGA device.
discrete steps much like an ordinary computer program
2. Experimental process
At this time a single control memory, minimal CISC
processor (MCP) core has been designed and synthesized
in VHDL. The design emphasis for this version of the
processor is to minimise hardware requirements whilst
supporting fast context switching, as shown in figure 2.
Figure 2 A minimal CISC processor core
This processor takes advantage of a microprogrammed
controller’s ability to execute different instruction sets.
The controller’s instruction decoder (Id) and microcontrol
memory (uCm) have been modified to allow this processor
to execute existing 8051 code, removing the need to
develop specialized software tools. The size of this
processor is further reduced by only supporting those
instructions required by the application i.e. the instruction
decoder is edited, removing instructions that are not
required; microcontrol memory is not altered since it is a
fixed dedicated resource. Future versions of this processor
will be tuned to support the particular requirements of
embedded processor applications.
To assess the performance of this CISC processor
architecture, a remote sensor node case study was chosen.
In this application, data from a variety of sensors are
processed and logged within each node and retrieved by a
centralised controller node via a wireless data link. To aid
testing, a serial port is also included to allow debugging
information to be sent to a data terminal. All peripheral
devices are connected to the CPU core using a single bus
master wishbone bus[4]. Three design solutions are to be
implemented:
?? Software biased : based on Xilinx’s PicoBlaze, 8 bit
RISC processor core[5]. All input and output
peripherals are emulated using bit banging techniques
i.e. using a periodic interrupt timer and general
purpose IO, the serial and radio ports are
implemented using software routines.
?? Firmware biased : based on the MCP CISC processor
core previously described. Like the software biased
approach, all input and output peripherals are
emulated using bit banging techniques with
microprogram support.
?? Hardware biased : based on Xilinx’s PicoBlaze, 8 bit
RISC processor core. All input and output peripherals
are implemented as separate hardware cores,
connected to the processor via the wishbone bus.
Initial results have been produced for the software and
firmware versions using a Spartan 3, Xc3s200 device with
XST synthesis tools :
?? 8 bit PicoBlaze: 150 slices, 64MHz, 2 block RAM
?? 8 bit MCP: 120 slices, 69MHz, 3 block RAM
?? 16 bit MCP: 188 slices, 35MHz, 3 block RAM
The results for the MCP compare favourably with existing
processor cores, showing a reduction in the number of
required slices. In future work it is hoped to show that a
firmware biased solution will have significant reductions
in area requirements when compared to software and
hardware biased solutions and increased speed
performance when compared to the software biased
solution.
3. Conclusions
This paper has presented the initial development work of a
minimal CISC processor for FPGA devices. Implementing
microcontrol memory in dedicated block RAM storage
elements reduces the amount of general purpose logic
required by this processor core, reducing the size and cost
of the required FPGA device. The performance of this
processor is then compared to existing software and
hardware biased approaches.
4. References
[1] Xilinx, (July 2003), Spartan – 3 1.2V FPGA Family:
Functional description, DS099-2 (v1.2), web site:
http://www.xilinx.com
[2] Katzan H., (1980) Microprogramming primer, McGraw-
Hill, ISBN 0-07-033387-4
[3] Hayes J.P., (1988), Computer architecture and organization,
McGraw-Hill, ISBN 0-07-027366-9
[4] The wishbone service center, web site:
http://www.silicore.net/wishbone.htm
[5] Chapmen K., February (2003), PicoBlaze 8 bit
microcontroller for Virtex-E and Spartan-II/IIE devices,
XAPP213(v2.1), web site: http://www.xilinx.com
[6] Freeman M., Ubiquitous development kit, web site:
http://www.cs.york.ac.uk/amadeus/projects/centre-udk/