1 Introduction To Analog IC Design

ICTP Microprocessor Laboratory Second Central American Regional Course on Advanced VLSI Design Techniques Benemrita Universidad Autnoma
de Puebla, Puebla, Mexico 29 November 17 December 2004
Introduction to Analog Design in Submicron CMOS Technologies

Giovanni Anelli CERN - European Organization for Nuclear Research Physics Department Microelectronics Group CH-1211 Geneva 23 Switzerland Giovanni.Anelli@cern.ch
Puebla, December 2004
The MOST important thing
Giovanni Anelli, CERN
A second tip
4kT i = f R
2 n
2 in
1 T/2 Pav = lim x 2 (t )dt T T / 2
fmax =
1 gm 2 Cgs
H(s) =
Vout (s) 1 = Vin (s) sRC

( x )2 22
K v 1 1 = 4kTn + 2 a f gm Cox WL f
IDS = ID0
W e L
VGS n t
(1 e
V DS n t
p( x ) =
1 e 2
IDS =
I I.C. = DS 2 2n t
( VGS VT )2 2n
d L = n2 F( ) d l
2 / =
2 A
WL
2 AC ox
WL
0 1 + ( VGS VT )
En = Z m0 q 2 2 8 2 0h n
2 4
kT t = q
1 1 F(I.C.) = + 2 6 1 4
I.C.
1 + 4 I.C. + 1
gm =
2
IDS = ( VGS VT ) = 2 IDS VGS n n

R = lw nd = A A
Vth
t ox 4 N = Const WL
E n ,DUT ( f ) =
Vn2,TOT ( f ) Vn2,BGD ( f ) G(f )

2
r0 =
1 1 V L = = E gds IDS _ SAT IDS _ SAT
The last warning before we start

The transparencies I will show you are sometimes quite full of details. You will not have the time to digest all these details this week, but I wanted to prepare the transparencies so that you will have a COMPLETE material for future reference. During the presentation, I will help you in identifying in the transparencies and in the formulas the most important issues that you should retain. I also made a special effort in referencing all the sources (books and papers) I have been using when preparing the lectures. This should help you in finding easily what you do not find in the transparencies
Puebla, December 2004 Giovanni Anelli, CERN
Outline
Semiconductor physics
Silicon and silicon dioxide properties Band diagram concept Intrinsic and doped semiconductors Carrier mobility in silicon The MOS transistor DC characteristics Important formulas Small signal equivalent circuit Some cross sections of real integrated circuits
CMOS technology: an analog designer perspective
Outline
Insulators and (semi)conductors
S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 1
Physical Properties of Si and SiO2

at room temperature (300 K)
Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, p. 11.
Silicon crystalline structure

Orbitals filling Diamond lattice structure
3p2 3s2 2p6 2s2 1s2 a = 0.513 nm for Silicon

Nucleus
S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 5. Linus Pauling, General Chemistry, Dover, 1988, p. 128.
Covalent bonding
From energy levels to bands

Allowed energy levels
E0 (reference) En E3
Z 2m0 q 4 En = 2 2 8 2 h n 0
E2
Z: atomic number m0: free electron mass q: electron charge 0: permittivity free space h: Plancks constant n: positive integers (level number)
Allowed energy band

putting more atoms together (and remembering Paulis exclusion principle)
Forbidden energy gap
E1
x
Energy-band diagrams
Insulator
Conduction Band Conduction Band Energy Gap Energy Gap Valence Band Valence Band Conduction Band
Semiconductor
Conductor
Conductor
Conduction Band
Valence Band
Empty allowed energy band
Full allowed energy band
Intrinsic and doped silicon
Fictitious particle
Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, pp. 10, 13, 14. E. S. Yang, Microelectronic Devices, McGraw-Hill International Editions, 1988, pp. 9, 15.
Donors and acceptors
Intrinsic Semiconductor: small amount of impurities compared to the thermally generated electrons and holes Donor level: the allowed energy level provided by a donor is neutral when occupied by an electron and positively charged when empty Acceptor level: the allowed energy level provided by an acceptor is neutral when empty (= occupied by a hole) and negatively charged when occupied by an electron (= empty)
Carrier density vs Temperature

N-type semiconductor Electrons are the majority carriers
Intrinsic carrier density (= hole density)
n i2 = N c N v e
S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 27
Eg kT
Mobility vs T and ND
ND: doping concentration
qm vd = E = nE me
vd = drift velocity m = mean free time between collisions me = conductivity effective mass E = electric field
S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 33.
Mobility vs doping
1 1 1 1 = + + L I S
= total mobility L = mobility due to lattice scattering I = mobility due to impurity scattering S = mobility due to surface scattering (the dominating factor in MOS transistors) It is like for resistors in parallel: the smaller dominates!
Carrier velocity vs Electric Field
R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd Edition, John Wiley and Sons, 1986, p. 36.
Resistivity vs doping
1 = q(n n + p p )
q = electronic charge = resistivity n, p = carrier concentration n, p = carrier mobility
Outline
The MOS transistor
y z x
DRAIN GATE SUBSTRATE SOURCE
iDS = g m v GS
Transconductance
Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999, p. 35
CMOS technology
NMOS
sub S G D S
PMOS
G D well
p+
n+
p-substrate Polysilicon Oxide Electrons Holes
n+
p+
p+
n-well
n+
n+ source G n+ drain
NMOS layout
Linear and Saturation regions

S G D
LINEAR REGION (Low VDS): Electrons (in light blue) are attracted to the SiO2 Si Interface. A conductive channel is created between source and drain. We have a Voltage Controlled Resistor (VCR).
n+
n+
n+
n+
SATURATION REGION (High VDS): When the drain voltage is high enough the electrons near the drain are insufficiently attracted by the gate, and the channel is pinched off. We have a Voltage Controlled Current Source (VCCS).
Drain current vs Drain voltage

3.0E-05
Locus of IDS_SAT vs VDS_SAT

2.5E-05
2.0E-05
IDS [ A ]
Output conductance
1.5E-05
1.0E-05
Saturation region (VCCS)
@ three different VGS

Linear region (VCR)
5.0E-06
0.0E+00 0.0 0.5 1.0 1.5 2.0 2.5
V DS [ V ]
Equations: strong inversion

LINEAR REGION:
VDS V VT < GS = VDS _ SAT n
IDS = ( VGS
gm =
nVDS )VDS VT 2
Transconductance:
IDS = VDS VGS
SATURATION REGION:
VDS > VGS VT = VDS _ SAT n
IDS =
gm =
( VGS VT )2 2n
Transconductance:
g m + g mb 1 .x gm
IDS = ( VGS VT ) = 2 IDS n VGS n

= C ox W L
C ox = SiO 2 t ox
n=
gmb =
IDS VBS
Drain current vs Gate voltage

2.E-03 1.E-03 1.E-03
Linear region (green) and saturation region (red) High field (vertical and longitudinal) effects
IDS [ A ]
1.E-03 8.E-04 6.E-04 4.E-04 2.E-04 0.E+00 -0.4 0.0
Subthreshold region
0.4
0.8
1.2
1.6
2.0
2.4
V GS [ V ]
Log(IDS) vs VGS
1.E-02 1.E-03 1.E-04 1.E-05
WEAK INVERSION THRESHOLD VOLTAGE
IDS [ A ]
1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12
STRONG INVERSION
SUBTHRESHOLD SLOPE
LEAKAGE CURRENT
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
2.4
V GS [ V ]
Equations: weak inversion

IDS = ID0 W e L
VGS n t
(1 e
VDS n t
If
IDS = ID0
V DS > 4 n t W e L
VGS n t
then the drain current does not depend on VDS any longer (saturation)
gm =
I IDS = DS VGS n t
Almost like a bipolar transistor!
t =
kT 25 mV @ 300 K q
Transcond. vs Gate voltage

1.E-04 9.E-05 8.E-05 7.E-05
Measurement made in the linear region
gm [ S ]
6.E-05 5.E-05 4.E-05 3.E-05 2.E-05 1.E-05 0.E+00 -0.35
0.05
0.45
0.85
1.25
1.65
2.05
2.45
V GS [ V ]
Output conductance
3.0E-05 2.5E-05 2.0E-05
IDS [ A ]
1.5E-05
1.0E-05
Dashed lines: ideal behavior
IDS ID ID
5.0E-06
0.0E+00 0.0 0.5 1.0 1.5 2.0 2.5
VD
VD
VDS
V DS [ V ]
n+
L L
n+
G out
ID I L = = V V L - L
Equations: output conductance

3.0E-05 2.5E-05
IDS =
( VGS VT )2 (1 + VDS ) 2n
VGS VT = n
2.0E-05
IDS [ A ]
1.5E-05
VDS _ SAT
IDS _ SAT =
0.0 0.5 1.0 1.5 2.0 2.5
1.0E-05
5.0E-06
0.0E+00
2 ( VGS VT )2 = nVDS _ SAT 2n 2
V DS [ V ]
gout = gds =
IDS = IDS _ SAT VDS =
r0 =
1 1 V L = = E gds IDS _ SAT IDS _ SAT
1 L where L = f ( VDS , NDoping ) VDS L L

Equations: addendum
Bulk effect
VT =
Vsb + Si Si
2q SiNa Cox
Source parasitic resistance Vertical electric field effect
' gm =
gm 1 + gmR S
0 1 + ( VGS VT )
Maximum frequency
fmax
1 gm 1 = = ( VGS VT ) 2 2 Cgs 2 nL
in s.i.
K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, Chapter 1
Equations: velocity saturation

For low values of the longitudinal electric field, the velocity of the carriers increases proportionally to the electric field (and the proportionality constant is the mobility). For high values of the electric field (3 V/m for electrons and 10 V/m for holes) the velocity of the carriers saturates.
IDS _ V .S. = WC ox v sat ( VGS VT ) with v sat = 10 7
cm s
gm _ V .S. = WC ox v sat
fmax_ V .S. 1 gm 1 v sat = = 2 Cgs 2 L
gm / ID vs log(ID / W)
30
Weak Inversion (W.I.)
25
W.I.
20
gm =
IDS n t
gm 1 = ID n t
gm / I D
15
Strong Inversion (S.I.)

S.I. & V.S.
gm = 2 IDS n
gm = ID 2 1 n IDS
I. M.
10 5
0 1E-11
Velocity Saturation (V.S.)

1E-09 1E-07 1E-05 1E-03
ID / W
g m = WC ox v sat
gm WC ox v sat = IDS IDS
Log(gm / ID) vs log(ID / W)

100
10
gm / I D
Slope = - 0.5 Strong inversion
Slope = - 1 Velocity saturation

0.1 1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03
ID / W
The poor PMOS transistor

S G D well
SOURCE GATE WELL DRAIN
VT < 0 V VGS < 0 V IDS < 0 V
p+
p+
n-well
n+
0.0E+00 -5.0E-06
IDS
= ( VGS VT )2 2n
IDS [ A ]
0.E+00 -2.E-04 -4.E-04 -6.E-04 -8.E-04 -1.E-03 -1.E-03 -1.E-03 -2.E-03 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4
IDS [ A ]
-1.0E-05 -1.5E-05 -2.0E-05 -2.5E-05 -3.0E-05 -2.5
gm =
IDS = VGS
-2.0
-1.5
-1.0
-0.5
0.0
VDS [ V ]
= ( VGS VT ) = n = 2 IDS n
VGS [ V ]
Small-signal equivalent circuit

G D
gm v gs
r0
IDSQ
= ( VGSQ VT )2 2n
S
This equation fixes the bias point This equation defines the small signal behavior
iDS = g m v GS
K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, p. 24.
Small-signal equivalent circuit

G
Cgd Cgs gm v gs gmb vbs r0
Cgb
C sb
Cdb
B
The real thing!
SOI technology from IBM

http://www-3.ibm.com/chips/gallery/ Puebla, December 2004 Giovanni Anelli, CERN
The real thing!
Metallization examples
http://www-3.ibm.com/chips/gallery/ Puebla, December 2004 Giovanni Anelli, CERN
Why is CMOS so widespread?

The IC market is driven by digital circuits (memories, microprocessors, ) Bipolar logic and NMOS - only logic had a too high power consumption per gate Progress in the manufacturing technology made CMOS technologies a reality Modern CMOS technologies offer excellent performance (especially for digital): high speed, low power consumption, VLSI, low cost, high yield
CMOS technologies occupies an increasing portion of the IC market

and this is why we will only talk about CMOS.
The next three lectures

Lecture 2: Noise and Matching in CMOS (Analog) Circuits Lecture 3: Scaling Impact on Analog Circuit Performance Lecture 4: Basic Building Blocks for Analog Design

1 Introduction To Analog IC Design

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ICTP Microprocessor Laboratory Second Central American Regional Course on Advanced VLSI Design Techniques Benemrita Universidad Autnoma

de Puebla, Puebla, Mexico 29 November 17 December 2004

Introduction to Analog Design in Submicron CMOS Technologies

Puebla, December 2004

The MOST important thing

Puebla, December 2004

Giovanni Anelli, CERN

1 T/2 Pav = lim x 2 (t )dt T T / 2

Vout (s) 1 = Vin (s) sRC

IDS = ( VGS VT ) = 2 IDS VGS n n

Vn2,TOT ( f ) Vn2,BGD ( f ) G(f )

1 1 V L = = E gds IDS _ SAT IDS _ SAT

Puebla, December 2004

Giovanni Anelli, CERN

The last warning before we start

CMOS technology: an analog designer perspective

Puebla, December 2004

Giovanni Anelli, CERN

CMOS technology: an analog designer perspective

Puebla, December 2004

Giovanni Anelli, CERN

Insulators and (semi)conductors

Puebla, December 2004

Giovanni Anelli, CERN

Physical Properties of Si and SiO2

Puebla, December 2004

Giovanni Anelli, CERN

Silicon crystalline structure

3p2 3s2 2p6 2s2 1s2 a = 0.513 nm for Silicon

Puebla, December 2004

Giovanni Anelli, CERN

From energy levels to bands

Allowed energy band

Forbidden energy gap

Empty allowed energy band

Full allowed energy band

Puebla, December 2004

Giovanni Anelli, CERN

Intrinsic and doped silicon

Puebla, December 2004

Giovanni Anelli, CERN

Donors and acceptors

Puebla, December 2004

Giovanni Anelli, CERN

Carrier density vs Temperature

Intrinsic carrier density (= hole density)

Puebla, December 2004

Giovanni Anelli, CERN

Puebla, December 2004

Giovanni Anelli, CERN

Puebla, December 2004

Giovanni Anelli, CERN

Carrier velocity vs Electric Field

Puebla, December 2004

Giovanni Anelli, CERN

Puebla, December 2004

Giovanni Anelli, CERN

CMOS technology: an analog designer perspective

Puebla, December 2004

Giovanni Anelli, CERN

The MOS transistor

DRAIN GATE SUBSTRATE SOURCE

Puebla, December 2004