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Topics in Randomization
Advantages of Randomization Constrained Random Simulation Constraint Randomization Object Randomization In-line constraints Solving constraints Randomization techniques Random Case Random Number Functions

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Advantages of Randomization
Directed testing detects the bugs you expect but Random testing detects the bugs you did not expect. Automatic stimulus generation
Change the characteristics of the data driving the DUT

Random setting of parameters

Select ports, addresses, operational parameters randomly

A random tests behavior depends on the seed

If you run the same test with the same seed, you will get the same behavior If you run the same test with many different seeds, you will get the equivalent of many different tests

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Constrained Random Simulation

Valid Inputs Specified as Constraints Test Scenario
Random Input Generator Constraints
DUT

Constraint Solver

Valid Inputs

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Randomization Example
Program test; class Transaction; rand bit [31:0] in_1,in_2,data[]; // Dynamic array randc bit [2:0] in_c; // Cyclic Randomization constraint c_length { data.size inside {[50:500]}; } // Limit array size endclass Transaction tx; initial begin tx = new(); assert(tx.randomize()); send(tx); end endprogram

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Constraint Randomization
Purely random stimulus takes too long to do something interesting So we need to limit the possible stimulus with constraint blocks Constraint distribution weights forms the basis for Random testbench Distribution weights can be variables or constants
:= assigns weight to each element :/ divides weight evenly in range
Constraint c_data { data.size <= 500; data.size > 50; In_c == 0; cntrl inside {[2:10], 20, 40, [100:107]}; if (test_mode == CONGEST) dest inside {[in_1-100:in_1+100]};} constraint c_long {data.size > 5000;}

constraint c_0 { src dist {0:=30, [1:3]:=60}; dst dist {0:/30, [1:3]:/60}; }

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Array Constraints
Constrain its size, individual elements, or all elements
class C; rand bit [5:0] ary[]; constraint cc {ary.size inside {[1:5]}; ary[0] > 0; foreach (ary[i]) if (i > 0) ary[i] > ary[i-1]);} function void pre_randomize; ary.delete; endfunction endclass

Output ary[0] = 1; ary[1] = 2; ary[2] = 33; ary[3] = 39; ary[4] = 40

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Object Randomization
Random variables
rand returns values over the entire range randc random cyclic value up to 16 bits

Object variables are randomized by randomize() The method is automatically available to classes with random variables. Returns a 1 upon success, 0 on failure

Optional: pre_randomize() & post_randomize() void functions which will be called automatically
pre_randomize() set up random weights post_randomize() cleanup calculations like CRC

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In-line Constraints
Constraints may be defined at the time of randomization
Allows test-specific constraints Dont modify the original class for just a single test In-line constraints are additive with existing class constraints Supports all SystemVerilog constraints and distributions
initial begin Transaction tx = new(); s = tx.randomize() with {in_1 >= 50; in_1 <= 1500; in_2 < 10;}; driveBus(tx); // force in_1 to a specific value s = tx.randomize() with { in_1 == 2000; in_2 > 10;}; driveBus(tx); end

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Solving Constraints
The solver has to handle algebraic factoring, complex Boolean expressions, mixed integer and bit expressions and more. All constraints interact bidirectional and are solved concurrently Solving rules are related to precedence, sign extension, truncation and wrap-around when creating constraints
Conditional operator: if else if else Behaves like a procedural if, except the conditionals are evaluated bi -directionally. Equivalent to implication. Implication Operator: -> Short version of if Ex: (mode == SMALL) -> (data.size < 10); Global Constraints: x < other object.y; References to rand object data members in the constraints get solved simultaneously Variable ordering: solve x before y; Otherwise all constraints solved simultaneously

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Randomization Techniques
Watch out for signed variables What are legal values for first and second? class Environment; rand byte in_1,in_2; constraint c { in_1 + in_2 < 8h40;} endclass Make instances rand Or they wont be randomized Dont call randomize() in new() constructor Test may want to change constraints first Use rand_mode to make a variable random / non-random env.in_1.rand_mode(0); Just replace result of randomization for a directed test

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Randomization Techniques cont..

If a constraint in a test needs to be modified, Use a variable in the constraint
class random; rand int size; int max_size = 100; constraint c { size inside {[1:max_size]}; } constraint c { size inside {[1:10]};} endclass

Extend the base class to override original constraint

class big extends random; constraint c {size inside {[1:1000]};} endclass

Constraint_mode() can be used to turn on/off randomization

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Random Case
Randomization can be done without a class? Use randcase or $urandom_range
randcase
2: len = $urandom_range(0, 2); // 20%: 0, 1, or 2 5: len = $urandom_range(3, 5); // 50%: 3, 4, or 5 3: len = $urandom_range(6, 7); // 30%: 6 or 7 endcase

Useful for creating single variable, stateless code, or nested set of actions Constrained randomization is easier to modify, and can make state variables for scoreboard The bad_crc variable can be used for both generating stimulus and checking the response

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Random Number Functions

$random() :-Flat distribution, signed 32-bit random $urandom() :-Flat distribution, unsigned 32-bit random $urandom_range() :-Flat distribution over a range $dist_exponential() :-Exponential decay $dist_normal() :-Bell-shaped distribution $dist_poisson() :-Bell-shaped distribution $dist_uniform() :-Flat distribution

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Summary
Constrained-random stimulus generation feature in SystemVerilog helps in creating a robust verification environment SystemVerilog offers alternatives in generating random stimulus

For detailed information visit our website:

http://www.systemverilog.in/random-constraints-examples.php

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