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Computer Organization & Assembly Language

Instruction Execution Interrupts

Instruction Cycle

Fetch
1.

2.
3.

Fetch an instruction from memory Decode the instruction to determine the operation Fetch data from memory if necessary

Execute
4. 5.

Perform the operation on the data Store the result in memory if needed

Contd..

Internal CPU Registers:

Program Counter (PC) = Address of instruction Instruction Register (IR) = Instruction being executed Accumulator (AC) = Temporary Storage

Contd..

Fetch the instruction from the memory Address in the Program Counter register Program Counter (PC) holds address of next instruction to fetch Increment the Program Counter Unless told otherwise Instruction loaded into Instruction Register (IR) Decode the type of instruction Fetch the operands Execute the instruction Store the results

Example Program Execution

Instruction Execution Cycle


PC I-1 op1 op2 Program (RAM) I-2 I-3 I-4 fetch Data (RAM) registers I-1

Instruction Queue decode

ALU execute store the output

Instruction Cycle State Diagram

Interrupts
Changing Program Flow

Interrupts

Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program

e.g. overflow, division by zero

Timer

Generated by internal processor timer Used in pre-emptive multi-tasking


from I/O controller e.g. memory parity error

I/O

Hardware failure

Interrupt Cycle

Added to instruction cycle Processor checks for interrupt

Indicated by an interrupt signal

If no interrupt, fetch next instruction If interrupt pending:


Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program

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Transfer of Control via Interrupts

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Instruction Cycle with Interrupts

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Instruction Cycle (with Interrupts) - State Diagram

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Multiple Interrupts

Disable interrupts

Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur

Define priorities

Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt

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Multiple Interrupts - Sequential

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Multiple Interrupts Nested

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Program Flow Control

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References

Chapter 1, Ytha Yu and Charles Marut, Assembly Language Programming and Organization of IBM PC Chapter 3, William Stallings, Computer Organization & Architecture

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