African Physical Review (2008) 2 Special Issue (Microelectronics): 0040

85

Design of an Operational Trans-conductance Amplifier in CMOS Technology With a 114 dB Gain and a Settling Time of 2.97ns

Djeghader Redouane and Pr. Nour Eddine Bougachel IC Design Lab., Universit Hadj Lakhdar, Batna, Algerie

1.

Introduction

The operational Amplifier (Op-Amp) is the key element which determines the overall performances of many analog and mixed circuits. However, to want a high DC gain assorted with a large band-width leads to contradictory design choices. The use of the gain enhanced technique to improve the output impedance [1] allows the possibility of decoupling the Gain/Band-width problem and makes the design of fast op-amps with a DC gain higher than 80dB possible. Fig. 1 presents a Fully Differential Folded Cascode OTA using two sub Op-Amps to improve DC gain. Ideally, except for the multiplication by a factor A, the SOAs do not introduce any other modification to transfer function TF of the circuit. However, if the necessary precautions are not taken [2], a narrowly spaced pole-zero pair will be introduced, this doublet drastically effects the transient response of the Op-amp and the settling time will be substantially longer than expected. In the Sec. 2, we will describe the optimization method and the results obtained. 2. Main results

transistors compensated with a capacitor CCN and the other with P channel compensated with a capacitor CCP. We begin our optimization by imposing the equality CCN=CCP. This allows a fast estimation of ranges, which are most likely to produce the best results. Fig. 2a gives the transient response to an input step of 0.5V for some values of the compensation capacitors and Fig. 2b gives the settling time for the of the explored interval. Using the results of preceding simulation, we fixed CCN to 1.2pF and varied CCP. In Fig. 3a, we can now observe a reduction in the interval for which the settling time is the minimum. The third step in our optimization consisted in taking the other way around and fixing CCP to 0.3pF, while varying CCN. The Fig. 4a gives the variation of the settling time versus CCN.

The Op-Amp was conceived for a CMOS 0.35 m technology. It should be noted that for a good transient response the unit frequencies of the SOAs should be higher than the closed loop cut-off frequency -3dB of the circuit and for reasons of stability the unit frequencies of the SOAs must remain below the non dominating pole frequency of the main Op-Amp MOA [2]. This restricts the choice of the polarization currents of the secondary OpAmps and their compensation capacitors. Nevertheless, if the choice of the currents of polarization is restricted by the allowed power consumption, one can always trades the phase margin for the band-width. The selected structure imposes (for reasons of input common mode range ICMR) the use of two complementary SOAs one with N channel input

Fig.1: Simplified schematic of Fully Differential Folded Cascode OTA using two sub op-amps (SOA-N and SOAP) to boost the DC gain.

Figs. 4a and 4b give, respectively, the curve of the gain and the phase of the implemented Op-Amp. Table 1 summarizes its essential characteristics for CL=1F.

African Physical Review (2008) 2 Special Issue (Microelectronics): 0040

86

Table 1: Characteristics of the Op-Amp. DC Gain Phase Margin Settling Time 0.1% Power consumption 114 dB 58 2.97ns 39.6mW

3.

Conclusion

The optimization of the settling time of an Op-Amp of the type Fully Differential Folded Cascode OTA using the gain enhanced technique is presented.

1 ,1

6 ,0
1 ,0

Temps d'tablissement (ns)

CCP
0 ,9

5 ,5

(Volts)

0 ,8

5 ,0

Vout

Diff

0 ,7

4 ,5

0 ,6

C C P = C C N = 0 .2 p F C C P = C C N = 0 .9 p F CCP=C CN=2pF

4 ,0

0 ,5

S im u la t io n H S P I C E C C N = C C P E x tr a p o l a tio n p o l y n o m ia le
0 ,5 1 ,0 1 ,5 2 ,0 2 ,5 3 ,0

3 ,5
1 ,0 1 ,5 2 ,0 2 ,5 3 ,0 3 ,5 4 ,0 4 ,5

T e m p s (n s )

CC

(p F )

Fig.2: First step of optimisation (a) Transient response to an input step for several values of compensations capacitors CCN=CCP (b) Settling time 0.1%.
6 ,0

C C P = 0 .3 p F
1 ,0

5 ,5

Temps d'tablissemnt (ns)

C C N = 1 .2 p F

C C P = 0 .7 p F (Volts) C C P = 0 .2 p F

5 ,0

4 ,5

0 ,8

Vout

Diff

4 ,0

3 ,5

0 ,6

3 ,0 0 ,0 0 ,2 0 ,4 0 ,6

S im u l a tio n H S P IC E C C N = 1 .2 p F E x tr a p o la t io n p o ly n o m ia le
0 ,8 1 ,0 1 ,2 1 ,4 1 ,6 1 ,8 2 ,0

1 ,0

1 ,5

2 ,0

2 ,5

3 ,0

3 ,5

4 ,0

4 ,5

T e m p s (n s )

C C P (p F )

Fig.3: Second step of optimisation (a) Transient response to an input step for several value of compensation capacitor CCP (b) Settling time 0.1%.
1 ,0 1 0 6 ,0

1
5 ,5 1 ,0 0 5

H S P IC E S i m u la t io n s C C P = 0 .3 p F E x t r a p o l a tio n p o l y n o m ia l e

2 Temps d'tablissement (ns)

4 ,0 4 ,5 5 ,0

(Volts)

1 ,0 0 0

4 ,5

Diff

3
0 ,9 9 5

Vout

4 ,0

3 ,5

0 ,9 9 0

1 2 3

C C N = 5 0 fF C C N = 0 .3 p F C C N = 1 .2 p F

3 ,0

0 ,9 8 5 2 ,0 2 ,5 3 ,0 3 ,5

2 ,5 0 ,0 0 ,5 1 ,0 1 ,5 2 ,0 2 ,5 3 ,0 3 ,5

T im e (n s )

CCN

(p F )

Fig.4: Third step of optimisation (a) Transient response to an input step for several value of compensation capacitor CCN (b) Settling time 0.1%

Good transient behaviour is obtained and simulation with HSPICE estimates the settling time (0.1%) to be 2.97ns assorted with a DC gain of 114 dB and a unit frequency of about 704MHz for a double load of 1pF.

References

[1] B. J. Hosticka, IEEEs J. Solid-State Circuits 14, 1111 (1979). [2] K. Bult and G. J. Greelen, IEEEs J. SolidState Circuits 25, 1379 (1990).